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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-09-14 20:19:37 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-14 20:19:37 -0700 |
| commit | ca16943e9330a1a937438e72e26c1189cfe20c4a (patch) | |
| tree | bd9b364fcdffb41016854de9463b7ea301f259a7 | |
| parent | ce3beb8dccf645dd725e0bd495af160fbe56fa66 (diff) | |
| download | riscv-isa-manual-ca16943e9330a1a937438e72e26c1189cfe20c4a.zip riscv-isa-manual-ca16943e9330a1a937438e72e26c1189cfe20c4a.tar.gz riscv-isa-manual-ca16943e9330a1a937438e72e26c1189cfe20c4a.tar.bz2 | |
Hypervisor extension requires page-based address translation (#737)
| -rw-r--r-- | src/hypervisor.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index d53441e..f8c829b 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -27,7 +27,8 @@ implement the SBI for its VS-mode guest. The hypervisor extension depends on an ``I'' base integer ISA with 32 {\tt x} registers (RV32I or RV64I), not RV32E, which has only 16 {\tt x} registers. -CSR {\tt mtval} must not be hardwired to zero. +CSR {\tt mtval} must not be hardwired to zero, and +{\tt satp}.MODE must not be hardwired to Bare. The hypervisor extension is enabled by setting bit 7 in the {\tt misa} CSR, which corresponds to the letter H. |