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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-08-17 14:30:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-17 14:30:36 -0700 |
| commit | 3bf08168b2f84dc6e16a107fdf90be59586caf5d (patch) | |
| tree | 65a51bd5a10d310e266ccf2d425ad24d9fa7cfcf | |
| parent | 010606fbd227838a95e0caf2b9d6f43376d62329 (diff) | |
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Make explicit the priorities of synch. exceptions of H extension (#711)
* Make explicit the priorities of synch. exceptions of H extension
* "page guest-fault" -> "guest-page fault"
| -rw-r--r-- | src/hypervisor.tex | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index e6262a0..97c8615 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -2750,6 +2750,59 @@ Because TSR and TVM in {\tt mstatus} are intended to impact only S-mode (HS-mode), they are ignored for determining exceptions in VS-mode. \end{commentary} +\begin{table*}[htbp] +\begin{center} +\begin{tabular}{|l|r|l|} + \hline + Priority & Exception Code & Description \\ + \hline + {\em Highest} & 3 & Instruction address breakpoint \\ + \hline + & 12 & Instruction page fault \\ + \hline + & 20 & Instruction guest-page fault \\ + \hline + & 1 & Instruction access fault \\ + \hline + & 2 & Illegal instruction \\ + & 22 & Virtual instruction \\ + & 0 & Instruction address misaligned \\ + & 8, 9, 10, 11 & Environment call \\ + & 3 & Environment break \\ + & 3 & Load/Store/AMO address breakpoint \\ + \hline + {\em Optionally, these may have} + & 6 & Store/AMO address misaligned \\ + {\em lowest priority instead.} + & 4 & Load address misaligned \\ + \hline + & 15 & Store/AMO page fault \\ + & 13 & Load page fault \\ + \hline + & 23 & Store/AMO guest-page fault \\ + & 21 & Load guest-page fault \\ + \hline + & 7 & Store/AMO access fault \\ + & 5 & Load access fault \\ + \hline +\end{tabular} +\end{center} +\caption{% +Synchronous exception priority when the hypervisor extension is +implemented.% +} +\label{tab:HSyncExcPrio} +\end{table*} + +If an instruction raises multiple synchronous exceptions, the +decreasing priority order of Table~\ref{tab:HSyncExcPrio} indicates +which exception is taken and reported in {\tt mcause} or {\tt scause}. +A virtual instruction exception has the same priority as an illegal +instruction exception, and a guest-page fault has lower priority than +a corresponding page fault. + +\FloatBarrier + \subsection{Trap Entry} When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless |