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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-01 16:45:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-01 16:45:21 -0700 |
| commit | 3879ff36fd78d81665b2309fc33617364fec05c2 (patch) | |
| tree | e9c2def633c74b447a48fed9a4d0ee25b985faeb | |
| parent | 7560a84d9649a941472ff629b0099eb95be40cb9 (diff) | |
| download | riscv-isa-manual-3879ff36fd78d81665b2309fc33617364fec05c2.zip riscv-isa-manual-3879ff36fd78d81665b2309fc33617364fec05c2.tar.gz riscv-isa-manual-3879ff36fd78d81665b2309fc33617364fec05c2.tar.bz2 | |
Remove errant preface entry
| -rw-r--r-- | src/priv-preface.tex | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index e606aff..4b943a1 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -63,7 +63,6 @@ Additionally, the following compatible changes have been made since version and access-fault exceptions. \item PMP reset values are now platform-defined. \item An additional 48 optional PMP registers have been defined. -\item Designated \item Software breakpoint exceptions are permitted to write either 0 or the PC to {\em x}\/{\tt tval}. \item Clarified that bare S-mode need not support the SFENCE.VMA instruction. |