mstatus/hstatus GVA bit may be set for breakpoint traps

1 files changed, 6 insertions, 2 deletions

diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index f836232..2f946f2 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -322,7 +322,7 @@ HS-mode and U-mode.
 
 Field GVA (Guest Virtual Address) is written by the implementation
 whenever a trap is taken into HS-mode.
-For any trap (address misaligned,
+For any trap (breakpoint, address misaligned,
 access fault, page fault, or guest-page fault) that writes
 a guest virtual address to {\tt stval}, GVA is set to~1.
 For any other trap into HS-mode, GVA is set to~0.
@@ -332,6 +332,10 @@ For memory access traps, GVA is redundant with field SPV (the two bits are set
 the same) except when the explicit memory access of an HLV, HLVX, or HSV
 instruction causes a fault.
 In that case, SPV=0 but GVA=1.
+
+If an instruction address misaligned or breakpoint trap writes zero to
+{\tt stval} instead of the faulting virtual address, then GVA=0 even if
+SPV=1.
 \end{commentary}
 
 The VSBE bit is a \warl\ field that controls the endianness of explicit
@@ -2006,7 +2010,7 @@ virtualization mode V is set to MPV, unless MPP=3, in which case V remains 0.
 
 Field GVA (Guest Virtual Address) is written by the implementation
 whenever a trap is taken into M-mode.
-For any trap (address misaligned,
+For any trap (breakpoint, address misaligned,
 access fault, page fault, or guest-page fault) that writes
 a guest virtual address to {\tt mtval}, GVA is set to~1.
 For any other trap into M-mode, GVA is set to~0.