Add mconfigptr CSR (#697)

* Add Smdisc extension (i.e. mconfigptr CSR)

* mconfigptr may be hardwired to zero

* Add changelog entry for mconfigptr

* Fix mconfigptr preface entry

"points to the address of" implies an extra level of indirection.
Should be "points to" or "contains the address of"

3 files changed, 49 insertions, 0 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 0f00279..22cc7c6 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2259,6 +2259,52 @@ If the feature to return the faulting instruction bits is implemented, {\tt
 mtval} must also be able to hold all values less than $2^N$, where $N$ is the
 smaller of XLEN and ILEN.
 
+\subsection{Machine Configuration Pointer Register ({\tt mconfigptr})}
+
+{\tt mconfigptr} is an MXLEN-bit read-only CSR, formatted as shown in
+Figure~\ref{mconfigptrreg}, that holds the physical address of a configuration
+data structure.
+Software can traverse this data structure to discover information about
+the harts, the platform, and their configuration.
+
+\begin{figure}[h!]
+{\footnotesize
+\begin{center}
+\begin{tabular}{@{}J}
+\instbitrange{MXLEN-1}{0} \\
+\hline
+\multicolumn{1}{|c|}{\tt mconfigptr} \\
+\hline
+MXLEN \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{Machine Configuration Pointer register.}
+\label{mconfigptrreg}
+\end{figure}
+
+The pointer alignment in bits must be no smaller than the greatest supported
+MXLEN: i.e., if the greatest supported MXLEN is $8\times n$, then
+{\tt mconfigptr}[$\log_2n$-1:0] must be hardwired to zero.
+
+{\tt mconfigptr} must be implemented, but it may be hardwired to zero to
+indicate the configuration data structure does not exist or that an
+alternative mechanism must be used to locate it.
+
+\begin{commentary}
+The format and schema of the configuration data structure have yet to be standardized.
+\end{commentary}
+
+\begin{commentary}
+While {\tt mconfigptr} will simply be hardwired in some implementations, other
+implementations may provide a means to configure the value returned on CSR
+reads.
+For example, {\tt mconfigptr} might present the value of a memory-mapped
+register that is programmed by the platform or by M-mode software towards the
+beginning of the boot process.
+\end{commentary}
+
 \section{Machine-Level Memory-Mapped Registers}
 
 \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})}
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index 230a28d..67f7dae 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -287,6 +287,7 @@ Number    & Privilege & Name & Description \\
 \tt 0xF12 & MRO &\tt marchid     & Architecture ID. \\
 \tt 0xF13 & MRO &\tt mimpid      & Implementation ID. \\
 \tt 0xF14 & MRO &\tt mhartid     & Hardware thread ID. \\
+\tt 0xF15 & MRO &\tt mconfigptr  & Pointer to configuration data structure. \\
 \hline
 \multicolumn{4}{|c|}{Machine Trap Setup} \\
 \hline
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 210e4bd..d7e301b 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -53,6 +53,8 @@ Additionally, the following compatible changes have been made since version
 \item Removed the N extension.
 \item Defined the mandatory RV32-only CSR {\tt mstatush}, which contains
   most of the same fields as the upper 32 bits of RV64's {\tt mstatus}.
+\item Defined the mandatory CSR {\tt mconfigptr}, which if nonzero
+  contains the address of a configuration data structure.
 \item Permitted the unconditional delegation of less-privileged interrupts.
 \item Added optional big-endian and bi-endian support.
 \item Made priority of load/store/AMO address-misaligned exceptions