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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-14 19:27:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-14 19:27:49 -0700 |
| commit | 0bb2e920c9795f62730d4c1ef1b36bd8e415a0f2 (patch) | |
| tree | bfedcb2108b9682445f1196df22c7376a891287c | |
| parent | 7d43cefd17b4fde0f542125bd33d611061ed5245 (diff) | |
| download | riscv-isa-manual-0bb2e920c9795f62730d4c1ef1b36bd8e415a0f2.zip riscv-isa-manual-0bb2e920c9795f62730d4c1ef1b36bd8e415a0f2.tar.gz riscv-isa-manual-0bb2e920c9795f62730d4c1ef1b36bd8e415a0f2.tar.bz2 | |
State behavior of uncacheable accesses to cacheable locations
Related to forthcoming Svpbmt extension.
| -rw-r--r-- | src/machine.tex | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 430b6fc..eb8502a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -3232,6 +3232,19 @@ because they will be fixed as either uncached, read-only, hardware cache-coherent, or only accessed by one agent. \end{commentary} +If a PMA indicates non-cacheability, then accesses to that region must +be satisfied by the memory itself, not by any caches. + +\begin{commentary} +For implementations with a cacheability-control mechanism, the situation +may arise that a program uncacheably accesses a memory location that is +currently cache-resident. +In this situation, the cached copy must be ignored. +This constraint is necessary to prevent more-privileged modes' speculative +cache refills from affecting the behavior of less-privileged modes' +uncacheable accesses. +\end{commentary} + \subsection{Idempotency PMAs} Idempotency PMAs describe whether reads and writes to an address |