Update register name order

https://github.com/riscv/riscv-isa-manual/issues/1352

Signed-off-by: Kersten Richter <kersten@riscv.org>

1 files changed, 9 insertions, 9 deletions

diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index 636c3bf..e87fbdd 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -36,7 +36,7 @@ supervisor-level CSR descriptions.
 ====
 
 [[sstatus]]
-==== Supervisor Status Register (`sstatus`)
+==== Supervisor Status (`sstatus`) Register 
 
 The `sstatus` register is an SXLEN-bit read/write register formatted as
 shown in <<sstatusreg-rv32>> when SXLEN=32
@@ -176,7 +176,7 @@ of one endianness to execute user-mode programs of the opposite
 endianness.
 ====
 
-==== Supervisor Trap Vector Base Address Register (`stvec`)
+==== Supervisor Trap Vector Base Address(`stvec`)  Register 
 
 The `stvec` register is an SXLEN-bit read/write register that holds trap
 vector configuration, consisting of a vector base address (BASE) and a
@@ -217,7 +217,7 @@ supervisor-mode timer interrupt (see <<scauses>>)
 causes the `pc` to be set to BASE+`0x14`. Setting MODE=Vectored may
 impose a stricter alignment constraint on BASE.
 
-==== Supervisor Interrupt Registers (`sip` and `sie`)
+==== Supervisor Interrupt (`sip` and `sie`) Registers 
 
 The `sip` register is an SXLEN-bit read/write register containing
 information on pending interrupts, while `sie` is the corresponding
@@ -336,7 +336,7 @@ the counter values.
 The implementation must provide a facility for scheduling timer
 interrupts in terms of the real-time counter, `time`.
 
-==== Counter-Enable Register (`scounteren`)
+==== Counter-Enable (`scounteren`) Register 
 
 .Counter-enable register (`scounteren`)
 include::images/bytefield/scounteren.edn[]
@@ -364,7 +364,7 @@ access a counter if the corresponding bits in `scounteren` and
 `mcounteren` are both set.
 ====
 
-==== Supervisor Scratch Register (`sscratch`)
+==== Supervisor Scratch (`sscratch`) Register 
 
 The `sscratch` register is an SXLEN-bit read/write register, dedicated
 for use by the supervisor. Typically, `sscratch` is used to hold a
@@ -375,7 +375,7 @@ with a user register to provide an initial working register.
 .Supervisor Scratch Register
 include::images/bytefield/sscratch.edn[]
 
-==== Supervisor Exception Program Counter (`sepc`)
+==== Supervisor Exception Program Counter (`sepc`) Register
 
 `sepc` is an SXLEN-bit read/write register formatted as shown in
 <<epcreg>>. The low bit of `sepc` (`sepc[0]`) is always zero. On implementations that support only IALIGN=32, the two low bits (`sepc[1:0]`) are always zero.
@@ -402,7 +402,7 @@ though it may be explicitly written by software.
 include::images/bytefield/epcreg.edn[]
 
 [[scause]]
-==== Supervisor Cause Register (`scause`)
+==== Supervisor Cause (`scause`) Register 
 
 The `scause` register is an SXLEN-bit read-write register formatted as
 shown in <<scausereg>>. When a trap is taken into
@@ -583,7 +583,7 @@ instruction bits is implemented, `stval` must also be able to hold all
 values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller
 of SXLEN and ILEN.
 
-==== Supervisor Environment Configuration Register (`senvcfg`)
+==== Supervisor Environment Configuration (`senvcfg`) Register 
 
 The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as
 shown in <<senvcfg>>, that controls certain
@@ -2132,7 +2132,7 @@ QoS Register Interface (CBQRI) specification, which provides methods for setting
 resource usage limits and monitoring resource consumption. The `RCID` controls
 resource allocations, while the `MCID` is used for tracking resource usage.
 
-=== Supervisor Resource Management Configuration register
+=== Supervisor Resource Management Configuration (`srmcfg`) register
 
 The `srmcfg` register is an SXLEN-bit read/write register used to configure a
 Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`). Both `RCID`