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| author | Kersten Richter <kersten@riscv.org> | 2024-04-18 07:17:57 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-18 07:17:57 -0500 |
| commit | e825d9f423d16a0dd997c89883004319ec704af2 (patch) | |
| tree | 1bbf86e6f7a97058ebf78d93cd07083e34e910dd | |
| parent | ccc3d194faab5569e926720f4bf22a46f41580b3 (diff) | |
| download | riscv-isa-manual-e825d9f423d16a0dd997c89883004319ec704af2.zip riscv-isa-manual-e825d9f423d16a0dd997c89883004319ec704af2.tar.gz riscv-isa-manual-e825d9f423d16a0dd997c89883004319ec704af2.tar.bz2 | |
Update src/sscofpmf.adoc
Signed-off-by: Kersten Richter <kersten@riscv.org>
| -rw-r--r-- | src/sscofpmf.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc index 4d301d5..58f1bde 100644 --- a/src/sscofpmf.adoc +++ b/src/sscofpmf.adoc @@ -101,7 +101,7 @@ maintaining a bit mask reflecting which counters are active and due to eventually overflow. ==== -=== Supervisor Count Overflow (scountovf) Register +=== Supervisor Count Overflow (`scountovf`) Register This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of |