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| author | Kersten Richter <kersten@riscv.org> | 2024-04-18 07:22:23 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-18 07:22:23 -0500 |
| commit | aa4a25cf6831cc962dbc72587a1804aaf8290aae (patch) | |
| tree | 38d0d387943f7f8e2de05829602b31a8b6e428b9 | |
| parent | be4662576c82c47ec4334221e1d2d195e9061af1 (diff) | |
| download | riscv-isa-manual-aa4a25cf6831cc962dbc72587a1804aaf8290aae.zip riscv-isa-manual-aa4a25cf6831cc962dbc72587a1804aaf8290aae.tar.gz riscv-isa-manual-aa4a25cf6831cc962dbc72587a1804aaf8290aae.tar.bz2 | |
Update src/supervisor.adoc
Signed-off-by: Kersten Richter <kersten@riscv.org>
| -rw-r--r-- | src/supervisor.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index e87fbdd..5b93c53 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -176,7 +176,7 @@ of one endianness to execute user-mode programs of the opposite endianness. ==== -==== Supervisor Trap Vector Base Address(`stvec`) Register +==== Supervisor Trap Vector Base Address (`stvec`) Register The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a |