Merge pull request #1344 from ved-rivos/jvt

Use lower case for jvt  CSR name

2 files changed, 21 insertions, 21 deletions

diff --git a/src/smstateen.adoc b/src/smstateen.adoc
index f0fdea0..e037720 100644
--- a/src/smstateen.adoc
+++ b/src/smstateen.adoc
@@ -247,7 +247,7 @@ floating-point instructions cause an illegal instruction trap (or virtual
 instruction trap, if relevant), as though they all access `fcsr`, regardless of
 whether they really do.
 
-The JVT bit controls access to the `JVT` CSR provided by the Zcmt extension.
+The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension.
 
 The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`,
 and the `sstateen0` CSRs. The SE0 bit in `hstateen0` controls access to the
diff --git a/src/zc.adoc b/src/zc.adoc
index 5bbac90..ac55345 100644
--- a/src/zc.adoc
+++ b/src/zc.adoc
@@ -272,7 +272,7 @@ The PUSH/POP assembly syntax uses several variables, the meaning of which are:
 [#Zcmt]
 === Zcmt
 
-Zcmt adds the table jump instructions and also adds the JVT CSR. The JVT CSR requires a 
+Zcmt adds the table jump instructions and also adds the jvt CSR. The jvt CSR requires a 
 state enable if Smstateen is implemented. See <<csrs-jvt>> for details.
 
 This extension reuses some encodings from _c.fsdsp_.  Therefore it is _incompatible_ with <<Zcd>>,
@@ -2356,9 +2356,9 @@ Table jump allows the linker to replace the following instruction sequences with
 
 If a return address stack is implemented, then as _cm.jalt_ is equivalent to _jal ra_, it pushes to the stack.
 
-==== JVT
+==== jvt
 
-The base of the table is in the JVT CSR (see <<csrs-jvt>>), each table entry is XLEN bits.
+The base of the table is in the jvt CSR (see <<csrs-jvt>>), each table entry is XLEN bits.
 
 If the same function is called with and without linking then it must have two entries in the table. 
 This is typically caused by the same function being called with and without tail calling.
@@ -2379,8 +2379,8 @@ if the tables have not been updated in memory since the last _fence.i_.
 If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction,  xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.
 
 <<<
-[#csrs-jvt,reftext="JVT CSR, table jump base vector and control register"]
-==== JVT CSR
+[#csrs-jvt,reftext="jvt CSR, table jump base vector and control register"]
+==== jvt CSR
 
 Synopsis:
 
@@ -2416,24 +2416,24 @@ Format (RV64):
 
 Description:
 
-The _JVT_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).
+The _jvt_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).
 
-If <<Zcmt>> is implemented then _JVT_ must also be implemented, but can contain a read-only value. If _JVT_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary.
+If <<Zcmt>> is implemented then _jvt_ must also be implemented, but can contain a read-only value. If _jvt_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary.
 
-_JVT.base_ is a virtual address, whenever virtual memory is enabled.
+_jvt.base_ is a virtual address, whenever virtual memory is enabled.
 
-The memory pointed to by _JVT.base_ is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission. 
+The memory pointed to by _jvt.base_ is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission. 
 
 [#JVT-config-table]
-._JVT.mode_ definition
+._jvt.mode_ definition
 [width="60%",options=header]
 |=============================================================================================
-| JVT.mode | Comment
+| jvt.mode | Comment
 | 000000 | Jump table mode
 | others | *reserved for future standard use*
 |=============================================================================================
 
-_JVT.mode_ is a *WARL* field, so can only be programmed to modes which are implemented. Therefore the discovery mechanism is to 
+_jvt.mode_ is a *WARL* field, so can only be programmed to modes which are implemented. Therefore the discovery mechanism is to 
 attempt to program different modes and read back the values to see which are available. Jump table mode _must_ be implemented.
 
 [NOTE]
@@ -2443,11 +2443,11 @@ in future the RISC-V Unified Discovery method will report the available modes.
 
 Architectural State:
 
-_JVT_ adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. 
+_jvt_ CSR adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. 
 
 State Enable:
 
-If the Smstateen extension is implemented, then bit 2 in _mstateen0_, _sstateen0_, and _hstateen0_ is implemented.  If bit 2 of a controlling _stateen0_ CSR is zero, then access to the _JVT_ CSR and execution of a _cm.jalt_ or _cm.jt_ instruction by a lower privilege level results in an Illegal Instruction trap (or, if appropriate, a Virtual Instruction trap).
+If the Smstateen extension is implemented, then bit 2 in _mstateen0_, _sstateen0_, and _hstateen0_ is implemented.  If bit 2 of a controlling _stateen0_ CSR is zero, then access to the _jvt_ CSR and execution of a _cm.jalt_ or _cm.jt_ instruction by a lower privilege level results in an Illegal Instruction trap (or, if appropriate, a Virtual Instruction trap).
 
 <<<
 [#insns-cm_jt,reftext="Jump via table"]
@@ -2480,7 +2480,7 @@ For this encoding to decode as _cm.jt_, _index<32_, otherwise it decodes as _cm.
 
 [NOTE]
 ====
-If JVT.mode = 0 (Jump Table Mode) then _cm.jt_ behaves as specified here. If JVT.mode is a reserved value, then _cm.jt_ is also reserved. In the future other defined values of JVT.mode may change the behaviour of _cm.jt_.
+If jvt.mode = 0 (Jump Table Mode) then _cm.jt_ behaves as specified here. If jvt.mode is a reserved value, then _cm.jt_ is also reserved. In the future other defined values of jvt.mode may change the behaviour of _cm.jt_.
 ====
 
 Assembly Syntax:
@@ -2517,8 +2517,8 @@ Operation:
 # InstMemory is byte indexed
 
 switch(XLEN) {
-  32:  table_address[XLEN-1:0] = JVT.base + (index<<2);
-  64:  table_address[XLEN-1:0] = JVT.base + (index<<3);
+  32:  table_address[XLEN-1:0] = jvt.base + (index<<2);
+  64:  table_address[XLEN-1:0] = jvt.base + (index<<3);
 }
 
 //fetch from the jump table
@@ -2559,7 +2559,7 @@ For this encoding to decode as _cm.jalt_, _index>=32_, otherwise it decodes as _
 
 [NOTE]
 ====
-If JVT.mode = 0 (Jump Table Mode) then _cm.jalt_ behaves as specified here. If JVT.mode is a reserved value, then _cm.jalt_ is also reserved. In the future other defined values of JVT.mode may change the behaviour of _cm.jalt_.
+If jvt.mode = 0 (Jump Table Mode) then _cm.jalt_ behaves as specified here. If jvt.mode is a reserved value, then _cm.jalt_ is also reserved. In the future other defined values of jvt.mode may change the behaviour of _cm.jalt_.
 ====
 
 Assembly Syntax:
@@ -2596,8 +2596,8 @@ Operation:
 # InstMemory is byte indexed
 
 switch(XLEN) {
-  32:  table_address[XLEN-1:0] = JVT.base + (index<<2);
-  64:  table_address[XLEN-1:0] = JVT.base + (index<<3);
+  32:  table_address[XLEN-1:0] = jvt.base + (index<<2);
+  64:  table_address[XLEN-1:0] = jvt.base + (index<<3);
 }
 
 //fetch from the jump table