Update sstc.adoc

Signed-off-by: Kersten Richter <kersten@riscv.org>

1 files changed, 51 insertions, 51 deletions

diff --git a/src/sstc.adoc b/src/sstc.adoc
index 5c72ada..fe8d8f6 100644
--- a/src/sstc.adoc
+++ b/src/sstc.adoc
@@ -27,15 +27,15 @@ and the VS-level vstimecmp CSR.
 
 === Machine and Supervisor Level Additions
 
-==== Supervisor Timer (stimecmp) Register 
+==== Supervisor Timer (`stimecmp`) Register 
 
 This extension adds this new CSR.
 
-The stimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and
-RV64 systems. In RV32 only, accesses to the stimecmp CSR access the low 32
-bits, while accesses to the stimecmph CSR access the high 32 bits of stimecmp.
+The `stimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and
+RV64 systems. In RV32 only, accesses to the `stimecmp` CSR access the low 32
+bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp`.
 
-The CSR numbers for stimecmp / stimecmph are 0x14D / 0x15D (within the
+The CSR numbers for `stimecmp` / `stimecmph` are 0x14D / 0x15D (within the
 Supervisor Trap Setup block of CSRs).
 
 A supervisor timer interrupt becomes pending - as reflected in the STIP bit in
@@ -49,7 +49,7 @@ based on the standard interrupt enable and delegation rules.
 [NOTE]
 ====
 A spurious timer interrupt might occur if an interrupt handler advances
-stimecmp then immediately returns, because STIP might not yet have fallen in
+`stimecmp` then immediately returns, because STIP might not yet have fallen in
 the interim. All software should be written to assume this event is possible,
 but most software should assume this event is extremely unlikely. It is almost
 always more performant to incur an occasional spurious timer interrupt than to
@@ -66,7 +66,7 @@ existing S-mode software that uses this SEE facility, while new S-mode software
 takes advantage of stimecmp directly.)
 ====
 
-==== Machine Interrupt (mip and mie) Registers 
+==== Machine Interrupt (`mip` and `mie`) Registers 
 
 This extension modifies the description of the STIP/STIE bits in these
 registers as follows:
@@ -75,60 +75,60 @@ If supervisor mode is implemented, its mip.STIP and mie.STIE are the
 interrupt-pending and interrupt-enable bits for supervisor-level timer
 interrupts. If the stimecmp register is not implemented, STIP is writable in
 mip, and may be written by M-mode software to deliver timer interrupts to
-S-mode. If the stimecmp (supervisor-mode timer compare) register is
+S-mode. If the `stimecmp` (supervisor-mode timer compare) register is
 implemented, STIP is read-only in mip and reflects the supervisor-level timer
 interrupt signal resulting from stimecmp. This timer interrupt signal is
-cleared by writing stimecmp with a value greater than the current time value.
+cleared by writing `stimecmp` with a value greater than the current time value.
 
-==== Supervisor Interrupt (sip and sie) Registers 
+==== Supervisor Interrupt (`sip` and `sie`) Registers 
 
 This extension modifies the description of the STIP/STIE bits in these
 registers as follows:
 
-Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits
+Bits `sip.STIP` and `sie.STIE` are the interrupt-pending and interrupt-enable bits
 for supervisor level timer interrupts. If implemented, STIP is read-only in
-sip, and is either set and cleared by the execution environment (if stimecmp is
+sip, and is either set and cleared by the execution environment (if `stimecmp` is
 not implemented), or reflects the timer interrupt signal resulting from
-stimecmp (if stimecmp is implemented). The sip.STIP bit, in response to timer
-interrupts generated by stimecmp, is set and cleared by writing stimecmp with a
+`stimecmp` (if `stimecmp` is implemented). The sip.STIP bit, in response to timer
+interrupts generated by `stimecmp`, is set and cleared by writing `stimecmp` with a
 value that respectively is less than or equal to, or greater than, the current
 time value.
 
-==== Machine Counter-Enable (mcounteren) Register 
+==== Machine Counter-Enable (`mcounteren`) Register 
 
 This extension adds to the description of the TM bit in this register as
 follows:
 
 In addition, when the TM bit in the mcounteren register is clear, attempts to
-access the stimecmp or vstimecmp register while executing in a mode less
+access the `stimecmp` or `vstimecmp` register while executing in a mode less
 privileged than M will cause an illegal instruction exception.  When this bit
-is set, access to the stimecmp or vstimecmp register is permitted in S-mode if
-implemented, and access to the vstimecmp register (via stimecmp) is permitted
+is set, access to the `stimecmp` or `vstimecmp` register is permitted in S-mode if
+implemented, and access to the `vstimecmp` register (via `stimecmp`) is permitted
 in VS-mode if implemented and not otherwise prevented by the TM bit in
-hcounteren.
+`hcounteren`.
 
 === Hypervisor Extension Additions
 
-==== Virtual Supervisor Timer (vstimecmp) Register 
+==== Virtual Supervisor Timer (`vstimecmp`) Register 
 
 This extension adds this new CSR.
 
-The vstimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and
-RV64 systems. In RV32 only, accesses to the vstimecmp CSR access the low 32
-bits, while accesses to the vstimecmph CSR access the high 32 bits of
+The `vstimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and
+RV64 systems. In RV32 only, accesses to the `vstimecmp` CSR access the low 32
+bits, while accesses to the `vstimecmph` CSR access the high 32 bits of
 vstimecmp.
 
-The proposed CSR numbers for vstimecmp / vstimecmph are 0x24D / 0x25D (within
+The proposed CSR numbers for `vstimecmp` / `vstimecmph` are 0x24D / 0x25D (within
 the Virtual Supervisor Registers block of CSRs, and mirroring the CSR numbers
 for stimecmp/stimecmph).
 
 A virtual supervisor timer interrupt becomes pending - as reflected in the
-VSTIP bit in the hip register - whenever (time + htimedelta), truncated to 64
-bits, contains a value greater than or equal to vstimecmp, treating the values
-as unsigned integers. Writes to vstimecmp and htimedelta are guaranteed to be
+VSTIP bit in the `hip` register - whenever (`time` + `htimedelta`), truncated to 64
+bits, contains a value greater than or equal to `vstimecmp`, treating the values
+as unsigned integers. Writes to `vstimecmp` and `htimedelta` are guaranteed to be
 reflected in VSTIP eventually, but not necessarily immediately. The interrupt
-remains posted until vstimecmp becomes greater than (time + htimedelta) -
-typically as a result of writing vstimecmp. The interrupt will be taken based
+remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`) -
+typically as a result of writing `vstimecmp`. The interrupt will be taken based
 on the standard interrupt enable and delegation rules while V=1.
 
 [NOTE]
@@ -141,7 +141,7 @@ ensures compatibility with existing guest VS-mode software that uses this SEE
 facility, while new VS-mode software takes advantage of vstimecmp directly.)
 ====
 
-==== Hypervisor Interrupt (hvip, hip, and hie) Registers 
+==== Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers 
 
 This extension modifies the description of the VSTIP/VSTIE bits in the hip/hie
 registers as follows:
@@ -149,39 +149,39 @@ registers as follows:
 Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enable
 bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the
 logical-OR of hvip.VSTIP and the timer interrupt signal resulting from
-vstimecmp (if vstimecmp is implemented). The hip.VSTIP bit, in response to
-timer interrupts generated by vstimecmp, is set and cleared by writing
-vstimecmp with a value that respectively is less than or equal to, or greater
-than, the current (time + htimedelta) value. The hip.VSTIP bit remains defined
+vstimecmp (if `vstimecmp` is implemented). The hip.VSTIP bit, in response to
+timer interrupts generated by `vstimecmp`, is set and cleared by writing
+`vstimecmp` with a value that respectively is less than or equal to, or greater
+than, the current (`time` + `htimedelta`) value. The hip.VSTIP bit remains defined
 while V=0 as well as V=1.
 
-==== Hypervisor Counter-Enable (hcounteren) Register 
+==== Hypervisor Counter-Enable (`hcounteren`) Register 
 
 This extension adds to the description of the TM bit in this register as
 follows:
 
-In addition, when the TM bit in the hcounteren register is clear, attempts to
-access the vstimecmp register (via stimecmp) while executing in VS-mode will
-cause a virtual instruction exception if the same bit in mcounteren is set.
-When this bit and the same bit in mcounteren are both set, access to the
-vstimecmp register (if implemented) is permitted in VS-mode.
+In addition, when the TM bit in the `hcounteren` register is clear, attempts to
+access the `vstimecmp` register (via stimecmp) while executing in VS-mode will
+cause a virtual instruction exception if the same bit in `mcounteren` is set.
+When this bit and the same bit in `mcounteren` are both set, access to the
+`vstimecmp` register (if implemented) is permitted in VS-mode.
 
-=== Environment Config (menvcfg/henvcfg) Support
+=== Environment Config (`menvcfg` or `henvcfg`) Support
 
-Enable/disable bits for this extension are provided in the new menvcfg /
-henvcfg CSRs.
+Enable/disable bits for this extension are provided in the new `menvcfg` /
+`henvcfg` CSRs.
 
-Bit 63 of menvcfg (or bit 31 of menvcfgh) - named STCE (STimecmp Enable) -
-enables stimecmp for S-mode when set to one, and the same bit of henvcfg
-enables vstimecmp for VS-mode. These STCE bits are WARL and are hard-wired to 0
+Bit 63 of `menvcfg` (or bit 31 of `menvcfgh`) - named STCE (STimecmp Enable) -
+enables `stimecmp` for S-mode when set to one, and the same bit of henvcfg
+enables `vstimecmp` for VS-mode. These STCE bits are WARL and are hard-wired to 0
 when this extension is not implemented.
 
-When this extension is implemented and STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a
-mode other than M-mode raises an illegal instruction exception, STCE in henvcfg
-is read-only zero, and STIP in mip and sip reverts to its defined behavior as
+When this extension is implemented and STCE in `menvcfg` is zero, an attempt to access `stimecmp` or `vstimecmp` in a
+mode other than M-mode raises an illegal instruction exception, STCE in `henvcfg`
+is read-only zero, and STIP in `mip` and `sip` reverts to its defined behavior as
 if this extension is not implemented. Further, if the H extension is implemented, then hip.VSTIP also reverts its defined behavior as if this extension is not implemented.
 
-But when STCE in menvcfg is one and STCE in henvcfg is zero, an attempt to access
-stimecmp (really vstimecmp) when V = 1 raises a virtual instruction exception,
+But when STCE in `menvcfg` is one and STCE in `henvcfg` is zero, an attempt to access
+`stimecmp` (really `vstimecmp`) when V = 1 raises a virtual instruction exception,
 and VSTIP in hip reverts to its defined behavior as if this extension is not
 implemented.