Update hypervisor.adoc

Signed-off-by: Kersten Richter <kersten@riscv.org>

1 files changed, 31 insertions, 31 deletions

diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc
index d0edb9b..09d70a2 100644
--- a/src/hypervisor.adoc
+++ b/src/hypervisor.adoc
@@ -158,7 +158,7 @@ In this chapter, we use the term _HSXLEN_ to refer to the effective XLEN
 when executing in HS-mode, and _VSXLEN_ to refer to the effective XLEN
 when executing in VS-mode.
 
-==== Hypervisor Status Register (`hstatus`)
+==== Hypervisor Status (`hstatus`) Register 
 
 The `hstatus` register is an HSXLEN-bit read/write register formatted as
 shown in <<hstatusreg-rv32>> when HSXLEN=32
@@ -270,7 +270,7 @@ to VS-level memory management data structures, such as page tables. An
 implementation may make VSBE a read-only field that always specifies the
 same endianness as HS-mode.
 
-==== Hypervisor Trap Delegation Registers (`hedeleg` and `hideleg`)
+==== Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers 
 
 Register `hedeleg` is a 64-bit read/write register, formatted as shown in
 <<hedelegreg>>.
@@ -396,7 +396,7 @@ Store/AMO guest-page fault
 |===
 
 [[hinterruptregs]]
-==== Hypervisor Interrupt Registers (`hvip`, `hip`, and `hie`)
+==== Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers 
 
 Register `hvip` is an HSXLEN-bit read/write register that a hypervisor
 can write to indicate virtual interrupts intended for VS-mode. Bits of
@@ -643,7 +643,7 @@ When XLEN=32, `henvcfgh` is a
 of `henvcfg`. Register `henvcfgh` does not exist when
 XLEN=64.
 
-==== Hypervisor Counter-Enable Register (`hcounteren`)
+==== Hypervisor Counter-Enable (`hcounteren`) Register 
 
 The counter-enable register `hcounteren` is a 32-bit register that
 controls the availability of the hardware performance monitoring
@@ -665,7 +665,7 @@ readable unless the applicable bits are set in both `hcounteren` and
 read-only zero, indicating reads to the corresponding counter will cause
 an exception when V=1. Hence, they are effectively *WARL* fields.
 
-==== Hypervisor Time Delta Register (`htimedelta`)
+==== Hypervisor Time Delta (`htimedelta`) Register 
 
 The `htimedelta` CSR is a 64-bit read/write register that contains the delta
 between the value of the `time` CSR and the value returned in VS-mode or
@@ -685,7 +685,7 @@ When XLEN=32, `htimedeltah` is a 32-bit read/write register
 that aliases bits 63:32 of `htimedelta`.
 Register `htimedeltah` does not exist when XLEN=64.
 
-==== Hypervisor Trap Value Register (`htval`)
+==== Hypervisor Trap Value (`htval`) Register 
 
 The `htval` register is an HSXLEN-bit read/write register formatted as
 shown in <<htvalreg>>. When a trap is taken into
@@ -746,7 +746,7 @@ software that writes a value to `htval` should read back from `htval` to
 confirm the stored value.
 ====
 
-==== Hypervisor Trap Instruction Register (`htinst`)
+==== Hypervisor Trap Instruction (`htinst`) Register 
 
 The `htinst` register is an HSXLEN-bit read/write register formatted as
 shown in <<htinstreg>>. When a trap is taken into
@@ -756,14 +756,14 @@ handling the trap. The values that may be written to `htinst` on a trap
 are documented in <<tinst-vals>>.
 
 [[htinstreg]]
-.Hypervisor trap instruction register (`htinst`).
+.Hypervisor trap instruction (`htinst`) register.
 include::images/bytefield/htinstreg.edn[]
 
 `htinst` is a *WARL* register that need only be able to hold the values that
 the implementation may automatically write to it on a trap.
 
 [[hgatp]]
-==== Hypervisor Guest Address Translation and Protection Register (`hgatp`)
+==== Hypervisor Guest Address Translation and Protection (`hgatp`) Register 
 
 The `hgatp` register is an HSXLEN-bit read/write register, formatted as
 shown in <<rv32hgatp>> for HSXLEN=32 and
@@ -883,7 +883,7 @@ modified, or if a VMID is reused, it may be necessary to execute an
 HFENCE.GVMA instruction (see <<hfence.vma>>) before or
 after writing `hgatp`.
 
-==== Virtual Supervisor Status Register (`vsstatus`)
+==== Virtual Supervisor Status (`vsstatus`) Register 
 
 The `vsstatus` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `sstatus`, formatted as shown
@@ -893,11 +893,11 @@ in <<vsstatusreg-rv32>> when VSXLEN=32 and
 normally read or modify `sstatus` actually access `vsstatus` instead.
 
 [[vsstatusreg-rv32]]
-.Virtual supervisor status register (`vstatus`) when VSXLEN=32.
+.Virtual supervisor status (`vstatus`)register when VSXLEN=32.
 include::images/bytefield/vsstatusreg-rv32.edn[]
 
 [[vsstatusreg]]
-.Virtual supervisor status register (`vsstatus`) when VSXLEN=64.
+.Virtual supervisor status (`vsstatus`) register when VSXLEN=64.
 include::images/bytefield/vsstatusreg.edn[]
 
 The UXL field controls the effective XLEN for VU-mode, which may differ
@@ -945,7 +945,7 @@ machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the
 MPRV feature in the `mstatus` register is used to execute a load or
 store _as though_ V=1.
 
-==== Virtual Supervisor Interrupt Registers (`vsip` and `vsie`)
+==== Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers 
 
 The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that
 are VS-mode’s versions of supervisor CSRs `sip` and `sie`, formatted as
@@ -996,7 +996,7 @@ When bit 2 of `hideleg` is zero, `vsip`.SSIP and `vsie`.SSIE are
 read-only zeros. Else, `vsip`.SSIP and `vsie`.SSIE are aliases of
 `hip`.VSSIP and `hie`.VSSIE.
 
-==== Virtual Supervisor Trap Vector Base Address Register (`vstvec`)
+==== Virtual Supervisor Trap Vector Base Address (`vstvec`) Register
 
 The `vstvec` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `stvec`, formatted as shown in
@@ -1009,7 +1009,7 @@ affect the behavior of the machine.
 .Virtual supervisor trap vector base address register `vstvec`.
 include::images/bytefield/vstvecreg.edn[]
 
-==== Virtual Supervisor Scratch Register (`vsscratch`)
+==== Virtual Supervisor Scratch (`vsscratch`) Register
 
 The `vsscratch` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `sscratch`, formatted as shown
@@ -1022,7 +1022,7 @@ of `vsscratch` never directly affect the behavior of the machine.
 .Virtual supervisor scratch register `vsscratch`.
 include::images/bytefield/vsscratchreg.edn[]
 
-==== Virtual Supervisor Exception Program Counter (`vsepc`)
+==== Virtual Supervisor Exception Program Counter (`vsepc`) Register
 
 The `vsepc` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `sepc`, formatted as shown in
@@ -1038,7 +1038,7 @@ that `sepc` can hold.
 .Virtual supervisor exception program counter (`vsepc`).
 include::images/bytefield/vsepcreg.edn[]
 
-==== Virtual Supervisor Cause Register (`vscause`)
+==== Virtual Supervisor Cause (`vscause`) Register
 
 The `vscause` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `scause`, formatted as shown in
@@ -1054,7 +1054,7 @@ values that `scause` can hold.
 .Virtual supervisor cause register (`vscause`).
 include::images/bytefield/vscausereg.edn[]
 
-==== Virtual Supervisor Trap Value Register (`vstval`)
+==== Virtual Supervisor Trap Value (`vstval`) Register
 
 The `vstval` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `stval`, formatted as shown in
@@ -1070,7 +1070,7 @@ that `stval` can hold.
 .Virtual supervisor trap value register (`vstval`).
 include::images/bytefield/vstvalreg.edn[]
 
-==== Virtual Supervisor Address Translation and Protection Register (`vsatp`)
+==== Virtual Supervisor Address Translation and Protection (`vsatp`) Register
 
 The `vsatp` register is a VSXLEN-bit read/write register that is
 VS-mode’s version of supervisor register `satp`, formatted as shown in
@@ -1082,11 +1082,11 @@ for guest virtual addresses (see
 <<two-stage-translation>>).
 
 [[rv32vsatpreg]]
-.Virtual supervisor address translation and protection register `vsatp` when VSXLEN=32.
+.Virtual supervisor address translation and protection `vsatp` register when VSXLEN=32.
 include::images/bytefield/rv32vsatpreg.edn[]
 
 [[rv64vsatpreg]]
-.Virtual supervisor address translation and protection register `vsatp` when VSXLEN=64.
+.Virtual supervisor address translation and protection `vsatp` register when VSXLEN=64.
 include::images/bytefield/rv64vsatpreg.edn[]
 
 The `vsatp` register is considered _active_ for the purposes of the
@@ -1290,7 +1290,7 @@ The hypervisor extension augments or modifies machine CSRs `mstatus`,
 `mstatush`, `mideleg`, `mip`, and `mie`, and adds CSRs `mtval2` and
 `mtinst`.
 
-==== Machine Status Registers (`mstatus` and `mstatush`)
+==== Machine Status (`mstatus` and `mstatush`) Registers
 
 The hypervisor extension adds two fields, MPV and GVA, to the
 machine-level `mstatus` or `mstatush` CSR, and modifies the behavior of
@@ -1304,11 +1304,11 @@ to `mstatus` but to `mstatush`.
 MXLEN=32.
 
 [[hypervisor-mstatus]]
-.Machine status register (`mstatus`) fpr RV64 when the hypervisor extension is implemented.
+.Machine status (`mstatus`) register for RV64 when the hypervisor extension is implemented.
 include::images/bytefield/hypv-mstatus.edn[]
 
 [[hypervisor-mstatush]]
-.Additional machine status register (`mstatush`) for RV32 when the hypervisor extension is implemented.  The format of `mstatus` is unchanged for RV32.
+.Additional machine status (`mstatush`) register for RV32 when the hypervisor extension is implemented.  The format of `mstatus` is unchanged for RV32.
 include::images/bytefield/hypv-mstatush.edn[]
 
 The MPV bit (Machine Previous Virtualization Mode) is written by the
@@ -1398,7 +1398,7 @@ always act as though V=1 and the nominal privilege mode were
 The `mstatus` register is a superset of the HS-level `sstatus` register
 but is not a superset of `vsstatus`.
 
-==== Machine Interrupt Delegation Register (`mideleg`)
+==== Machine Interrupt Delegation (`mideleg`) Register
 
 When the hypervisor extension is implemented, bits 10, 6, and 2 of
 `mideleg` (corresponding to the standard VS-level interrupts) are each
@@ -1411,9 +1411,9 @@ past M-mode to HS-mode.
 For bits of `mideleg` that are zero, the corresponding bits in
 `hideleg`, `hip`, and `hie` are read-only zeros.
 
-==== Machine Interrupt Registers (`mip` and `mie`)
+==== Machine Interrupt (`mip` and `mie`) Registers
 
-The hypervisor extension gives registers `mip` and `mie` additional
+The hypervisor extension allows registers `mip` and `mie` additional
 active bits for the hypervisor-added interrupts. <<hypervisor-mipreg-standard>> and <<hypervisor-miereg-standard>> show the
 standard portions (bits 15:0) of registers `mip` and `mie` when the
 hypervisor extension is implemented.
@@ -1430,7 +1430,7 @@ Bits SGEIP, VSEIP, VSTIP, and VSSIP in `mip` are aliases for the same
 bits in hypervisor CSR `hip`, while SGEIE, VSEIE, VSTIE, and VSSIE in
 `mie` are aliases for the same bits in `hie`.
 
-==== Machine Second Trap Value Register (`mtval2`)
+==== Machine Second Trap Value (`mtval2`) Register
 
 The `mtval2` register is an MXLEN-bit read/write register formatted as
 shown in <<mtval2reg>>. When a trap is taken into
@@ -1464,7 +1464,7 @@ the instruction as indicated by the virtual address in `mtval`.
 capable of holding only an arbitrary subset of other 2-bit-shifted guest
 physical addresses, if any.
 
-==== Machine Trap Instruction Register (`mtinst`)
+==== Machine Trap Instruction (`mtinst`) Register
 
 The `mtinst` register is an MXLEN-bit read/write register formatted as
 shown in <<mtinstreg>>. When a trap is taken into
@@ -1474,7 +1474,7 @@ handling the trap. The values that may be written to `mtinst` on a trap
 are documented in <<tinst-vals>>.
 
 [[mtinstreg]]
-.Machine trap instruction register (`mtinst`).
+.Machine trap instruction (`mtinst`) register.
 include::images/bytefield/mtinstreg.edn[]
 
 `mtinst` is a *WARL* register that need only be able to hold the values that
@@ -2175,7 +2175,7 @@ earlier.
 <<<
 
 [[tinst-values]]
-.Values that may be automatically written to the trap instruction register (`mtinst` or `htinst`) on an exception trap.
+.Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap.
 [float="center",align="center",cols="2,^,^,^,^",options="header"]
 |===
 <.>|Exception