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| author | wmat <wmat@riscv.org> | 2024-03-05 09:57:54 -0500 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-03-05 09:57:54 -0500 |
| commit | b72d233d542a75d272bf343e38285165ccaddd29 (patch) | |
| tree | 778c5f416fe6ff80c6558d7b012d35661d671834 | |
| parent | 532ddc2703dd1ad9a24d242445115a39b4c5bbbf (diff) | |
| download | riscv-isa-manual-b72d233d542a75d272bf343e38285165ccaddd29.zip riscv-isa-manual-b72d233d542a75d272bf343e38285165ccaddd29.tar.gz riscv-isa-manual-b72d233d542a75d272bf343e38285165ccaddd29.tar.bz2 | |
Fixing formatting
Fixing the monospaced formatting on some text.
| -rw-r--r-- | src/sscofpmt.adoc | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/sscofpmt.adoc b/src/sscofpmt.adoc index e5d48b8..101c15f 100644 --- a/src/sscofpmt.adoc +++ b/src/sscofpmt.adoc @@ -33,9 +33,7 @@ interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers. This extension expands the hardware performance monitor description and extends the mhpmevent registers to 64 bits (in RV32) as follows: -The hardware performance monitor includes 29 additional 64-bit event counters -and 29 associated 64-bit event selector registers - the -mhpmcounter3–mhpmcounter31 and mhpmevent3–mhpmevent31 CSRs. +The hardware performance monitor includes 29 additional 64-bit event counters and 29 associated 64-bit event selector registers - the mhpmcounter3–mhpmcounter31 and mhpmevent3–mhpmevent31 CSRs. The mhpmcounters are WARL registers that support up to 64 bits of precision on RV32 and RV64. @@ -72,8 +70,8 @@ bit [57] 0 - Reserved for possible future modes bit [56] 0 - Reserved for possible future modes -Each of the five `x`INH bits, when set, inhibit counting of events while in -privilege mode `x`. All-zeroes for these bits results in counting of events in +Each of the five ``x``INH bits, when set, inhibit counting of events while in +privilege mode ``x``. All-zeroes for these bits results in counting of events in all modes. The OF bit is set when the corresponding hpmcounter overflows, and remains set |