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| author | Bill Traynor <wmat@riscv.org> | 2023-07-18 09:06:11 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-18 09:06:11 -0400 |
| commit | cb6e9d32ef35fe428bb5c4cd6d87215df0e68575 (patch) | |
| tree | 9cabbc7d266048620cb0d28c2d90a256f36c6885 | |
| parent | 160d53fb364afa83ea19985e5e33bc691e740544 (diff) | |
| parent | e9d1350042b9309b2b48f02308160bad50bac8f2 (diff) | |
| download | riscv-isa-manual-cb6e9d32ef35fe428bb5c4cd6d87215df0e68575.zip riscv-isa-manual-cb6e9d32ef35fe428bb5c4cd6d87215df0e68575.tar.gz riscv-isa-manual-cb6e9d32ef35fe428bb5c4cd6d87215df0e68575.tar.bz2 | |
Merge pull request #1069 from tariqkurd-repo/patch-5
fix formatting
| -rw-r--r-- | src/hypervisor.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 919e63f..f7bc318 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -1410,7 +1410,7 @@ include::images/bytefield/mtval2reg.edn[] When a guest-page-fault trap is taken into M-mode, `mtval2` is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, `mtval2` is set to zero, but a future -standard or extension may redefine `mtval2`'s setting for other traps. +standard or extension may redefine `mtval2's` setting for other traps. If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address |