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| author | Bill Traynor <wmat@riscv.org> | 2023-07-13 11:17:35 -0400 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-07-13 11:17:35 -0400 |
| commit | 261384ecd47f73e83cc1f3828b2ce213b7b5680c (patch) | |
| tree | 96f796056739214b5b38a9f5228b9d8f5383a1f1 | |
| parent | 71ac43eb32534d154f165938876eb2a199562465 (diff) | |
| download | riscv-isa-manual-261384ecd47f73e83cc1f3828b2ce213b7b5680c.zip riscv-isa-manual-261384ecd47f73e83cc1f3828b2ce213b7b5680c.tar.gz riscv-isa-manual-261384ecd47f73e83cc1f3828b2ce213b7b5680c.tar.bz2 | |
Fix SP Load & Store for F Extension
Set Width to W for the Single-Precision Loand and
Store Instructions for the F Extension to match LaTeX.
Added new wavedrom file for this diagram.
| -rw-r--r-- | src/f-st-ext.adoc | 2 | ||||
| -rw-r--r-- | src/images/wavedrom/sp-load-and-store-2.adoc | 24 |
2 files changed, 25 insertions, 1 deletions
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc index 13db568..0e27348 100644 --- a/src/f-st-ext.adoc +++ b/src/f-st-ext.adoc @@ -231,7 +231,7 @@ signals. Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register _rs1_ and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register _rd_. FSW stores a single-precision value from floating-point register _rs2_ to memory. -include::images/wavedrom/sp-load-store.adoc[] +include::images/wavedrom/sp-load-store-2.adoc[] [[sp-ldst]] //.SP load and store diff --git a/src/images/wavedrom/sp-load-and-store-2.adoc b/src/images/wavedrom/sp-load-and-store-2.adoc new file mode 100644 index 0000000..f1025e9 --- /dev/null +++ b/src/images/wavedrom/sp-load-and-store-2.adoc @@ -0,0 +1,24 @@ +//## 12.5 Single-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP'], type: 8}, + {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, + {bits: 3, name: 'width', attr: ['3', 'W'], type: 8}, + {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP'], type: 8}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, + {bits: 3, name: 'width', attr: ['3', 'W'], type: 8}, + {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, + {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, +]} +....
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