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authorBill Traynor <wmat@riscv.org>2023-07-11 09:04:53 -0400
committerBill Traynor <wmat@riscv.org>2023-07-11 09:04:53 -0400
commit1fa1528008f7e34c8d0e3434606868c4a952a6a2 (patch)
tree63619b592ef6ccad7ab3b124863b9bc8761ec164
parent9d49cc632417db08ba2fecf2e91b423656ce92a8 (diff)
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Fixes to HINT table.
First ADD should have rs1!=x0 Second ADD should have rs2!=x2-x5 Third ADD had an rs3 and should have rs2 in purpose column Third ADD was missing NTL.ALL Fence was missing succ=0 Fixed some formatting adding second backtick around text
-rw-r--r--src/rv32.adoc16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc
index 6e57344..8101c3a 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -1005,7 +1005,7 @@ hints, security tags, and instrumentation flags for simulation/emulation.
|AUIPC |_rd_=`x0` |latexmath:[$2^{20}$]
-|ADDI |_rd_=`x0`, and either _rs1_ &#8800; `x0` or _imm_&#8800;0 |latexmath:[$2^{17}-1$]
+|ADDI |_rd_=`x0`, and either _rs1_&#8800;``x0`` or _imm_&#8800;0 |latexmath:[$2^{17}-1$]
|ANDI |_rd_=`x0` |latexmath:[$2^{17}$]
@@ -1013,14 +1013,14 @@ hints, security tags, and instrumentation flags for simulation/emulation.
|XORI |_rd_=`x0` |latexmath:[$2^{17}$]
-|ADD |_rd_=`x0`, _rs1_=`x0` |latexmath:[$2^{10}-32$]
+|ADD |_rd_=`x0`, _rs1_&#8800;``x0`` |latexmath:[$2^{10}-32$]
-|ADD |_rd_=`x0`, _rs1_=`x0`, _rs2_=`x2-x5` | 28
+|ADD |_rd_=`x0`, _rs1_=`x0`, _rs2_&#8800;``x2-x5`` | 28
|ADD |_rd_=`x0`, _rs1_=`x0`, _rs2_=`x2-x5` |4|(_rs2_=`x2`) NTL.P1 +
(_rs2_=`x3`) NTL.PALL +
-(_rs3_=`x4`) NTL.S1 +
-(_rs2_=`x5`)
+(_rs2_=`x4`) NTL.S1 +
+(_rs2_=`x5`) NTL.ALL
|SUB |_rd_=`x0` |latexmath:[$2^{10}$] .11+<.^m|_Designated for future standard use_
@@ -1036,13 +1036,13 @@ hints, security tags, and instrumentation flags for simulation/emulation.
|SRA |_rd_=`x0` |latexmath:[$2^{10}$]
-|FENCE|_rd_=`x0`, _rs1_ &#8800; `x0`, _fm_=0, and either _pred_=0 or _succ_=0| latexmath:[$2^{10}-63$]
+|FENCE|_rd_=`x0`, _rs1_&#8800;``x0``, _fm_=0, and either _pred_=0 or _succ_=0| latexmath:[$2^{10}-63$]
-|FENCE|_rd_ &#8800; `x0`, _rs1_=`x0`, _fm_=0, and either _pred_=0 or _succ_=0| latexmath:[$2^{10}-63$]
+|FENCE|_rd_&#8800;``x0``, _rs1_=`x0`, _fm_=0, and either _pred_=0 or _succ_=0| latexmath:[$2^{10}-63$]
|FENCE |_rd_=_rs1_=`x0`, _fm_=0, _pred_=0, _succ_&#8800;0 |15
-|FENCE |_rd_=_rs1_=`x0`, _fm_=0, _pred_&#8800;W, _succ_&#8800;0 |15
+|FENCE |_rd_=_rs1_=`x0`, _fm_=0, _pred_&#8800;W, _succ_=0 |15
|FENCE |_rd_=_rs1_=`x0`, _fm_=0, _pred_=W, _succ_=0 |1 |PAUSE