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| author | Andrew Waterman <andrew@sifive.com> | 2023-05-30 16:21:39 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-05-30 16:23:04 -0700 |
| commit | 017548abc66996177ad5d58f5290319d7b4f4636 (patch) | |
| tree | 1f843d088adb53c350f356ee76688f674eb2a463 | |
| parent | d122646f2cf8dad21f26af5c8f8a78e9b72807be (diff) | |
| download | riscv-isa-manual-017548abc66996177ad5d58f5290319d7b4f4636.zip riscv-isa-manual-017548abc66996177ad5d58f5290319d7b4f4636.tar.gz riscv-isa-manual-017548abc66996177ad5d58f5290319d7b4f4636.tar.bz2 | |
Next-lowest => next-lower
No functional change. For consistency with other specs.
cc @gfavor
| -rw-r--r-- | src/machine.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.adoc b/src/machine.adoc index 6e76b32..864b96b 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1408,7 +1408,7 @@ include::images/bytefield/hpmcounters.adoc[] The counter-enable register `mcounteren` is a 32-bit register that controls the availability of the hardware performance-monitoring -counters to the next-lowest privileged mode. +counters to the next-lower privileged mode. .Counter-enable register (`mcounteren`). include::images/bytefield/counteren.adoc[] |