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| author | Andrew Waterman <andrew@sifive.com> | 2019-04-19 22:06:07 -0500 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-04-19 22:06:07 -0500 |
| commit | a5df328724f5b769b4c5941625871cc280b84604 (patch) | |
| tree | 5804198c27b272bea03c83c97cf3318d6250b256 | |
| parent | aa5734d69383c97c119923d1e823997e3e2930c5 (diff) | |
| download | riscv-isa-manual-a5df328724f5b769b4c5941625871cc280b84604.zip riscv-isa-manual-a5df328724f5b769b4c5941625871cc280b84604.tar.gz riscv-isa-manual-a5df328724f5b769b4c5941625871cc280b84604.tar.bz2 | |
Clarify hypervisor/PLIC sentiment
| -rw-r--r-- | src/hypervisor.tex | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index e8cf7c2..179611d 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -502,10 +502,14 @@ virtualization modes (V=0 to V=1, or vice-versa), the implementation swaps the defined fields of {\tt bsip} with their counterparts in {\tt sip}. The other fields in {\tt sip} are unchanged. -\note{Need to describe how {\tt bsip}.SEIP interacts with PLIC. Current -thinking is that {\tt bsip}.SEIP should purely be a read-write storage bit to -emulate the PLIC for VS-mode; the PLIC should not be wired into {\tt -bsip}.SEIP.} +\note{Need to describe how {\tt bsip}.SEIP interacts with PLIC. +Current thinking is that the VS-level {\tt sip}.SEIP should purely be a +read-write storage bit to emulate the PLIC for VS-mode; the PLIC should not be +wired into the VS-level {\tt sip}.SEIP. + +A future revision of the PLIC is expected to provide direct support +for VS-level interrupts to reduce virtualization overhead.} + \begin{figure*}[h!] {\footnotesize |