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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-07 22:21:48 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-07 22:21:48 -0800 |
| commit | 8ad28437a347aadc733d2106064a380624f8b581 (patch) | |
| tree | 653d235a3d816c99c25a258baa8fe28fe842d3ce | |
| parent | 8dc9b9cc34bdd200422043014df648a268f11662 (diff) | |
| download | riscv-isa-manual-8ad28437a347aadc733d2106064a380624f8b581.zip riscv-isa-manual-8ad28437a347aadc733d2106064a380624f8b581.tar.gz riscv-isa-manual-8ad28437a347aadc733d2106064a380624f8b581.tar.bz2 | |
Update preface
| -rw-r--r-- | src/priv-preface.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 820e347..74598b4 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -30,6 +30,7 @@ The changes in this version of the document include: \item Improvements to the description and commentary. \item Added a draft proposal for a hypervisor extension. \item Specified which interrupt sources are reserved for standard use. +\item Allocated some synchronous exception causes for custom use. \item Added specification that xRET instructions may, but are not required to, clear LR reservations if A extension present. \item The virtual-memory system no longer permits supervisor mode to execute |