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author | Andrew Waterman <andrew@sifive.com> | 2019-03-13 19:06:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-03-13 19:06:59 -0700 |
commit | 0c852a1c5012d56cf365db9e5fd1953375509596 (patch) | |
tree | 5e29627d2a4ec85413e585a0bf23fbe329ca3769 | |
parent | fa75f2515b2021e211b8432cfe0d81448438deec (diff) | |
download | riscv-isa-manual-0c852a1c5012d56cf365db9e5fd1953375509596.zip riscv-isa-manual-0c852a1c5012d56cf365db9e5fd1953375509596.tar.gz riscv-isa-manual-0c852a1c5012d56cf365db9e5fd1953375509596.tar.bz2 |
Improve commentary on CSR ordering
-rw-r--r-- | src/csr.tex | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/csr.tex b/src/csr.tex index 1118fb1..f73a8cd 100644 --- a/src/csr.tex +++ b/src/csr.tex @@ -181,9 +181,12 @@ scheme. \end{commentary} \begin{commentary} -Some CSRs, including those defined in Chapter~\ref{sec:single-float}, are not -accessible to other harts or devices and cause no side effects visible to -other harts or devices when accessed locally. Accesses to such CSRs can be -freely reordered with respect to FENCE instructions without violating this -specification. +These CSR-ordering constraints are imposed primarily to support ordering +memory and memory-mapped I/O accesses with respect to reads of the {\tt time} +CSR. With the exception of the {\tt time}, {\tt cycle}, and {\tt mcycle} +CSRs, the CSRs defined thus far in Volumes I and II of this specification are +not directly accessible to other harts or devices and cause no side effects +visible to other harts or devices. Thus, accesses to CSRs other than the +aforementioned three can be freely reordered with respect to FENCE +instructions without violating this specification. \end{commentary} |