Moved XLEN definition to intro.

2 files changed, 12 insertions, 11 deletions

diff --git a/src/intro.tex b/src/intro.tex
index ddfea66..5077ae5 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -197,12 +197,15 @@ width of the integer registers and the corresponding size of the
 address space and by the number of integer registers.  There are two
 primary base integer variants, RV32I and RV64I, described in
 Chapters~\ref{rv32} and \ref{rv64}, which provide 32-bit or 64-bit
-address spaces respectively.  Chapter~\ref{rv32e} describes the RV32E
-subset variant of the RV32I base instruction set, which has been added
-to support small microcontrollers.  Chapter~\ref{rv128} sketches a
-future RV128I variant of the base integer instruction set supporting a
-flat 128-bit address space.  The base integer instruction sets use a
-two's-complement representation for signed integer values.
+address spaces respectively.  We use the term XLEN to refer to the
+width of an integer register in bits (either 32 or 64).
+Chapter~\ref{rv32e} describes the RV32E subset variant of the RV32I
+base instruction set, which has been added to support small
+microcontrollers, and which has half the number of integer registers.
+Chapter~\ref{rv128} sketches a future RV128I variant of the base
+integer instruction set supporting a flat 128-bit address space
+(XLEN=128).  The base integer instruction sets use a two's-complement
+representation for signed integer values.
 
 \begin{commentary}
 Although 64-bit address spaces are a requirement for larger systems,
@@ -239,10 +242,10 @@ encodings, and the different RISC-V base ISAs are similar enough that
 supporting multiple versions is relatively low cost.  Although some
 have proposed that the strict superset design would allow legacy
 32-bit libraries to be linked with 64-bit code, this is impractical in
-practice even with compatible encodings due to the differences in
+practice, even with compatible encodings, due to the differences in
 software calling conventions and system-call interfaces.
 
-The current RISC-V privileged architecture provides fields in {\tt
+The RISC-V privileged architecture provides fields in {\tt
   misa} to control the user ISA at each level to support emulating
 different base ISAs on the same hardware.  We note that newer SPARC
 and MIPS ISA revisions have deprecated support for running 32-bit code
diff --git a/src/rv32.tex b/src/rv32.tex
index 11cb063..e3075c8 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -32,9 +32,7 @@ which hold integer values.  Register {\tt x0} is hardwired to the
 constant 0.  There is no hardwired subroutine return address link
 register, but the standard software calling convention uses register
 {\tt x1} to hold the return address on a call.  For RV32, the {\tt x}
-registers are 32 bits wide, and for RV64, they are 64 bits wide.  This
-document uses the term XLEN to refer to the current width of an {\tt
-  x} register in bits (either 32 or 64).
+registers are 32 bits wide, and for RV64, they are 64 bits wide.
 
 There is one additional user-visible register: the program counter {\tt pc}
 holds the address of the current instruction.