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author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-29 22:22:54 -0700 |
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committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-29 22:22:54 -0700 |
commit | c931c5ac21baf03f6e476ef718b5e78413a3cc46 (patch) | |
tree | 019dc9b212b22205ab43464482d6a04094cc5208 | |
parent | 4a331c8aebde7bcf0c28eb75173fe76b9323f2eb (diff) | |
download | riscv-isa-manual-c931c5ac21baf03f6e476ef718b5e78413a3cc46.zip riscv-isa-manual-c931c5ac21baf03f6e476ef718b5e78413a3cc46.tar.gz riscv-isa-manual-c931c5ac21baf03f6e476ef718b5e78413a3cc46.tar.bz2 |
Clarified that AUIPC uses PC of AUIPC instruction itself.
-rw-r--r-- | src/rv32.tex | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index c27e20b..469ed3b 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -123,15 +123,16 @@ RV32E subset, which only has 16 registers (Chapter~\ref{rv32e}). In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure~\ref{fig:baseinstformats}. All are a fixed 32 bits in -length and must be aligned on a four-byte boundary in memory. An instruction address misaligned exception is generated on a -taken branch or unconditional jump if the target address is not -four-byte aligned. No instruction fetch misaligned exception is -generated for a conditional branch that is not taken. +length and must be aligned on a four-byte boundary in memory. An +instruction-address-misaligned exception is generated on a taken +branch or unconditional jump if the target address is not four-byte +aligned. No instruction-address-misaligned exception is generated for +a conditional branch that is not taken. \begin{commentary} The alignment constraint for base ISA instructions is relaxed to a two-byte boundary when instruction extensions with 16-bit lengths or -other odd multiples of 16-bit lengths are added. +other odd multiples of 16-bit lengths are added (i.e., IALIGN=16). \end{commentary} \vspace{-0.2in} @@ -541,7 +542,7 @@ bits with zeros. AUIPC (add upper immediate to {\tt pc}) is used to build {\tt pc}-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits with zeros, adds this offset -to the {\tt pc}, then places the result in register {\em rd}. +to the {\tt pc} of the AUIPC instruction, then places the result in register {\em rd}. \begin{commentary} The AUIPC instruction supports two-instruction sequences to access @@ -551,10 +552,11 @@ JALR can transfer control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit immediate offset in regular load or store instructions can access any 32-bit PC-relative data address. -The current PC can be obtained by setting the U-immediate to 0. Although -a JAL +4 instruction could also be used to obtain the PC, it might cause -pipeline breaks in simpler microarchitectures or pollute the BTB structures in -more complex microarchitectures. +The current PC can be obtained by setting the U-immediate to 0. +Although a JAL +4 instruction could also be used to obtain the local +PC (of the instruction following the JAL), it might cause pipeline +breaks in simpler microarchitectures or pollute BTB structures in more +complex microarchitectures. \end{commentary} \subsubsection*{Integer Register-Register Operations} |