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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 18:15:01 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 18:15:01 -0700 |
| commit | b285e77d9334a29fac058c0cf43ce4037c9080aa (patch) | |
| tree | c63accf313e2778399a2169e85f033201ef1bf37 | |
| parent | a533b92630e9715d90a2a35c4309c90d3820c98b (diff) | |
| download | riscv-isa-manual-b285e77d9334a29fac058c0cf43ce4037c9080aa.zip riscv-isa-manual-b285e77d9334a29fac058c0cf43ce4037c9080aa.tar.gz riscv-isa-manual-b285e77d9334a29fac058c0cf43ce4037c9080aa.tar.bz2 | |
Added comment that we might consider different pattern for RV128 to improve compatibility with RV64.
| -rw-r--r-- | src/rv128.tex | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/rv128.tex b/src/rv128.tex index 17075d0..ef78dd9 100644 --- a/src/rv128.tex +++ b/src/rv128.tex @@ -47,6 +47,13 @@ values held in the low bits of the 128-bit integer registers are added. The ``*D'' instructions consume two major opcodes (OP-IMM-64 and OP-64) in the standard 32-bit encoding. +\begin{commentary} + To improve compatibilty with RV64, in a reverse of how RV32 to RV64 + was handled, we might change the decoding around to rename RV64I ADD + as a 64-bit ADDD, and add a 128-bit ADDQ in what was previously the + OP-64 major opcode (now renamed the OP-128 major opcode). +\end{commentary} + Shifts by an immediate (SLLI/SRLI/SRAI) are now encoded using the low 7 bits of the I-immediate, and variable shifts (SLL/SRL/SRA) use the low 7 bits of the shift amount source register. |