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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-13 18:54:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-13 18:54:27 -0700 |
| commit | fa75f2515b2021e211b8432cfe0d81448438deec (patch) | |
| tree | c253758a0d1ff6dce02f9fb7d95fe8a10e425893 | |
| parent | d08060cef4facf327957a133c826c7cf749c6846 (diff) | |
| download | riscv-isa-manual-fa75f2515b2021e211b8432cfe0d81448438deec.zip riscv-isa-manual-fa75f2515b2021e211b8432cfe0d81448438deec.tar.gz riscv-isa-manual-fa75f2515b2021e211b8432cfe0d81448438deec.tar.bz2 | |
Improve wording of satp/ASID/caching/speculation paragraph
@dkruckemyer-ventana This isn't meant to encode any semantic changes,
just to clarify the existing text. But I thought you might want to
read over it.
| -rw-r--r-- | src/supervisor.tex | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index bc9b15f..9956c7c 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -998,11 +998,22 @@ the ASID value in {\em rs2} and always perform a global fence. \end{commentary} Implementations may perform implicit reads of the translation data structures -arbitrarily early and speculatively. The results of these implicit speculative reads -may be incoherently cached. However, implementations must only perform implicit -reads of the translation data structures pointed to by the current {\tt satp} -register, and must establish cache entries only for the ASID currently loaded -into the {\tt satp} register, or for global entries. +pointed to by the current {\tt satp} register arbitrarily early and +speculatively. The results of these reads may be held in an incoherent cache +but not shared with other harts. Cache entries may only be established for +the ASID currently loaded into the {\tt satp} register, or for global entries. +The cache may only satisfy implicit reads for entries that have been +established for the ASID currently loaded into {\tt satp}, or for global +entries. Changes in the {\tt satp} register do not necessarily flush any such +translation caches. To ensure the implicit reads observe writes to the same +memory locations, an SFENCE.VMA instruction must be executed after the writes +to flush the relevant cached translations. + +Implementations must only perform implicit reads of the translation +data structures pointed to by the current contents of the satp +register, and must only raise exceptions for implicit accesses that are +generated as a result of instruction execution, not those that are +performed speculatively. \begin{commentary} The following common situations typically require executing an |