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| author | Andrew Waterman <andrew@sifive.com> | 2019-04-11 17:33:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-04-11 17:33:40 -0700 |
| commit | ebac213077afc0f886b835304fd42819f7569cc5 (patch) | |
| tree | e2b7147d5f2c8468392e6bacf59fe7ef87739d09 | |
| parent | 30f01bd475a5dc0bc533c92f06cb329218ac5d76 (diff) | |
| download | riscv-isa-manual-ebac213077afc0f886b835304fd42819f7569cc5.zip riscv-isa-manual-ebac213077afc0f886b835304fd42819f7569cc5.tar.gz riscv-isa-manual-ebac213077afc0f886b835304fd42819f7569cc5.tar.bz2 | |
clarify in commentary that environment break == EBREAK
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index a7a3ba6..747c97a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2008,7 +2008,7 @@ The priority of any custom synchronous exceptions is implementation-defined. \begin{commentary} Instruction address breakpoints have the same cause value as, but different priority than, data address breakpoints (a.k.a. watchpoints) -and environment breaks. +and environment break exceptions (which are raised by the EBREAK instruction). \end{commentary} \begin{commentary} |