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| author | Andrew Waterman <andrew@sifive.com> | 2019-02-19 13:54:45 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-02-19 13:54:45 -0800 |
| commit | e67203b8b608586e1cce0578e5f575ed317f253c (patch) | |
| tree | 0d2d52fd5d74099d5f35fd10061439c33aa126f6 | |
| parent | 8d5ad23a1ceb1690c6d2ffec0676d23bd785e92e (diff) | |
| download | riscv-isa-manual-e67203b8b608586e1cce0578e5f575ed317f253c.zip riscv-isa-manual-e67203b8b608586e1cce0578e5f575ed317f253c.tar.gz riscv-isa-manual-e67203b8b608586e1cce0578e5f575ed317f253c.tar.bz2 | |
tweak A/D bit wording
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index fb83897..0a8f12c 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1208,7 +1208,7 @@ Two schemes to manage the A and D bits are permitted: The PTE update is not required to be atomic with respect to the explicit memory access that caused the update, and the sequence is interruptible. However, the hart must not perform the explicit memory access before the - PTE update. + PTE update is globally visible. \end{itemize} All harts in a system must employ the same PTE-update scheme as each other. |