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| author | Alex Bradbury <asb@lowrisc.org> | 2019-07-10 07:15:04 +0100 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-09 23:15:04 -0700 |
| commit | b2d6a97fb1986261b785a7200d403912b4d14b3b (patch) | |
| tree | 2be766f9eb16e55988241a16a621ae5a4438d404 | |
| parent | 9f0e2341734fb3dcbcec737fd21ff8d5f4e6ea00 (diff) | |
| download | riscv-isa-manual-b2d6a97fb1986261b785a7200d403912b4d14b3b.zip riscv-isa-manual-b2d6a97fb1986261b785a7200d403912b4d14b3b.tar.gz riscv-isa-manual-b2d6a97fb1986261b785a7200d403912b4d14b3b.tar.bz2 | |
Clarify that mtvec is WARL (#406)
Other WARL registers seem to be explicit (e.g. "The misa CSR is a WARL
read-write register..."). This patch adds a similar indication for
mtvec. This consistency is important, as otherwise the reader will spend
time trying to determine if the behaviour is different. You can
determine it's WARL by reading the field layout diagram, but I think a
little redundancy in favour of easing readability makes sense.
At least one simulator started off trapping on invalid field
modifications
<https://lists.gnu.org/archive/html/qemu-devel/2018-04/msg04510.html>.
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 34c7046..a3a8e92 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1114,7 +1114,7 @@ interrupts, unless the interrupt results in a user-level context swap. \subsection{Machine Trap-Vector Base-Address Register ({\tt mtvec})} -The {\tt mtvec} register is an MXLEN-bit read/write register that holds +The {\tt mtvec} register is an MXLEN-bit \warl\ read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). |