Clarify the behaviour of LR.W/D and SC.W/D

Concerning issue #376.

1 files changed, 9 insertions, 7 deletions

diff --git a/src/a.tex b/src/a.tex
index ce92e66..c4a8d26 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -77,19 +77,21 @@ address domain.
 \multicolumn{1}{c|}{opcode} \\
 \hline
 5 & 1 & 1 & 5 & 5 & 3 & 5 & 7 \\
-LR & \multicolumn{2}{c}{ordering} & 0   & addr & width & dest & AMO    \\
-SC & \multicolumn{2}{c}{ordering} & src & addr & width & dest & AMO  \\
+LR.W/D & \multicolumn{2}{c}{ordering} & 0   & addr & width & dest & AMO    \\
+SC.W/D & \multicolumn{2}{c}{ordering} & src & addr & width & dest & AMO  \\
 \end{tabular}
 \end{center}
 
-Complex atomic memory operations on a single memory word are performed
+Complex atomic memory operations on a single memory word or doubleword are performed
 with the load-reserved (LR) and store-conditional (SC) instructions.
-LR loads a word from the address in {\em rs1}, places the
+LR.W loads a word from the address in {\em rs1}, places the
 sign-extended value in {\em rd}, and registers a reservation on the
 memory address and a range of bytes including at least all bytes of
-the addressed word.  SC writes a word in {\em rs2} to the address in
+the addressed word.  SC.W writes a word in {\em rs2} to the address in
 {\em rs1}, provided a valid reservation still exists on that address.
-SC writes zero to {\em rd} on success or a nonzero code on failure.
+SC.W writes zero to {\em rd} on success or a nonzero code on failure.
+LR.D and SC.D act analogously on doublewords and are only available on RV64.
+For RV64, LR.W and SC.W sign-extend the value placed in {\em rd}.
 
 \begin{commentary}
 Both compare-and-swap (CAS) and LR/SC can be used to build lock-free
@@ -191,7 +193,7 @@ not meet the forward-progress guarantee.
 
 An implementation can reserve an arbitrarily large subset of the
 address space on each LR, provided the memory range includes all bytes
-of the addressed data word.
+of the addressed data word or doubleword.
 An SC can only pair with the most recent LR in program order.  An SC
 may succeed if no store from another hart to the address range
 reserved by the LR can be observed to have occurred between the LR and