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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 18:57:19 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 18:57:19 -0700 |
| commit | 964513a32e4472190d8f9c671fca515142a1b6f8 (patch) | |
| tree | 1df483c020f04eb396460ae597f86c2f12bd058d | |
| parent | fc5b6ca73edcb04f7c8d8f215ecf0d543466e6a0 (diff) | |
| download | riscv-isa-manual-964513a32e4472190d8f9c671fca515142a1b6f8.zip riscv-isa-manual-964513a32e4472190d8f9c671fca515142a1b6f8.tar.gz riscv-isa-manual-964513a32e4472190d8f9c671fca515142a1b6f8.tar.bz2 | |
Clarify PC behavior when XLEN < max supported XLEN
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index be3413e..302a620 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -658,6 +658,8 @@ Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register. +Similarly, {\tt pc} bits above XLEN are ignored, and when the {\tt pc} +is written, it is sign-extended to fill the widest supported XLEN. \begin{commentary} We require that operations always fill the entire underlying hardware registers with defined values to avoid implementation-defined |