Clarify behavior of LR.rl and SC.aq (#339)

Resolves #338

1 files changed, 6 insertions, 3 deletions

diff --git a/src/a.tex b/src/a.tex
index 7841d49..ce92e66 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -254,14 +254,17 @@ by setting the {\em rl} bit on the SC instruction.  Setting the {\em
 consistent, meaning that it cannot be reordered with earlier or
 later memory operations from the same hart.
 
-The {\em rl} bit on an LR instruction must not be set unless the {\em aq} bit is also set.
-The {\em aq} bit on an SC instruction must not be set unless the {\em rl} bit is also set.
-
 If neither bit is set on both LR and SC, the LR/SC sequence can be
 observed to occur before or after surrounding memory operations from
 the same RISC-V hart.  This can be appropriate when the LR/SC
 sequence is used to implement a parallel reduction operation.
 
+Software should not set the {\em rl} bit on an LR instruction unless the {\em
+aq} bit is also set, nor should software set the {\em aq} bit on an SC
+instruction unless the {\em rl} bit is also set.  LR.{\em rl} and SC.{\em aq}
+instructions are not guaranteed to provide any stronger ordering than those
+with both bits clear, but may result in lower performance.
+
 \begin{commentary}
 In general, a multi-word atomic primitive is desirable but there is
 still considerable debate about what form this should take, and