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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 12:11:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 12:11:16 -0700 |
| commit | 645dbe107502c344c3fa3e6816cbb49fafeb8098 (patch) | |
| tree | ab7e65ccdf8b158eab9ff79e5b8bb10aa250e15a | |
| parent | 009829465918a84ced119df9a5eaf725c2de62cc (diff) | |
| download | riscv-isa-manual-645dbe107502c344c3fa3e6816cbb49fafeb8098.zip riscv-isa-manual-645dbe107502c344c3fa3e6816cbb49fafeb8098.tar.gz riscv-isa-manual-645dbe107502c344c3fa3e6816cbb49fafeb8098.tar.bz2 | |
Spelling
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/supervisor.tex | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 9d4fe06..010aafc 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -751,7 +751,7 @@ Figure~\ref{sv32pte}) are little-endian or big-endian, including explicit accesses to such pages made from S-mode with {\tt sstatus}.SUM=1. For {\em implicit} accesses to supervisor-level memory management data -structures, such as page tables, endianness is always controled by SBE. +structures, such as page tables, endianness is always controlled by SBE. If S-mode is supported, an implementation may hardwire SBE so that SBE=MBE. diff --git a/src/supervisor.tex b/src/supervisor.tex index 28e27b4..29afbca 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -12,7 +12,7 @@ interrupts, to support clean virtualization. In this spirit, certain supervisor-level facilities, including requests for timer and interprocessor interrupts, are provided by implementation-specific mechanisms. In some systems, a supervisor execution environment (SEE) -provides these facilities in a manner specified by a superivsor binary +provides these facilities in a manner specified by a supervisor binary interface (SBI). Other systems supply these facilities directly, through some other implementation-defined mechanism. \end{commentary} |