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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-12 10:57:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-12 10:57:08 -0700 |
| commit | 5960072e57140d9a56446e837d59fd5bf484434d (patch) | |
| tree | b22b39c7d78280210afa190a11fa21046ade3c18 | |
| parent | b2d6a97fb1986261b785a7200d403912b4d14b3b (diff) | |
| download | riscv-isa-manual-5960072e57140d9a56446e837d59fd5bf484434d.zip riscv-isa-manual-5960072e57140d9a56446e837d59fd5bf484434d.tar.gz riscv-isa-manual-5960072e57140d9a56446e837d59fd5bf484434d.tar.bz2 | |
Clarify that mtime writes/ticks can also clear MTIP
| -rw-r--r-- | src/machine.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index a3a8e92..6a9d922 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1580,8 +1580,9 @@ systems. Platforms provide a 64-bit memory-mapped machine-mode timer compare register ({\tt mtimecmp}), which causes a timer interrupt to be posted when the {\tt mtime} register contains a value greater than or equal to the value in the {\tt mtimecmp} register. -The interrupt remains posted until it is cleared by writing the {\tt - mtimecmp} register. The interrupt will only be taken if interrupts +The interrupt remains posted until {\tt mtimecmp} becomes greater than +{\tt mtime} (typically as a result of writing {\tt mtimecmp}). +The interrupt will only be taken if interrupts are enabled and the MTIE bit is set in the {\tt mie} register. \begin{figure}[h!] |