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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-04 13:56:11 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-04 13:56:11 -0800 |
| commit | 564b18ac2eeee14c19231739d10f18dd0c4a10f0 (patch) | |
| tree | 8938564df6dbb49105905f97f7ac19856c86e60f | |
| parent | 2abb68f521d50e0ac4bff7661f4748a8f0bc773a (diff) | |
| download | riscv-isa-manual-564b18ac2eeee14c19231739d10f18dd0c4a10f0.zip riscv-isa-manual-564b18ac2eeee14c19231739d10f18dd0c4a10f0.tar.gz riscv-isa-manual-564b18ac2eeee14c19231739d10f18dd0c4a10f0.tar.bz2 | |
Add lla pseudoinstruction; add PIC version of la
Closes #351
| -rw-r--r-- | src/assembly.tex | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/src/assembly.tex b/src/assembly.tex index cfbc0d0..b535e16 100644 --- a/src/assembly.tex +++ b/src/assembly.tex @@ -59,7 +59,11 @@ RISC-V pseudoinstructions. \begin{tabular}{l l l} pseudoinstruction & Base Instruction(s) & Meaning \\ \hline -\tt la rd, symbol & {\tt auipc rd, ${\tt delta[31:12]} + {\tt delta[11]}$} & Load absolute address, \\ +\tt la rd, symbol (\emph{non-PIC}) & {\tt auipc rd, ${\tt delta[31:12]} + {\tt delta[11]}$} & Load absolute address, \\ + & {\tt addi rd, rd, delta[11:0]} & where ${\tt delta} = {\tt symbol} - {\tt pc}$ \\[1ex] +\tt la rd, symbol (\emph{PIC})& {\tt auipc rd, ${\tt delta[31:12]} + {\tt delta[11]}$} & Load absolute address, \\ + & {\tt l\{w|d\} rd, rd, delta[11:0]} & where ${\tt delta} = {\tt GOT[symbol]} - {\tt pc}$ \\[1ex] +\tt lla rd, symbol& {\tt auipc rd, ${\tt delta[31:12]} + {\tt delta[11]}$} & Load local address, \\ & {\tt addi rd, rd, delta[11:0]} & where ${\tt delta} = {\tt symbol} - {\tt pc}$ \\[1ex] \tt l\{b|h|w|d\} rd, symbol & {\tt auipc rd, ${\tt delta[31:12]} + {\tt delta[11]}$} & Load global \\ & {\tt l\{b|h|w|d\} rd, delta[11:0](rd)} & \\[1ex] @@ -103,18 +107,6 @@ pseudoinstruction & Base Instruction(s) & Meaning \\ \hline {\tt bgtu rs, rt, offset} & {\tt bltu rt, rs, offset} & Branch if $>$, unsigned \\ {\tt bleu rs, rt, offset} & {\tt bgeu rt, rs, offset} & Branch if $\leq$, unsigned \\ \hline -{\tt j offset} & {\tt jal x0, offset} & Jump \\ -{\tt jal offset} & {\tt jal x1, offset} & Jump and link \\ -{\tt jr rs} & {\tt jalr x0, 0(rs)} & Jump register \\ -{\tt jalr rs} & {\tt jalr x1, 0(rs)} & Jump and link register \\ -{\tt ret} & {\tt jalr x0, 0(x1)} & Return from subroutine \\ -\tt call offset & {\tt auipc x1, ${\tt offset[31:12]} + {\tt offset[11]}$} & Call far-away subroutine \\ - & {\tt jalr x1, offset[11:0](x1)} & \\ -\tt tail offset & {\tt auipc x6, ${\tt offset[31:12]} + {\tt offset[11]}$} & Tail call far-away subroutine \\ - & {\tt jalr x0, offset[11:0](x6)} & \\ -\hline -{\tt fence} & {\tt fence iorw, iorw} & Fence on all memory and I/O \\ -\hline \end{tabular} \end{center} @@ -129,6 +121,18 @@ pseudoinstruction & Base Instruction(s) & Meaning \\ \hline \begin{tabular}{l l l} pseudoinstruction & Base Instruction & Meaning \\ \hline +{\tt j offset} & {\tt jal x0, offset} & Jump \\ +{\tt jal offset} & {\tt jal x1, offset} & Jump and link \\ +{\tt jr rs} & {\tt jalr x0, 0(rs)} & Jump register \\ +{\tt jalr rs} & {\tt jalr x1, 0(rs)} & Jump and link register \\ +{\tt ret} & {\tt jalr x0, 0(x1)} & Return from subroutine \\ +\tt call offset & {\tt auipc x1, ${\tt offset[31:12]} + {\tt offset[11]}$} & Call far-away subroutine \\ + & {\tt jalr x1, offset[11:0](x1)} & \\ +\tt tail offset & {\tt auipc x6, ${\tt offset[31:12]} + {\tt offset[11]}$} & Tail call far-away subroutine \\ + & {\tt jalr x0, offset[11:0](x6)} & \\ +\hline +{\tt fence} & {\tt fence iorw, iorw} & Fence on all memory and I/O \\ +\hline {\tt rdinstret[h] rd} & {\tt csrrs rd, instret[h], x0} & Read instructions-retired counter \\ {\tt rdcycle[h] rd} & {\tt csrrs rd, cycle[h], x0} & Read cycle counter \\ {\tt rdtime[h] rd} & {\tt csrrs rd, time[h], x0} & Read real-time clock \\ |