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author | Andrew Waterman <andrew@sifive.com> | 2019-06-25 17:10:10 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-06-25 17:10:10 -0700 |
commit | 50822297ef9ce9bf35d1853453804aaea7609df8 (patch) | |
tree | 48a69776e63cbff9a006d1fc22b4f60281634e47 | |
parent | 2f0c6aeadd8114a71cdd290bd4ec07fbe8cb68fc (diff) | |
download | riscv-isa-manual-50822297ef9ce9bf35d1853453804aaea7609df8.zip riscv-isa-manual-50822297ef9ce9bf35d1853453804aaea7609df8.tar.gz riscv-isa-manual-50822297ef9ce9bf35d1853453804aaea7609df8.tar.bz2 |
Touch up the mcycle text
-rw-r--r-- | src/machine.tex | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/machine.tex b/src/machine.tex index cde159e..34c7046 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1684,9 +1684,11 @@ precision on all RV32 and RV64 systems. The counter registers have an arbitrary value after system reset, and can be written with a given value. Any CSR write takes effect after -the writing instruction has otherwise completed. Writes to {\tt mcycle} on one -hart may change the value of {\tt mcycle} on other harts, the platform must -provide a mechanism to indicate when this behavior will occur. +the writing instruction has otherwise completed. +The {\tt mcycle} CSR may be shared between harts on the same core, in which +case writes to {\tt mcycle} will be visible to those harts. +The platform should provide a mechanism to indicate which harts share an {\tt +mcycle} CSR. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt @@ -1895,9 +1897,11 @@ their accessibility is not affected by the setting of this register. When the CY, IR, or HPM{\em n} bit in the {\tt mcountinhibit} register is clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register increments as usual. When the CY, IR, or HPM{\em n} bit is set, the -corresponding counter does not increment. Writes to {\tt mcountinhibit}.CY may -change the value of {\tt mcountintihib}.CY on other harts, the platform must -provide a mechanism to indicate when this behavior will occur. +corresponding counter does not increment. + +The {\tt mcycle} CSR may be shared between harts on the same core, in which +case the {\tt mcountinhibit}.CY field is also shared between those harts, +and so writes to {\tt mcountinhibit}.CY will be visible to those harts. If the {\tt mcountinhibit} register is not implemented, the implementation behaves as though the register were set to zero. @@ -1908,9 +1912,6 @@ desirable to conditionally inhibit them to reduce energy consumption. Providing a single CSR to inhibit all counters also allows the counters to be atomically sampled. -As all the harts on a processor core may share a {\tt cycle} counter, -so they share an {\tt mcountinhibit}.CY bit. - Because the {\tt time} counter can be shared between multiple cores, it cannot be inhibited with the {\tt mcountinhibit} mechanism. \end{commentary} |