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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-21 16:17:40 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-21 16:17:40 -0800 |
| commit | 3b4c695efcb7933ca9b647913792ccb04db02553 (patch) | |
| tree | edd5908ba528179823e5445066de98e2f79780c4 | |
| parent | 9674e5a7ea75291071aeab086c260e133cf8e31d (diff) | |
| download | riscv-isa-manual-3b4c695efcb7933ca9b647913792ccb04db02553.zip riscv-isa-manual-3b4c695efcb7933ca9b647913792ccb04db02553.tar.gz riscv-isa-manual-3b4c695efcb7933ca9b647913792ccb04db02553.tar.bz2 | |
tweaks
| -rw-r--r-- | src/machine.tex | 5 | ||||
| -rw-r--r-- | src/rv32.tex | 2 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index d42b7a3..1921b03 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2172,9 +2172,8 @@ The Wait for Interrupt instruction (WFI) provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing. Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should -preferentially be routed to this hart. WFI is available in all of the -supported S and M privilege modes, and optionally available to -U-mode for implementations that support U-mode interrupts. This instruction may +preferentially be routed to this hart. WFI is available in all +privileged modes, and optionally available to U-mode. This instruction may raise an illegal instruction exception when TW=1 in {\tt mstatus}, as described in Section~\ref{virt-control}. diff --git a/src/rv32.tex b/src/rv32.tex index 7b6368d..92a310f 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1177,7 +1177,7 @@ ordered as device input and device output operations respectively rather than memory reads and writes. For example, memory-mapped I/O devices will typically be accessed with uncached loads and stores that are ordered using the I and O bits rather than the R and W bits. -Instruction-set extensions might also describe new coprocessor I/O +Instruction-set extensions might also describe new I/O instructions that will also be ordered using the I and O bits in a FENCE. |