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| author | Andrew Waterman <andrew@sifive.com> | 2019-02-22 14:12:23 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-02-22 14:12:23 -0800 |
| commit | 340287d72766324863a817c4cfa59555dce33a59 (patch) | |
| tree | cf4b9770562e55097d8124c7a5e1eca777703420 | |
| parent | e67203b8b608586e1cce0578e5f575ed317f253c (diff) | |
| download | riscv-isa-manual-340287d72766324863a817c4cfa59555dce33a59.zip riscv-isa-manual-340287d72766324863a817c4cfa59555dce33a59.tar.gz riscv-isa-manual-340287d72766324863a817c4cfa59555dce33a59.tar.bz2 | |
Add misa to reset section
We describe how misa is reset earlier in the chapter, but accidentally
omitted it from the list of registers that are reset.
Resolves #342
| -rw-r--r-- | src/machine.tex | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index f0c7627..390a5a7 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -17,6 +17,7 @@ In addition to the machine-level CSRs described in this section, M-mode code can access all CSRs at lower privilege levels. \subsection{Machine ISA Register {\tt misa}} +\label{sec:misa} The {\tt misa} CSR is a \warl\ read-write register reporting the ISA supported by the hart. This register must be @@ -2267,7 +2268,10 @@ arrival. \label{sec:reset} Upon reset, a hart's privilege mode is set to M. The {\tt mstatus} fields MIE -and MPRV are reset to 0. The {\tt pc} is set to an implementation-defined +and MPRV are reset to 0. +The {\tt misa} register is reset to enable the maximal set of supported +extensions and widest MXLEN, as described in Section~\ref{sec:misa}. +The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. Writable PMP registers' A and L fields are set to 0. All other hart state is unspecified. |