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| author | Andrew Waterman <andrew@sifive.com> | 2019-02-23 20:22:55 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-02-23 20:22:55 -0800 |
| commit | 16f5e5c5da86e28b3289e224d69a75a4df99b762 (patch) | |
| tree | 1a3db1700d6e2ca95b78ed8228176e8087cddcfa | |
| parent | cbc2663ef7df1b2bcda627740d94f3e95adbc141 (diff) | |
| download | riscv-isa-manual-16f5e5c5da86e28b3289e224d69a75a4df99b762.zip riscv-isa-manual-16f5e5c5da86e28b3289e224d69a75a4df99b762.tar.gz riscv-isa-manual-16f5e5c5da86e28b3289e224d69a75a4df99b762.tar.bz2 | |
tweak
| -rw-r--r-- | src/f.tex | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -486,8 +486,8 @@ were defined to negate the sum, rather than negating the product as the RISC-V instructions do, so the naming scheme was more rational at the time. The two definitions differ with respect to signed-zero results. The RISC-V definition matches the behavior of the x86 and ARM fused multiply-add -instructions, but unfortunately the RISC-V instruction names do not match -that of x86 and ARM. +instructions, but unfortunately the RISC-V instruction names are swapped +with those of x86 and ARM. \end{commentary} \vspace{-0.2in} |