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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-24 17:50:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-24 17:50:21 -0700 |
| commit | 0b25db1fa7477b35cc7a3664a079a71ec4879165 (patch) | |
| tree | ed8ccdb2a572fc840d2ca7a14ebee6d005324e5d | |
| parent | 6993896ac6824b7c7559b7f41ecaa0daf77a8cbe (diff) | |
| download | riscv-isa-manual-0b25db1fa7477b35cc7a3664a079a71ec4879165.zip riscv-isa-manual-0b25db1fa7477b35cc7a3664a079a71ec4879165.tar.gz riscv-isa-manual-0b25db1fa7477b35cc7a3664a079a71ec4879165.tar.bz2 | |
Clarify that, if all PMPs are OFF, all S/U accesses fail
Closes #399
| -rw-r--r-- | src/machine.tex | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 302a620..8e3282e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -3268,6 +3268,11 @@ If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails. +\begin{commentary} +If at least one PMP entry is implemented, but all PMP entries' A fields are +set to OFF, then all S-mode and U-mode memory accesses will fail. +\end{commentary} + Failed accesses generate a load, store, or instruction access exception. Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access exception is generated if at least one access |