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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 13:08:44 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 13:08:44 -0700 |
| commit | 08005b8ecc728b3764d57d892a5e6727bfcf0555 (patch) | |
| tree | 584030ad41917b02b7ce8261d34949afe848509f | |
| parent | e554c939026818337038cf2ac91d9e24d494f820 (diff) | |
| download | riscv-isa-manual-08005b8ecc728b3764d57d892a5e6727bfcf0555.zip riscv-isa-manual-08005b8ecc728b3764d57d892a5e6727bfcf0555.tar.gz riscv-isa-manual-08005b8ecc728b3764d57d892a5e6727bfcf0555.tar.bz2 | |
Add mstatush to preface
| -rw-r--r-- | src/priv-preface.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 1ce8d4e..660a412 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -29,6 +29,8 @@ Changes from version 1.11 include: \begin{itemize} \parskip 0pt \itemsep 1pt +\item Defined the RV32-only CSR {\tt mstatush}, which contains most of the + same fields as the upper 32 bits of RV64's {\tt mstatus}. \item A revised hypervisor architecture proposal that represents VS-mode CSR state more simply. \item Added optional big-endian and bi-endian support. |