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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 11:56:18 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 11:56:18 -0700 |
| commit | 009829465918a84ced119df9a5eaf725c2de62cc (patch) | |
| tree | c206f107eef13ad5185a3d36086041288f9f140f | |
| parent | f4401aa271842098bc5aa4bc89be95a500fff826 (diff) | |
| download | riscv-isa-manual-009829465918a84ced119df9a5eaf725c2de62cc.zip riscv-isa-manual-009829465918a84ced119df9a5eaf725c2de62cc.tar.gz riscv-isa-manual-009829465918a84ced119df9a5eaf725c2de62cc.tar.bz2 | |
Bi-endian systems reset as little-endian
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index dcf17f3..9d4fe06 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2458,6 +2458,8 @@ arrival. Upon reset, a hart's privilege mode is set to M. The {\tt mstatus} fields MIE and MPRV are reset to 0. +If little-endian memory accesses are supported, the {\tt mstatus}/{\tt mstatush} +field MBE is reset to 0. The {\tt misa} register is reset to enable the maximal set of supported extensions and widest MXLEN, as described in Section~\ref{sec:misa}. The {\tt pc} is set to an implementation-defined |