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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2021-06-14 03:38:19 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-02 16:46:30 -0700 |
| commit | b422dae1c3ad048527b0b8a0c5fc0388e7c9e592 (patch) | |
| tree | f5725930d16a3cd053cd73d5254f7da0f533e4d0 | |
| parent | 1c02a1ff0a8eea05ac7192bc54e15a6f35ac9da4 (diff) | |
| download | riscv-isa-manual-b422dae1c3ad048527b0b8a0c5fc0388e7c9e592.zip riscv-isa-manual-b422dae1c3ad048527b0b8a0c5fc0388e7c9e592.tar.gz riscv-isa-manual-b422dae1c3ad048527b0b8a0c5fc0388e7c9e592.tar.bz2 | |
Removed "baseline" from description of F extension in comment.
| -rw-r--r-- | src/zfinx.tex | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/zfinx.tex b/src/zfinx.tex index 404bac2..ab67d7a 100644 --- a/src/zfinx.tex +++ b/src/zfinx.tex @@ -7,9 +7,8 @@ extensions, but that operate on the {\tt x} registers instead of the {\tt f} registers. \begin{commentary} -The baseline F extension uses separate {\tt f} registers for floating-point -computation. -This design reduces register pressure and simplifies the provision of +The F extension uses separate {\tt f} registers for floating-point +computation, to reduce register pressure and simplifies the provision of register-file ports for wide superscalars. However, the additional \wunits{128}{B} of architectural state increases the minimal implementation cost. |