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| author | John Hauser <31252952+jhauser-us@users.noreply.github.com> | 2021-08-16 12:53:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-16 12:53:23 -0700 |
| commit | 3181456e0280fcb0c42d693806f4b88b59743774 (patch) | |
| tree | b528d93166284e63c6b445018c84d98ba3345638 | |
| parent | 7d0006ed81cfab6a4a09578e91e238e88b1b4b62 (diff) | |
| download | riscv-isa-manual-3181456e0280fcb0c42d693806f4b88b59743774.zip riscv-isa-manual-3181456e0280fcb0c42d693806f4b88b59743774.tar.gz riscv-isa-manual-3181456e0280fcb0c42d693806f4b88b59743774.tar.bz2 | |
Minor improvements to text for virtual instruction exceptions (#709)
| -rw-r--r-- | src/hypervisor.tex | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index ba7e797..78de7e1 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -2630,7 +2630,7 @@ separately. When V=1, a virtual instruction exception (code 22) is normally raised instead of an illegal instruction exception if the attempted instruction is \textit{HS-qualified} -but is prevented when V=1 due to +but is prevented from executing when V=1 due to insufficient privilege or because the instruction is expressly disabled by a hypervisor CSR such as {\tt hcounteren}. An instruction is \textit{HS-qualified} if it would be valid to execute @@ -2663,7 +2663,7 @@ by an extension. \end{commentary} Specifically, a virtual instruction exception is raised for the -following cases, not necessarily a complete list: +following cases: \begin{itemize} \item @@ -2718,6 +2718,9 @@ in VS-mode, attempts to execute an SFENCE instruction or to access {\tt satp}, when {\tt hstatus}.VTVM=1. \end{itemize} +Other extensions to the \mbox{RISC-V} Privileged Architecture may add +to the set of circumstances that cause a virtual instruction exception +when V=1. On a virtual instruction trap, {\tt mtval} or {\tt stval} is written the same as for an illegal instruction trap. |