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| author | Andrew Waterman <andrew@sifive.com> | 2021-05-11 02:31:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-02 16:46:30 -0700 |
| commit | 04cfc0e7be8acded973627ebf9568525c293d464 (patch) | |
| tree | 4f948618293e062d8fff48699ff04a0bacfa40ba | |
| parent | 9025a7f4a7a66e5f7b6e69522db21115b7a5b916 (diff) | |
| download | riscv-isa-manual-04cfc0e7be8acded973627ebf9568525c293d464.zip riscv-isa-manual-04cfc0e7be8acded973627ebf9568525c293d464.tar.gz riscv-isa-manual-04cfc0e7be8acded973627ebf9568525c293d464.tar.bz2 | |
improve wording
| -rw-r--r-- | src/zfinx.tex | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/zfinx.tex b/src/zfinx.tex index 6e61c59..6e12de2 100644 --- a/src/zfinx.tex +++ b/src/zfinx.tex @@ -16,12 +16,11 @@ minimal implementation cost. By eliminating the {\tt f} registers, the Zfinx extension substantially reduces the cost of simple RISC-V implementations with floating-point instruction-set support. -Zfinx also reduces context-switch effort. +Zfinx also reduces context-switch cost. -Unlike most RISC-V extensions, the addition of Zfinx is not backwards -compatible: software that uses floating-point instructions but assumes the -absence of the Zfinx extension will not, in general, execute correctly on -implementations with the Zfinx extension. +In general, software that assumes the presence of the F extension +is incompatible with software that assumes the presence of the Zfinx +extension, and vice versa. \end{commentary} The Zfinx extension adds all of the instructions that the F extension |