diff options
| author | Andrew Waterman <andrew@sifive.com> | 2019-08-30 12:59:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-08-30 12:59:53 -0700 |
| commit | fb2ea70991e94771ee9824a0a110a07d95186214 (patch) | |
| tree | 5c78cddba0a3e4a2e9df9f22f0d35308aee98d08 | |
| parent | d7d1c0c539510233bc8c685e78217a3801a1ab6f (diff) | |
| download | riscv-isa-manual-fb2ea70991e94771ee9824a0a110a07d95186214.zip riscv-isa-manual-fb2ea70991e94771ee9824a0a110a07d95186214.tar.gz riscv-isa-manual-fb2ea70991e94771ee9824a0a110a07d95186214.tar.bz2 | |
mstatus TVM, TW, and TSR are WARL fields
| -rw-r--r-- | src/machine.tex | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index bb02579..4d58647 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -808,7 +808,7 @@ example by swapping byte order after loads and before stores. \subsubsection{Virtualization Support in {\tt mstatus} Register} \label{virt-control} -The TVM (Trap Virtual Memory) bit supports intercepting +The TVM (Trap Virtual Memory) bit is a \warl\ field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the {\tt satp} CSR or execute the SFENCE.VMA instruction while executing in S-mode will raise an illegal instruction @@ -825,8 +825,9 @@ Trapping {\tt satp} accesses and the SFENCE.VMA instruction provides the hooks necessary to lazily populate shadow page tables. \end{commentary} -The TW (Timeout Wait) bit supports intercepting the WFI instruction (see -Section~\ref{wfi}). When TW=0, the WFI instruction may execute in lower +The TW (Timeout Wait) bit is a \warl\ field that supports intercepting the WFI +instruction (see Section~\ref{wfi}). +When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction @@ -847,7 +848,8 @@ bounded time limit. A future revision of this specification might add a feature that allows S-mode to selectively permit WFI in U-mode. Such a feature would only be active when TW=0. -The TSR (Trap SRET) bit supports intercepting the supervisor exception return +The TSR (Trap SRET) bit is a \warl\ field that +supports intercepting the supervisor exception return instruction, SRET. When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction exception. When TSR=0, this operation is permitted in S-mode. TSR is hard-wired to 0 when S-mode is not |