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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-25 15:25:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-10-02 17:25:50 +0200 |
| commit | a9d00eec3b67739532e41ff64580876d27e3464c (patch) | |
| tree | d5b1c6134a168a76cdca7a994af595c4177a7ad0 | |
| parent | da4b1faaec9c92bff499b5ec4d02300fb3bbc4c5 (diff) | |
| download | riscv-isa-manual-a9d00eec3b67739532e41ff64580876d27e3464c.zip riscv-isa-manual-a9d00eec3b67739532e41ff64580876d27e3464c.tar.gz riscv-isa-manual-a9d00eec3b67739532e41ff64580876d27e3464c.tar.bz2 | |
Constrained loops must use same *virtual* address for SC
| -rw-r--r-- | src/a.tex | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -261,8 +261,8 @@ the following properties: constraint as the code between the LR and SC. \item The LR address must lie either within a main memory region or within some other memory region specified by the execution environment. -\item The SC must be to the same address and of the same data size as the - latest LR executed by the same hart. +\item The SC must be to the same virtual address and of the same data size as + the latest LR executed by the same hart. \end{itemize} LR/SC sequences that do not lie within constrained LR/SC loops are {\em |