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| author | Bill Traynor <wmat@riscv.org> | 2024-03-20 16:25:01 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-20 16:25:01 -0400 |
| commit | dd33cca23176277dfa94a3fff44eeb781503e07e (patch) | |
| tree | 07b9e851b85b5d40a9379dd0b9a29737ed91fb28 | |
| parent | 56f19ae7d0b2a4e006ac13906f8afc3490aaf876 (diff) | |
| parent | b824d33cb64b1a6b5f7ded702d8ac4f93dbc3e05 (diff) | |
| download | riscv-isa-manual-dd33cca23176277dfa94a3fff44eeb781503e07e.zip riscv-isa-manual-dd33cca23176277dfa94a3fff44eeb781503e07e.tar.gz riscv-isa-manual-dd33cca23176277dfa94a3fff44eeb781503e07e.tar.bz2 | |
Merge branch 'main' into zicond
Signed-off-by: Bill Traynor <wmat@riscv.org>
35 files changed, 23424 insertions, 30 deletions
diff --git a/build/Makefile b/build/Makefile index eef7da5..fad4fbc 100644 --- a/build/Makefile +++ b/build/Makefile @@ -91,3 +91,4 @@ clean: echo "Removing unpriv-isa-asciidoc.html"; \ rm -f unpriv-isa-asciidoc.html; \ fi + diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc index 9240f6e..52beb61 100644 --- a/src/b-st-ext.adoc +++ b/src/b-st-ext.adoc @@ -1,18 +1,3901 @@ [[bits]] -== "B" Standard Extension for Bit Manipulation, Version 0.0 +== "B" Standard Extension for Bit Manipulation, Version 1.0.0 -This chapter is a placeholder for a future standard extension to provide -bit manipulation instructions, including instructions to insert, -extract, and test bit fields, and for rotations, funnel shifts, and bit -and byte permutations. -[NOTE] +[[preface]] +=== Bit-manipulation a, b, c and s extensions grouped for public review and ratification + +The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. +While the instructions are intended to have general use, some instructions are more useful in some domains than others. +Hence, several smaller bitmanip extensions are provided, rather than one large extension. +Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name. + +Each bitmanip extension includes a group of several bitmanip instructions that have similar purposes and that can often share the same logic. Some instructions are available in only one extension while others are available in several. +The instructions have mnemonics and encodings that are independent of the extensions in which they appear. +Thus, when implementing extensions with overlapping instructions, there is no redundancy in logic or encoding. + +The bitmanip extensions are defined for RV32 and RV64. +Most of the instructions are expected to be forward compatible with RV128. +While the shift-immediate instructions are defined to have at most a 6-bit immediate field, a 7th bit is available in the encoding space should this be needed for RV128. + +=== Word Instructions + +The bitmanip extension follows the convention in RV64 that _w_-suffixed instructions (without a dot before the _w_) ignore the upper 32 bits of their inputs, operate on the least-significant 32-bits as signed values and produce a 32-bit signed result that is sign-extended to XLEN. + +Bitmanip instructions with the suffix _.uw_ have one operand that is an unsigned 32-bit value that is extracted from the least significant 32 bits of the specified register. Other than that, these perform full XLEN operations. + +Bitmanip instructions with the suffix _.b_, _.h_ and _.w_ only look at the least significant 8-bits, 16-bits and 32-bits of the input (respectively) and produce an XLEN-wide result that is sign-extended or zero-extended, based on the specific instruction. + +=== Pseudocode for instruction semantics + +The semantics of each instruction in <<#insns>> is expressed in a SAIL-like syntax. + +=== Extensions + +The first group of bitmanip extensions to be released for Public Review are: + +* <<#zba>> +* <<#zbb>> +* <<#zbc>> +* <<#zbs>> + +Below is a list of all of the instructions (and pseudoinstructions) that are included in these extensions +along with their specific mapping: + +[%header,cols="^3,^3,10,16,^2,^2,^2,^2"] +|==== +|RV32 +|RV64 +|Mnemonic +|Instruction +|Zba +|Zbb +|Zbc +|Zbs + +| +|✓ +|add.uw _rd_, _rs1_, _rs2_ +|<<#insns-add_uw>> +|✓ +| +| +| + +|✓ +|✓ +|andn _rd_, _rs1_, _rs2_ +|<<#insns-andn>> +| +|✓ +| +| + + +|✓ +|✓ +|clmul _rd_, _rs1_, _rs2_ +|<<#insns-clmul>> +| +| +|✓ +| + +|✓ +|✓ +|clmulh _rd_, _rs1_, _rs2_ +|<<#insns-clmulh>> +| +| +|✓ +| + +|✓ +|✓ +|clmulr _rd_, _rs1_, _rs2_ +|<<#insns-clmulr>> +| +| +|✓ +| + +|✓ +|✓ +|clz _rd_, _rs_ +|<<#insns-clz>> +| +|✓ +| +| + +| +|✓ +|clzw _rd_, _rs_ +|<<#insns-clzw>> +| +|✓ +| +| +|✓ +|✓ +|cpop _rd_, _rs_ +|<<#insns-cpop>> +| +|✓ +| +| + +| +|✓ +|cpopw _rd_, _rs_ +|<<#insns-cpopw>> +| +|✓ +| +| + +|✓ +|✓ +|ctz _rd_, _rs_ +|<<#insns-ctz>> +| +|✓ +| +| + +| +|✓ +|ctzw _rd_, _rs_ +|<<#insns-ctzw>> +| +|✓ +| +| + +|✓ +|✓ +|max _rd_, _rs1_, _rs2_ +|<<#insns-max>> +| +|✓ +| +| + +|✓ +|✓ +|maxu _rd_, _rs1_, _rs2_ +|<<#insns-maxu>> +| +|✓ +| +| + +|✓ +|✓ +|min _rd_, _rs1_, _rs2_ +|<<#insns-min>> +| +|✓ +| +| + +|✓ +|✓ +|minu _rd_, _rs1_, _rs2_ +|<<#insns-minu>> +| +|✓ +| +| + +|✓ +|✓ +|orc.b _rd_, _rs1_, _rs2_ +|<<#insns-orc_b>> +| +|✓ +| +| + +|✓ +|✓ +|orn _rd_, _rs1_, _rs2_ +|<<#insns-orn>> +| +|✓ +| +| + +|✓ +|✓ +|rev8 _rd_, _rs_ +|<<#insns-rev8>> +| +|✓ +| +| + +|✓ +|✓ +|rol _rd_, _rs1_, _rs2_ +|<<#insns-rol>> +| +|✓ +| +| + +| +|✓ +|rolw _rd_, _rs1_, _rs2_ +|<<#insns-rolw>> +| +|✓ +| +| + +|✓ +|✓ +|ror _rd_, _rs1_, _rs2_ +|<<#insns-ror>> +| +|✓ +| +| + +|✓ +|✓ +|rori _rd_, _rs1_, _shamt_ +|<<#insns-rori>> +| +|✓ +| +| + +| +|✓ +|roriw _rd_, _rs1_, _shamt_ +|<<#insns-roriw>> +| +|✓ +| +| + +| +|✓ +|rorw _rd_, _rs1_, _rs2_ +|<<#insns-rorw>> +| +|✓ +| +| + +|✓ +|✓ +|bclr _rd_, _rs1_, _rs2_ +|<<#insns-bclr>> +| +| +| +|✓ + +|✓ +|✓ +|bclri _rd_, _rs1_, _imm_ +|<<#insns-bclri>> +| +| +| +|✓ + +|✓ +|✓ +|bext _rd_, _rs1_, _rs2_ +|<<#insns-bext>> +| +| +| +|✓ + +|✓ +|✓ +|bexti _rd_, _rs1_, _imm_ +|<<#insns-bexti>> +| +| +| +|✓ + +|✓ +|✓ +|binv _rd_, _rs1_, _rs2_ +|<<#insns-binv>> +| +| +| +|✓ + +|✓ +|✓ +|binvi _rd_, _rs1_, _imm_ +|<<#insns-binvi>> +| +| +| +|✓ + +|✓ +|✓ +|bset _rd_, _rs1_, _rs2_ +|<<#insns-bset>> +| +| +| +|✓ + +|✓ +|✓ +|bseti _rd_, _rs1_, _imm_ +|<<#insns-bseti>> +| +| +| +|✓ + +|✓ +|✓ +|sext.b _rd_, _rs_ +|<<#insns-sext_b>> +| +|✓ +| +| + +|✓ +|✓ +|sext.h _rd_, _rs_ +|<<#insns-sext_h>> +| +|✓ +| +| + +|✓ +|✓ +|sh1add _rd_, _rs1_, _rs2_ +|<<#insns-sh1add>> +|✓ +| +| +| + +| +|✓ +|sh1add.uw _rd_, _rs1_, _rs2_ +|<<#insns-sh1add_uw>> +|✓ +| +| +| + +|✓ +|✓ +|sh2add _rd_, _rs1_, _rs2_ +|<<#insns-sh2add>> +|✓ +| +| +| + +| +|✓ +|sh2add.uw _rd_, _rs1_, _rs2_ +|<<#insns-sh2add_uw>> +|✓ +| +| +| + +|✓ +|✓ +|sh3add _rd_, _rs1_, _rs2_ +|<<#insns-sh3add>> +|✓ +| +| +| + +| +|✓ +|sh3add.uw _rd_, _rs1_, _rs2_ +|<<#insns-sh3add_uw>> +|✓ +| +| +| + +| +|✓ +|slli.uw _rd_, _rs1_, _imm_ +|<<#insns-slli_uw>> +|✓ +| +| +| + +|✓ +|✓ +|xnor _rd_, _rs1_, _rs2_ +|<<#insns-xnor>> +| +|✓ +| +| + +|✓ +|✓ +|zext.h _rd_, _rs_ +|<<#insns-zext_h>> +| +|✓ +| +| + +| +|✓ +|zext.w _rd_, _rs_ +|<<#insns-add_uw>> +|✓ +| +| +| + +|==== + +[#zba,reftext=Address generation instructions] +==== Zba: Address generation + +[NOTE,caption=Frozen] +==== +The Zba extension is frozen. +==== + +The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. + +The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. + +While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw -- added in this extension -- can be used when the index is to be interpreted as an unsigned word. + +The following instructions (and pseudoinstructions) comprise the Zba extension: + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| +|✓ +|add.uw _rd_, _rs1_, _rs2_ +|<<#insns-add_uw>> + +|✓ +|✓ +|sh1add _rd_, _rs1_, _rs2_ +|<<#insns-sh1add>> + +| +|✓ +|sh1add.uw _rd_, _rs1_, _rs2_ +|<<#insns-sh1add_uw>> + +|✓ +|✓ +|sh2add _rd_, _rs1_, _rs2_ +|<<#insns-sh2add>> + +| +|✓ +|sh2add.uw _rd_, _rs1_, _rs2_ +|<<#insns-sh2add_uw>> + +|✓ +|✓ +|sh3add _rd_, _rs1_, _rs2_ +|<<#insns-sh3add>> + +| +|✓ +|sh3add.uw _rd_, _rs1_, _rs2_ +|<<#insns-sh3add_uw>> + +| +|✓ +|slli.uw _rd_, _rs1_, _imm_ +|<<#insns-slli_uw>> + +| +|✓ +|zext.w _rd_, _rs_ +|<<#insns-add_uw>> + +|=== + +[#zbb,reftext="Basic bit-manipulation"] +==== Zbb: Basic bit-manipulation + +[NOTE,caption=Frozen] ==== -Although bit manipulation instructions are very effective in some -application domains, particularly when dealing with externally packed -data structures, we excluded them from the base ISAs as they are not -useful in all domains and can add additional complexity or instruction -formats to supply all needed operands. +The Zbb extension is frozen. +==== +===== Logical with negate + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|andn _rd_, _rs1_, _rs2_ +|<<#insns-andn>> + +|✓ +|✓ +|orn _rd_, _rs1_, _rs2_ +|<<#insns-orn>> + +|✓ +|✓ +|xnor _rd_, _rs1_, _rs2_ +|<<#insns-xnor>> +|=== + +.Implementation Hint +[NOTE, caption="Imp" ] +=============================================================== +The Logical with Negate instructions can be implemented by inverting the _rs2_ inputs to the base-required AND, OR, and XOR logic instructions. +In some implementations, the inverter on rs2 used for subtraction can be reused for this purpose. +=============================================================== + +===== Count leading/trailing zero bits + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|clz _rd_, _rs_ +|<<#insns-clz>> + +| +|✓ +|clzw _rd_, _rs_ +|<<#insns-clzw>> + +|✓ +|✓ +|ctz _rd_, _rs_ +|<<#insns-ctz>> + +| +|✓ +|ctzw _rd_, _rs_ +|<<#insns-ctzw>> +|=== + +===== Count population + +These instructions count the number of set bits (1-bits). This is also +commonly referred to as population count. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|cpop _rd_, _rs_ +|<<#insns-cpop>> + +| +|✓ +|cpopw _rd_, _rs_ +|<<#insns-cpopw>> +|=== + +===== Integer minimum/maximum + +The integer minimum/maximum instructions are arithmetic R-type +instructions that return the smaller/larger of two operands. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|max _rd_, _rs1_, _rs2_ +|<<#insns-max>> + +|✓ +|✓ +|maxu _rd_, _rs1_, _rs2_ +|<<#insns-maxu>> + +|✓ +|✓ +|min _rd_, _rs1_, _rs2_ +|<<#insns-min>> + +|✓ +|✓ +|minu _rd_, _rs1_, _rs2_ +|<<#insns-minu>> +|=== + +===== Sign- and zero-extension + +These instructions perform the sign-extension or zero-extension of the least significant 8 bits or 16 bits of the source register. + +These instructions replace the generalized idioms `slli rD,rS,(XLEN-<size>) + srli` (for zero-extension) or `slli + srai` (for sign-extension) for the sign-extension of 8-bit and 16-bit quantities, and for the zero-extension of 16-bit quantities. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|sext.b _rd_, _rs_ +|<<#insns-sext_b>> + +|✓ +|✓ +|sext.h _rd_, _rs_ +|<<#insns-sext_h>> + +|✓ +|✓ +|zext.h _rd_, _rs_ +|<<#insns-zext_h>> +|=== + +===== Bitwise rotation + +Bitwise rotation instructions are similar to the shift-logical operations from the base spec. However, where the shift-logical +instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value. +Such operations are also referred to as ‘circular shifts’. + + + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|rol _rd_, _rs1_, _rs2_ +|<<#insns-rol>> + +| +|✓ +|rolw _rd_, _rs1_, _rs2_ +|<<#insns-rolw>> + +|✓ +|✓ +|ror _rd_, _rs1_, _rs2_ +|<<#insns-ror>> + +|✓ +|✓ +|rori _rd_, _rs1_, _shamt_ +|<<#insns-rori>> + +| +|✓ +|roriw _rd_, _rs1_, _shamt_ +|<<#insns-roriw>> + +| +|✓ +|rorw _rd_, _rs1_, _rs2_ +|<<#insns-rorw>> +|=== + +.Architecture Explanation +[NOTE, caption="AE" ] +=============================================================== +The rotate instructions were included to replace a common +four-instruction sequence to achieve the same effect (neg; sll/srl; srl/sll; or) +=============================================================== + +===== OR Combine + +*orc.b* sets the bits of each byte in the result _rd_ to all zeros if no bit within the respective byte of _rs_ is set, or to all ones if any bit within the respective byte of _rs_ is set. + +One use-case is string-processing functions, such as *strlen* and *strcpy*, which can use *orc.b* to test for the terminating zero byte by counting the set bits in leading non-zero bytes in a word. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|orc.b _rd_, _rs_ +|<<#insns-orc_b>> +|=== + +===== Byte-reverse + +*rev8* reverses the byte-ordering of _rs_. + +[%header,cols="^1,^1,4,8"] +|==== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|rev8 _rd_, _rs_ +|<<#insns-rev8>> + +|==== + +[#zbc,reftext="Carry-less multiplication"] +==== Zbc: Carry-less multiplication + +[NOTE,caption=Frozen] +==== +The Zbc extension is frozen. +==== + +Carry-less multiplication is the multiplication in the polynomial ring over GF(2). + +*clmul* produces the lower half of the carry-less product and *clmulh* produces the upper half of the 2✕XLEN carry-less product. + +*clmulr* produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|clmul _rd_, _rs1_, _rs2_ +|<<#insns-clmul>> + +|✓ +|✓ +|clmulh _rd_, _rs1_, _rs2_ +|<<#insns-clmulh>> + +|✓ +|✓ +|clmulr _rd_, _rs1_, _rs2_ +|<<#insns-clmulr>> + +|=== + +[#zbs,reftext="Single-bit instructions"] +==== Zbs: Single-bit instructions + +[NOTE,caption=Frozen] +==== +The Zbs extension is frozen. +==== + +The single-bit instructions provide a mechanism to set, clear, invert, or extract +a single bit in a register. The bit is specified by its index. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|bclr _rd_, _rs1_, _rs2_ +|<<#insns-bclr>> + +|✓ +|✓ +|bclri _rd_, _rs1_, _imm_ +|<<#insns-bclri>> + +|✓ +|✓ +|bext _rd_, _rs1_, _rs2_ +|<<#insns-bext>> + +|✓ +|✓ +|bexti _rd_, _rs1_, _imm_ +|<<#insns-bexti>> + +|✓ +|✓ +|binv _rd_, _rs1_, _rs2_ +|<<#insns-binv>> + +|✓ +|✓ +|binvi _rd_, _rs1_, _imm_ +|<<#insns-binvi>> + +|✓ +|✓ +|bset _rd_, _rs1_, _rs2_ +|<<#insns-bset>> + +|✓ +|✓ +|bseti _rd_, _rs1_, _imm_ +|<<#insns-bseti>> + +|=== + +[#zbkc,reftext="Carry-less multiplication for Cryptography"] +==== Zbkc: Carry-less multiplication for Cryptography + +[NOTE,caption=Frozen] +==== +The Zbkc extension is frozen. +==== + +Carry-less multiplication is the multiplication in the polynomial ring over +GF(2). This is a critical operation in some cryptographic workloads, +particularly the AES-GCM authenticated encryption scheme. +This extension provides only the instructions needed to +efficiently implement the GHASH operation, which is part of this workload. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|clmul _rd_, _rs1_, _rs2_ +|<<#insns-clmul>> + +|✓ +|✓ +|clmulh _rd_, _rs1_, _rs2_ +|<<#insns-clmulh>> + +|=== + +[#zbkx,reftext="Crossbar permutations"] +==== Zbkx: Crossbar permutations + +[NOTE,caption=Frozen] +==== +The Zbkx extension is frozen. +==== + +These instructions implement a "lookup table" for 4 and 8 bit elements +inside the general purpose registers. +_rs1_ is used as a vector of N-bit words, and _rs2_ as a vector of N-bit +indices into _rs1_. +Elements in _rs1_ are replaced by the indexed element in _rs2_, or zero +if the index into _rs2_ is out of bounds. + +These instructions are useful for expressing N-bit to N-bit boolean +operations, and implementing cryptographic code with secret +dependent memory accesses (particularly SBoxes) such that the execution +latency does not depend on the (secret) data being operated on. -We anticipate the B extension will be a brownfield encoding within the -base 30-bit instruction space. +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +|✓ +|✓ +|xperm.n _rd_, _rs1_, _rs2_ +|<<#insns-xpermn>> + +|✓ +|✓ +|xperm.b _rd_, _rs1_, _rs2_ +|<<#insns-xpermb>> + +|=== + +[#zbkb,reftext="Bit-manipulation for Cryptography"] +==== Zbkb: Bit-manipulation for Cryptography + +[NOTE,caption=Frozen] +==== +The Zbkb extension is frozen. ==== + +This extension contains instructions essential for implementing +common operations in cryptographic workloads. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + + +| ✓ +| ✓ +| rol +| <<insns-rol>> + +| +| ✓ +| rolw +| <<insns-rolw>> + +| ✓ +| ✓ +| ror +| <<insns-ror>> + +| ✓ +| ✓ +| rori +| <<insns-rori>> + +| +| ✓ +| roriw +| <<insns-roriw>> + +| +| ✓ +| rorw +| <<insns-rorw>> + +| ✓ +| ✓ +| andn +| <<insns-andn>> + +| ✓ +| ✓ +| orn +| <<insns-orn>> + +| ✓ +| ✓ +| xnor +| <<insns-xnor>> + +| ✓ +| ✓ +| pack +| <<insns-pack>> + +| ✓ +| ✓ +| packh +| <<insns-packh>> + +| +| ✓ +| packw +| <<insns-packw>> + +| ✓ +| ✓ +| rev.b +| <<insns-revb>> + +| ✓ +| ✓ +| rev8 +| <<insns-rev8>> + +| ✓ +| +| zip +| <<insns-zip>> + +| ✓ +| +| unzip +| <<insns-unzip>> + +|=== + +<<< + +[#insns,reftext="Instructions (in alphabetical order)"] +=== Instructions (in alphabetical order) + +[#insns-add_uw,reftext=Add unsigned word] +==== add.uw + +Synopsis:: +Add unsigned word + +Mnemonic:: +add.uw _rd_, _rs1_, _rs2_ + + +Pseudoinstructions:: +zext.w _rd_, _rs1_ → add.uw _rd_, _rs1_, zero + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x0, attr: ['ADD.UW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x04, attr: ['ADD.UW'] }, +]} +.... + +Description:: +This instruction performs an XLEN-wide addition between _rs2_ and the zero-extended least-significant word of _rs1_. + +Operation:: +[source,sail] +-- +let base = X(rs2); +let index = EXTZ(X(rs1)[31..0]); + +X(rd) = base + index; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-andn,reftext="AND with inverted operand"] +==== andn + +Synopsis:: +AND with inverted operand + +Mnemonic:: +andn _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['ANDN']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x20, attr: ['ANDN'] }, +]} +.... + +Description:: +This instruction performs the bitwise logical AND operation between _rs1_ and the bitwise inversion of _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs1) & ~X(rs2); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-bclr,reftext="Single-Bit Clear (Register)"] +==== bclr + +Synopsis:: +Single-Bit Clear (Register) + +Mnemonic:: +bclr _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BCLR'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x24, attr: ['BCLR/BEXT'] }, +]} +.... + +Description:: +This instruction returns _rs1_ with a single bit cleared at the index specified in _rs2_. +The index is read from the lower log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let index = X(rs2) & (XLEN - 1); +X(rd) = X(rs1) & ~(1 << index) +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-bclri,reftext="Single-Bit Clear (Immediate)"] +==== bclri + +Synopsis:: +Single-Bit Clear (Immediate) + +Mnemonic:: +bclri _rd_, _rs1_, _shamt_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BCLRI'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x24, attr: ['BCLRI'] }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BCLRI'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x12, attr: ['BCLRI'] }, +]} +.... + +Description:: +This instruction returns _rs1_ with a single bit cleared at the index specified in _shamt_. +The index is read from the lower log2(XLEN) bits of _shamt_. +For RV32, the encodings corresponding to shamt[5]=1 are reserved. + +Operation:: +[source,sail] +-- +let index = shamt & (XLEN - 1); +X(rd) = X(rs1) & ~(1 << index) +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-bext,reftext="Single-Bit Extract (Register)"] +==== bext + +Synopsis:: +Single-Bit Extract (Register) +// Should we describe this as a Set-if-bit-is-set? + +Mnemonic:: +bext _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['BEXT'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x24, attr: ['BCLR/BEXT'] }, +]} +.... + +Description:: +This instruction returns a single bit extracted from _rs1_ at the index specified in _rs2_. +The index is read from the lower log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let index = X(rs2) & (XLEN - 1); +X(rd) = (X(rs1) >> index) & 1; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-bexti,reftext="Single-Bit Extract (Immediate)"] +==== bexti + +Synopsis:: +Single-Bit Extract (Immediate) + +Mnemonic:: +bexti _rd_, _rs1_, _shamt_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['BEXTI'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x24, attr: ['BEXTI/BCLRI'] }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['BEXTI'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x12, attr: ['BEXTI/BCLRI'] }, +]} +.... + +Description:: +This instruction returns a single bit extracted from _rs1_ at the index specified in _rs2_. +The index is read from the lower log2(XLEN) bits of _shamt_. +For RV32, the encodings corresponding to shamt[5]=1 are reserved. + +Operation:: +[source,sail] +-- +let index = shamt & (XLEN - 1); +X(rd) = (X(rs1) >> index) & 1; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-binv,reftext="Single-Bit Invert (Register)"] +==== binv + +Synopsis:: +Single-Bit Invert (Register) + +Mnemonic:: +binv _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BINV'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x34, attr: ['BINV'] }, +]} +.... + +Description:: +This instruction returns _rs1_ with a single bit inverted at the index specified in _rs2_. +The index is read from the lower log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let index = X(rs2) & (XLEN - 1); +X(rd) = X(rs1) ^ (1 << index) +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-binvi,reftext="Single-Bit Invert (Immediate)"] +==== binvi + +Synopsis:: +Single-Bit Invert (Immediate) + +Mnemonic:: +binvi _rd_, _rs1_, _shamt_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BINV'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x34, attr: ['BINVI'] }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BINV'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x1a, attr: ['BINVI'] }, +]} +.... + +Description:: +This instruction returns _rs1_ with a single bit inverted at the index specified in _shamt_. +The index is read from the lower log2(XLEN) bits of _shamt_. +For RV32, the encodings corresponding to shamt[5]=1 are reserved. + +Operation:: +[source,sail] +-- +let index = shamt & (XLEN - 1); +X(rd) = X(rs1) ^ (1 << index) +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-bset,reftext="Single-Bit Set (Register)"] +==== bset + +Synopsis:: +Single-Bit Set (Register) + +Mnemonic:: +bset _rd_, _rs1_,_rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BSET'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x14, attr: ['BSET'] }, +]} +.... + +Description:: +This instruction returns _rs1_ with a single bit set at the index specified in _rs2_. +The index is read from the lower log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let index = X(rs2) & (XLEN - 1); +X(rd) = X(rs1) | (1 << index) +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-bseti,reftext="Single-Bit Set (Immediate)"] +==== bseti + +Synopsis:: +Single-Bit Set (Immediate) + +Mnemonic:: +bseti _rd_, _rs1_,_shamt_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BSETI'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x14, attr: ['BSETI'] }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['BSETI'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x0a, attr: ['BSETI'] }, +]} +.... + +Description:: +This instruction returns _rs1_ with a single bit set at the index specified in _shamt_. +The index is read from the lower log2(XLEN) bits of _shamt_. +For RV32, the encodings corresponding to shamt[5]=1 are reserved. + +Operation:: +[source,sail] +-- +let index = shamt & (XLEN - 1); +X(rd) = X(rs1) | (1 << index) +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbs (<<#zbs>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-clmul,reftext="Carry-less multiply (low-part)"] +==== clmul + +Synopsis:: +Carry-less multiply (low-part) + +Mnemonic:: +clmul _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CLMUL'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +clmul produces the lower half of the 2·XLEN carry-less product. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); +let output : xlenbits = 0; + +foreach (i from 0 to (xlen - 1) by 1) { + output = if ((rs2_val >> i) & 1) + then output ^ (rs1_val << i); + else output; +} + +X[rd] = output +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbc (<<#zbc>>) +|0.93 +|Frozen + +|Zbkc (<<#zbkc>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-clmulh,reftext="Carry-less multiply (high-part)"] +==== clmulh + +Synopsis:: +Carry-less multiply (high-part) + +Mnemonic:: +clmulh _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x3, attr: ['CLMULH'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +clmulh produces the upper half of the 2·XLEN carry-less product. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); +let output : xlenbits = 0; + +foreach (i from 1 to xlen by 1) { + output = if ((rs2_val >> i) & 1) + then output ^ (rs1_val >> (xlen - i)); + else output; +} + +X[rd] = output +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbc (<<#zbc>>) +|0.93 +|Frozen + +|Zbkc (<<#zbkc>>) +|v0.9.4 +|Frozen +|=== + + +<<< +[#insns-clmulr,reftext="Carry-less multiply (reversed)"] +==== clmulr + +Synopsis:: +Carry-less multiply (reversed) + +Mnemonic:: +clmulr _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x2, attr: ['CLMULR'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +*clmulr* produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less +product. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); +let output : xlenbits = 0; + +foreach (i from 0 to (xlen - 1) by 1) { + output = if ((rs2_val >> i) & 1) + then output ^ (rs1_val >> (xlen - i - 1)); + else output; +} + +X[rd] = output +-- + +.Note +[NOTE, caption="A" ] +=============================================================== +The *clmulr* instruction is used to accelerate CRC calculations. +The *r* in the instruction's mnemonic stands for _reversed_, as the +instruction is equivalent to bit-reversing the inputs, performing +a *clmul*, then bit-reversing the output. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbc (<<#zbc>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-clz,reftext="Count leading zero bits"] +==== clz + +Synopsis:: +Count leading zero bits + +Mnemonic:: +clz _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CLZ'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0, attr: ['CLZ'] }, + { bits: 7, name: 0x30, attr: ['CLZ'] }, +]} +.... + +Description:: +This instruction counts the number of 0's before the first 1, starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0. Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0. + +Operation:: +[source,sail] +-- +val HighestSetBit : forall ('N : Int), 'N >= 0. bits('N) -> int + +function HighestSetBit x = { + foreach (i from (xlen - 1) to 0 by 1 in dec) + if [x[i]] == 0b1 then return(i) else (); + return -1; +} + +let rs = X(rs); +X[rd] = (xlen - 1) - HighestSetBit(rs); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-clzw,reftext="Count leading zero bits in word"] +==== clzw + +Synopsis:: +Count leading zero bits in word + +Mnemonic:: +clzw _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CLZW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0, attr: ['CLZW'] }, + { bits: 7, name: 0x30, attr: ['CLZW'] }, +]} +.... + +Description:: +This instruction counts the number of 0's before the first 1 starting at bit 31 and progressing to bit 0. +Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant bit of the word (i.e., bit 31) is a 1, the output is 0. + +Operation:: +[source,sail] +-- +val HighestSetBit32 : forall ('N : Int), 'N >= 0. bits('N) -> int + +function HighestSetBit32 x = { + foreach (i from 31 to 0 by 1 in dec) + if [x[i]] == 0b1 then return(i) else (); + return -1; +} + +let rs = X(rs); +X[rd] = 31 - HighestSetBit(rs); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-cpop,reftext="Count set bits"] +==== cpop + +Synopsis:: +Count set bits + +Mnemonic:: +cpop _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CPOP'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x2, attr: ['CPOP'] }, + { bits: 7, name: 0x30, attr: ['CPOP'] }, +]} +.... +Description:: +This instructions counts the number of 1's (i.e., set bits) in the source register. + +Operation:: +[source,sail] +-- +let bitcount = 0; +let rs = X(rs); + +foreach (i from 0 to (xlen - 1) in inc) + if rs[i] == 0b1 then bitcount = bitcount + 1 else (); + +X[rd] = bitcount +-- + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +This operations is known as population count, popcount, sideways sum, bit summation, or Hamming weight. + +The GCC builtin function `+__builtin_popcount (unsigned int x)+` is implemented by cpop on RV32 and by *cpopw* on RV64. +The GCC builtin function `+__builtin_popcountl (unsigned long x)+` for LP64 is implemented by *cpop* on RV64. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-cpopw,reftext="Count set bits in word"] +==== cpopw + +Synopsis:: +Count set bits in word + +Mnemonic:: +cpopw _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CPOPW'] }, + { bits: 5, name: 'rs' }, + { bits: 5, name: 0x2, attr: ['CPOPW'] }, + { bits: 7, name: 0x30, attr: ['CPOPW'] }, +]} +.... +Description:: +This instructions counts the number of 1's (i.e., set bits) in the least-significant word of the source register. + +Operation:: +[source,sail] +-- +let bitcount = 0; +let val = X(rs); + +foreach (i from 0 to 31 in inc) + if val[i] == 0b1 then bitcount = bitcount + 1 else (); + +X[rd] = bitcount +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-ctz,reftext="Count trailing zero bits"] +==== ctz + +Synopsis:: +Count trailing zeros + +Mnemonic:: +ctz _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CTZ/CTZW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x1, attr: ['CTZ/CTZW'] }, + { bits: 7, name: 0x30, attr: ['CTZ/CTZW'] }, +]} +.... + +Description:: +This instruction counts the number of 0's before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1). +Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0. + +Operation:: +[source,sail] +-- +val LowestSetBit : forall ('N : Int), 'N >= 0. bits('N) -> int + +function LowestSetBit x = { + foreach (i from 0 to (xlen - 1) by 1 in dec) + if [x[i]] == 0b1 then return(i) else (); + return xlen; +} + +let rs = X(rs); +X[rd] = LowestSetBit(rs); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-ctzw,reftext="Count trailing zero bits in word"] +==== ctzw + +Synopsis:: +Count trailing zero bits in word + +Mnemonic:: +ctzw _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CTZ/CTZW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x1, attr: ['CTZ/CTZW'] }, + { bits: 7, name: 0x30, attr: ['CTZ/CTZW'] }, +]} +.... + +Description:: +This instruction counts the number of 0's before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit of the least-significant word (i.e., 31). Accordingly, if the least-significant word is 0, the output is 32, and if the least-significant bit of the input is a 1, the output is 0. + +Operation:: +[source,sail] +-- +val LowestSetBit32 : forall ('N : Int), 'N >= 0. bits('N) -> int + +function LowestSetBit32 x = { + foreach (i from 0 to 31 by 1 in dec) + if [x[i]] == 0b1 then return(i) else (); + return 32; +} + +let rs = X(rs); +X[rd] = LowestSetBit32(rs); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-max,reftext="Maximum"] +==== max + +Synopsis:: +Maximum + +Mnemonic:: +max _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['MAX']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +This instruction returns the larger of two signed integers. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); + +let result = if rs1_val <_s rs2_val + then rs2_val + else rs1_val; + +X(rd) = result; +-- + +.Software Hint +[NOTE, caption="SW"] +=============================================================== +Calculating the absolute value of a signed integer can be performed +using the following sequence: *neg rD,rS* followed by *max +rD,rS,rD*. When using this common sequence, it is suggested that they +are scheduled with no intervening instructions so that +implementations that are so optimized can fuse them together. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-maxu,reftext="Unsigned maximum"] +==== maxu + +Synopsis:: +Unsigned maximum + +Mnemonic:: +maxu _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['MAXU']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +This instruction returns the larger of two unsigned integers. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); + +let result = if rs1_val <_u rs2_val + then rs2_val + else rs1_val; + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-min,reftext="Minimum"] +==== min + +Synopsis:: +Minimum + +Mnemonic:: +min _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['MIN']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +This instruction returns the smaller of two signed integers. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); + +let result = if rs1_val <_s rs2_val + then rs1_val + else rs2_val; + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-minu,reftext="Unsigned minimum"] +==== minu + +Synopsis:: +Unsigned minimum + +Mnemonic:: +minu _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['MINU']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +This instruction returns the smaller of two unsigned integers. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); + +let result = if rs1_val <_u rs2_val + then rs1_val + else rs2_val; + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-orc_b,reftext="Bitwise OR-Combine, byte granule"] +==== orc.b + +Synopsis:: +Bitwise OR-Combine, byte granule + +Mnemonic:: +orc.b _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x287 } +]} +.... + +Description:: +Combines the bits within each byte using bitwise logical OR. +This sets the bits of each byte in the result _rd_ to all zeros if no bit within the respective byte of _rs_ is set, or to all ones if any bit within the respective byte of _rs_ is set. + +Operation:: +[source,sail] +-- +let input = X(rs); +let output : xlenbits = 0; + +foreach (i from 0 to (xlen - 8) by 8) { + output[(i + 7)..i] = if input[(i + 7)..i] == 0 + then 0b00000000 + else 0b11111111; +} + +X[rd] = output; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-orn,reftext="OR with inverted operand"] +==== orn + +Synopsis:: +OR with inverted operand + +Mnemonic:: +orn _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['ORN']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x20, attr: ['ORN'] }, +]} +.... + +Description:: +This instruction performs the bitwise logical OR operation between _rs1_ and the bitwise inversion of _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs1) | ~X(rs2); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-pack,reftext="Pack low halves of registers"] +==== pack + +Synopsis:: +Pack the low halves of _rs1_ and _rs2_ into _rd_. + +Mnemonic:: +pack _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + {bits: 7, name: 0x33, attr: ['OP'] }, + {bits: 5, name: 'rd'}, + {bits: 3, name: 0x4, attr:['PACK']}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 0x4, attr:['PACK']}, +]} +.... + +Description:: +The pack instruction packs the XLEN/2-bit lower halves of _rs1_ and _rs2_ into +_rd_, with _rs1_ in the lower half and _rs2_ in the upper half. + +Operation:: +[source,sail] +-- +let lo_half : bits(xlen/2) = X(rs1)[xlen/2-1..0]; +let hi_half : bits(xlen/2) = X(rs2)[xlen/2-1..0]; +X(rd) = EXTZ(hi_half @ lo_half); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-packh,reftext="Pack low bytes of registers"] +==== packh + +Synopsis:: +Pack the low bytes of _rs1_ and _rs2_ into _rd_. + +Mnemonic:: +packh _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + {bits: 7, name: 0x33, attr: ['OP'] }, + {bits: 5, name: 'rd'}, + {bits: 3, name: 0x7, attr: ['PACKH']}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 0x4, attr: ['PACKH']}, +]} +.... + +Description:: +And the packh instruction packs the least-significant bytes of +_rs1_ and _rs2_ into the 16 least-significant bits of _rd_, +zero extending the rest of _rd_. + +Operation:: +[source,sail] +-- +let lo_half : bits(8) = X(rs1)[7..0]; +let hi_half : bits(8) = X(rs2)[7..0]; +X(rd) = EXTZ(hi_half @ lo_half); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-packw,reftext="Pack low 16-bits of registers (RV64)"] +==== packw + +Synopsis:: +Pack the low 16-bits of _rs1_ and _rs2_ into _rd_ on RV64. + +Mnemonic:: +packw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 2, name: 0x3}, +{bits: 5, name: 0xe}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x4}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 7, name: 0x4}, +]} +.... + +Description:: +This instruction packs the low 16 bits of +_rs1_ and _rs2_ into the 32 least-significant bits of _rd_, +sign extending the 32-bit result to the rest of _rd_. +This instruction only exists on RV64 based systems. + +Operation:: +[source,sail] +-- +let lo_half : bits(16) = X(rs1)[15..0]; +let hi_half : bits(16) = X(rs2)[15..0]; +X(rd) = EXTS(hi_half @ lo_half); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-rev8,reftext="Byte-reverse register"] +==== rev8 + +Synopsis:: +Byte-reverse register + +Mnemonic:: +rev8 _rd_, _rs_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x698 } +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x6b8 } +]} +.... + +Description:: +This instruction reverses the order of the bytes in _rs_. + +Operation:: +[source,sail] +-- +let input = X(rs); +let output : xlenbits = 0; +let j = xlen - 1; + +foreach (i from 0 to (xlen - 8) by 8) { + output[i..(i + 7)] = input[(j - 7)..j]; + j = j - 8; +} + +X[rd] = output +-- + +.Note +[NOTE, caption="A" ] +=============================================================== +The *rev8* mnemonic corresponds to different instruction encodings in RV32 and RV64. +=============================================================== + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +The byte-reverse operation is only available for the full register +width. To emulate word-sized and halfword-sized byte-reversal, +perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K is +XLEN-32 and XLEN-16, respectively. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-revb,reftext="Reverse bits in bytes"] +==== rev.b + +Synopsis:: +Reverse the bits in each byte of a source register. + +Mnemonic:: +rev.b _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x687 } +]} +.... + +Description:: +This instruction reverses the order of the bits in every byte of a register. + +Operation:: +[source,sail] +-- +result : xlenbits = EXTZ(0b0); +foreach (i from 0 to sizeof(xlen) by 8) { + result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]); +}; +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-rol,reftext="Rotate left (Register)"] +==== rol + +Synopsis:: +Rotate Left (Register) + +Mnemonic:: +rol _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['ROL']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['ROL'] }, +]} +.... + +Description:: +This instruction performs a rotate left of _rs1_ by the amount in least-significant log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let shamt = if xlen == 32 + then X(rs2)[4..0] + else X(rs2)[5..0]; +let result = (X(rs1) << shamt) | (X(rs1) >> (xlen - shamt)); + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-rolw,reftext="Rotate Left Word (Register)"] +==== rolw + +Synopsis:: +Rotate Left Word (Register) + +Mnemonic:: +rolw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['ROLW']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['ROLW'] }, +]} +.... + +Description:: +This instruction performs a rotate left on the least-significant word of _rs1_ by the amount in least-significant 5 bits of _rs2_. +The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits. + +Operation:: +[source,sail] +-- +let rs1 = EXTZ(X(rs1)[31..0]) +let shamt = X(rs2)[4..0]; +let result = (rs1 << shamt) | (rs1 >> (32 - shamt)); +X(rd) = EXTS(result[31..0]); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-ror,reftext="Rotate right (Register)"] +==== ror + +Synopsis:: +Rotate Right + +Mnemonic:: +ror _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['ROR']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['ROR'] }, +]} +.... + +Description:: +This instruction performs a rotate right of _rs1_ by the amount in least-significant log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let shamt = if xlen == 32 + then X(rs2)[4..0] + else X(rs2)[5..0]; +let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt)); + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-rori,reftext="Rotate right (Immediate)"] +==== rori + +Synopsis:: +Rotate Right (Immediate) + +Mnemonic:: +rori _rd_, _rs1_, _shamt_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORI']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x30, attr: ['RORI'] }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORI']}, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x18, attr: ['RORI'] }, +]} +.... + +Description:: +This instruction performs a rotate right of _rs1_ by the amount in the least-significant log2(XLEN) bits of _shamt_. +For RV32, the encodings corresponding to shamt[5]=1 are reserved. + +Operation:: +[source,sail] +-- +let shamt = if xlen == 32 + then shamt[4..0] + else shamt[5..0]; +let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt)); + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-roriw,reftext="Rotate right Word (Immediate)"] +==== roriw + +Synopsis:: +Rotate Right Word by Immediate + +Mnemonic:: +roriw _rd_, _rs1_, _shamt_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORIW']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x30, attr: ['RORIW'] }, +]} +.... + +Description:: +This instruction performs a rotate right on the least-significant word +of _rs1_ by the amount in the least-significant log2(XLEN) bits of +_shamt_. +The resulting word value is sign-extended by copying bit 31 to all of +the more-significant bits. + + +Operation:: +[source,sail] +-- +let rs1_data = EXTZ(X(rs1)[31..0]; +let result = (rs1_data >> shamt) | (rs1_data << (32 - shamt)); +X(rd) = EXTS(result[31..0]); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-rorw,reftext="Rotate right Word (Register)"] +==== rorw + +Synopsis:: +Rotate Right Word (Register) + +Mnemonic:: +rorw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORW']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['RORW'] }, +]} +.... + +Description:: +This instruction performs a rotate right on the least-significant word of _rs1_ by the amount in least-significant 5 bits of _rs2_. +The resultant word is sign-extended by copying bit 31 to all of the more-significant bits. + +Operation:: +[source,sail] +-- +let rs1 = EXTZ(X(rs1)[31..0]) +let shamt = X(rs2)[4..0]; +let result = (rs1 >> shamt) | (rs1 << (32 - shamt)); +X(rd) = EXTS(result); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-sext_b,reftext="Sign-extend byte"] +==== sext.b + +Synopsis:: +Sign-extend byte + +Mnemonic:: +sext.b _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['SEXT.B/SEXT.H'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x04, attr: ['SEXT.B'] }, + { bits: 7, name: 0x30 }, +]} +.... + +Description:: +This instruction sign-extends the least-significant byte in the source to XLEN by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. + +Operation:: +[source,sail] +-- +X(rd) = EXTS(X(rs)[7..0]); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-sext_h,reftext="Sign-extend halfword"] +==== sext.h + +Synopsis:: +Sign-extend halfword + +Mnemonic:: +sext.h _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['SEXT.B/SEXT.H'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x05, attr: ['SEXT.H'] }, + { bits: 7, name: 0x30 }, +]} +.... + +Description:: +This instruction sign-extends the least-significant halfword in _rs_ to XLEN by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. + +Operation:: +[source,sail] +-- +X(rd) = EXTS(X(rs)[15..0]); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + + +<<< +[#insns-sh1add,reftext=Shift left by 1 and add] +==== sh1add + +Synopsis:: +Shift left by 1 and add + +Mnemonic:: +sh1add _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x2, attr: ['SH1ADD'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x10, attr: ['SH1ADD'] }, +]} +.... + +Description:: +This instruction shifts _rs1_ to the left by 1 bit and adds it to _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs2) + (X(rs1) << 1); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +// We have decided that this and all other instructions will not have reserved encodings for "useless encodings" +// We could follow suit of the base ISA and create HINTs if there is some recognized value for doing so + +<<< +[#insns-sh1add_uw,reftext=Shift unsigned word left by 1 and add] +==== sh1add.uw + +Synopsis:: +Shift unsigned word left by 1 and add + +Mnemonic:: +sh1add.uw _rd_, _rs1_, _rs2_ +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x2, attr: ['SH1ADD.UW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x10, attr: ['SH1ADD.UW'] }, +]} +.... + +Description:: +This instruction performs an XLEN-wide addition of two addends. +The first addend is _rs2_. The second addend is the unsigned value formed by extracting the least-significant word of _rs1_ and shifting it left by 1 place. + +Operation:: +[source,sail] +-- +let base = X(rs2); +let index = EXTZ(X(rs1)[31..0]); + +X(rd) = base + (index << 1); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-sh2add,reftext=Shift left by 2 and add] +==== sh2add + +Synopsis:: +Shift left by 2 and add + +Mnemonic:: +sh2add _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['SH2ADD'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x10, attr: ['SH2ADD'] }, +]} +.... + +Description:: +This instruction shifts _rs1_ to the left by 2 places and adds it to _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs2) + (X(rs1) << 2); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-sh2add_uw,reftext=Shift unsigned word left by 2 and add] +==== sh2add.uw + +Synopsis:: +Shift unsigned word left by 2 and add + +Mnemonic:: +sh2add.uw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['SH2ADD.UW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x10, attr: ['SH2ADD.UW'] }, +]} +.... + +Description:: +This instruction performs an XLEN-wide addition of two addends. +The first addend is _rs2_. +The second addend is the unsigned value formed by extracting the least-significant word of _rs1_ and shifting it left by 2 places. + +Operation:: +[source,sail] +-- +let base = X(rs2); +let index = EXTZ(X(rs1)[31..0]); + +X(rd) = base + (index << 2); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-sh3add,reftext=Shift left by 3 and add] +==== sh3add + +Synopsis:: +Shift left by 3 and add + +Mnemonic:: +sh3add _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['SH3ADD'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x10, attr: ['SH3ADD'] }, +]} +.... + +Description:: +This instruction shifts _rs1_ to the left by 3 places and adds it to _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs2) + (X(rs1) << 3); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-sh3add_uw,reftext=Shift unsigned word left by 3 and add] +==== sh3add.uw + +Synopsis:: +Shift unsigned word left by 3 and add + +Mnemonic:: +sh3add.uw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['SH3ADD.UW'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x10, attr: ['SH3ADD.UW'] }, +]} +.... + +Description:: +This instruction performs an XLEN-wide addition of two addends. The first addend is _rs2_. The second addend is the unsigned value formed by extracting the least-significant word of _rs1_ and shifting it left by 3 places. + +Operation:: +[source,sail] +-- +let base = X(rs2); +let index = EXTZ(X(rs1)[31..0]); + +X(rd) = base + (index << 3); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-slli_uw,reftext="Shift-left unsigned word (Immediate)"] +==== slli.uw + +Synopsis:: +Shift-left unsigned word (Immediate) + +Mnemonic:: +slli.uw _rd_, _rs1_, _shamt_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['SLLI.UW'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x02, attr: ['SLLI.UW'] }, +]} +.... + +Description:: +This instruction takes the least-significant word of _rs1_, zero-extends it, and shifts it left by the immediate. + +Operation:: +[source,sail] +-- +X(rd) = (EXTZ(X(rs)[31..0]) << shamt); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zba (<<#zba>>) +|0.93 +|Frozen +|=== + +.Architecture Explanation +[NOTE, caption="A" ] +=============================================================== +This instruction is the same as *slli* with *zext.w* performed on _rs1_ before shifting. +=============================================================== + +<<< +[#insns-unzip,reftext="Bit deinterleave"] +==== unzip + +Synopsis:: +Implements the inverse of the zip instruction. + +Mnemonic:: +unzip _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13, attr: ['OP-IMM']}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x5}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x1f}, +{bits: 7, name: 0x4}, +]} +.... + +Description:: +This instruction gathers bits from the high and low halves of the source +word into odd/even bit positions in the destination word. +It is the inverse of the <<insns-zip,zip>> instruction. +This instruction is available only on RV32. + +Operation:: +[source,sail] +-- +foreach (i from 0 to xlen/2-1) { + X(rd)[i] = X(rs1)[2*i] + X(rd)[i+xlen/2] = X(rs1)[2*i+1] +} +-- + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +This instruction is useful for implementing the SHA3 cryptographic +hash function on a 32-bit architecture, as it implements the +bit-interleaving operation used to speed up the 64-bit rotations +directly. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) (RV32) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-xnor,reftext="Exclusive NOR"] +==== xnor + +Synopsis:: +Exclusive NOR + +Mnemonic:: +xnor _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['XNOR']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x20, attr: ['XNOR'] }, +]} +.... + +Description:: +This instruction performs the bit-wise exclusive-NOR operation on _rs1_ and _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = ~(X(rs1) ^ X(rs2)); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen + +|Zbkb (<<#zbkb>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-xpermb,reftext="Crossbar permutation (bytes)"] +==== xperm.b + +Synopsis:: +Byte-wise lookup of indices into a vector in registers. + +Mnemonic:: +xperm.b _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 2, name: 0x3}, +{bits: 5, name: 0xc}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x4}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 7, name: 0x14}, +]} +.... + +Description:: +The xperm.b instruction operates on bytes. +The _rs1_ register contains a vector of XLEN/8 8-bit elements. +The _rs2_ register contains a vector of XLEN/8 8-bit indexes. +The result is each element in _rs2_ replaced by the indexed element in _rs1_, +or zero if the index into _rs2_ is out of bounds. + +Operation:: +[source,sail] +-- +val xpermb_lookup : (bits(8), xlenbits) -> bits(8) +function xpermb_lookup (idx, lut) = { + (lut >> (idx @ 0b000))[7..0] +} + +function clause execute ( XPERM_B (rs2,rs1,rd)) = { + result : xlenbits = EXTZ(0b0); + foreach(i from 0 to xlen by 8) { + result[i+7..i] = xpermn_lookup(X(rs2)[i+7..i], X(rs1)); + }; + X(rd) = result; + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkx (<<#zbkx>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-xpermn,reftext="Crossbar permutation (nibbles)"] +==== xperm.n + +Synopsis:: +Nibble-wise lookup of indices into a vector. + +Mnemonic:: +xperm.n _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 2, name: 0x3}, +{bits: 5, name: 0xc}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x2}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 7, name: 0x14}, +]} +.... + +Description:: +The xperm.n instruction operates on nibbles. +The _rs1_ register contains a vector of XLEN/4 4-bit elements. +The _rs2_ register contains a vector of XLEN/4 4-bit indexes. +The result is each element in _rs2_ replaced by the indexed element in _rs1_, +or zero if the index into _rs2_ is out of bounds. + +Operation:: +[source,sail] +-- +val xpermn_lookup : (bits(4), xlenbits) -> bits(4) +function xpermn_lookup (idx, lut) = { + (lut >> (idx @ 0b00))[3..0] +} + +function clause execute ( XPERM_N (rs2,rs1,rd)) = { + result : xlenbits = EXTZ(0b0); + foreach(i from 0 to xlen by 4) { + result[i+3..i] = xpermn_lookup(X(rs2)[i+3..i], X(rs1)); + }; + X(rd) = result; + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkx (<<#zbkx>>) +|v0.9.4 +|Frozen +|=== + +<<< +[#insns-zext_h,reftext="Zero-extend halfword"] +==== zext.h + +Synopsis:: +Zero-extend halfword + +Mnemonic:: +zext.h _rd_, _rs_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['ZEXT.H']}, + { bits: 5, name: 'rs' }, + { bits: 5, name: 0x00 }, + { bits: 7, name: 0x04 }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['ZEXT.H']}, + { bits: 5, name: 'rs' }, + { bits: 5, name: 0x00 }, + { bits: 7, name: 0x04 }, +]} +.... + +Description:: +This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0's into all of the bits more significant than 15. + +Operation:: +[source,sail] +-- +X(rd) = EXTZ(X(rs)[15..0]); +-- + +.Note +[NOTE, caption="A" ] +=============================================================== +The *zext.h* mnemonic corresponds to different instruction encodings in RV32 and RV64. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|0.93 +|Frozen +|=== + +<<< +[#insns-zip,reftext="Bit interleave"] +==== zip + +Synopsis:: +Gather odd and even bits of the source word into upper/lower halves of the +destination. + +Mnemonic:: +zip _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13, attr: ['OP-IMM']}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x1e}, +{bits: 7, name: 0x4}, +]} +.... + +Description:: +This instruction scatters all of the odd and even bits of a source word into +the high and low halves of a destination word. +It is the inverse of the <<insns-unzip,unzip>> instruction. +This instruction is available only on RV32. + +Operation:: +[source,sail] +-- +foreach (i from 0 to xlen/2-1) { + X(rd)[2*i] = X(rs1)[i] + X(rd)[2*i+1] = X(rs1)[i+xlen/2] +} +-- + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +This instruction is useful for implementing the SHA3 cryptographic +hash function on a 32-bit architecture, as it implements the +bit-interleaving operation used to speed up the 64-bit rotations +directly. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) (RV32) +|v0.9.4 +|Frozen +|=== + + +=== Software optimization guide + +==== strlen + +The *orc.b* instruction allows for the efficient detection of *NUL* bytes in an XLEN-sized chunk of data: + + * the result of *orc.b* on a chunk that does not contain any *NUL* bytes will be all-ones, and + * after a bitwise-negation of the result of *orc.b*, the number of data bytes before the first *NUL* byte (if any) can be detected by *ctz*/*clz* (depending on the endianness of data). + +A full example of a *strlen* function, which uses these techniques and also demonstrates the use of it for unaligned/partial data, is the following: + +[source,asm] +-- +#include <sys/asm.h> + + .text + .globl strlen + .type strlen, @function +strlen: + andi a3, a0, (SZREG-1) // offset + andi a1, a0, -SZREG // align pointer +.Lprologue: + li a4, SZREG + sub a4, a4, a3 // XLEN - offset + slli a3, a3, 3 // offset * 8 + REG_L a2, 0(a1) // chunk + /* + * Shift the partial/unaligned chunk we loaded to remove the bytes + * from before the start of the string, adding NUL bytes at the end. + */ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + srl a2, a2 ,a3 // chunk >> (offset * 8) +#else + sll a2, a2, a3 +#endif + orc.b a2, a2 + not a2, a2 + /* + * Non-NUL bytes in the string have been expanded to 0x00, while + * NUL bytes have become 0xff. Search for the first set bit + * (corresponding to a NUL byte in the original chunk). + */ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + ctz a2, a2 +#else + clz a2, a2 +#endif + /* + * The first chunk is special: compare against the number of valid + * bytes in this chunk. + */ + srli a0, a2, 3 + bgtu a4, a0, .Ldone + addi a3, a1, SZREG + li a4, -1 + .align 2 + /* + * Our critical loop is 4 instructions and processes data in 4 byte + * or 8 byte chunks. + */ +.Lloop: + REG_L a2, SZREG(a1) + addi a1, a1, SZREG + orc.b a2, a2 + beq a2, a4, .Lloop + +.Lepilogue: + not a2, a2 +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + ctz a2, a2 +#else + clz a2, a2 +#endif + sub a1, a1, a3 + add a0, a0, a1 + srli a2, a2, 3 + add a0, a0, a2 +.Ldone: + ret +-- + +==== strcmp + +[source,asm] +-- +#include <sys/asm.h> + + .text + .globl strcmp + .type strcmp, @function +strcmp: + or a4, a0, a1 + li t2, -1 + and a4, a4, SZREG-1 + bnez a4, .Lsimpleloop + + # Main loop for aligned strings +.Lloop: + REG_L a2, 0(a0) + REG_L a3, 0(a1) + orc.b t0, a2 + bne t0, t2, .Lfoundnull + addi a0, a0, SZREG + addi a1, a1, SZREG + beq a2, a3, .Lloop + + # Words don't match, and no null byte in first word. + # Get bytes in big-endian order and compare. +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + rev8 a2, a2 + rev8 a3, a3 +#endif + # Synthesize (a2 >= a3) ? 1 : -1 in a branchless sequence. + sltu a0, a2, a3 + neg a0, a0 + ori a0, a0, 1 + ret + +.Lfoundnull: + # Found a null byte. + # If words don't match, fall back to simple loop. + bne a2, a3, .Lsimpleloop + + # Otherwise, strings are equal. + li a0, 0 + ret + + # Simple loop for misaligned strings +.Lsimpleloop: + lbu a2, 0(a0) + lbu a3, 0(a1) + addi a0, a0, 1 + addi a1, a1, 1 + bne a2, a3, 1f + bnez a2, .Lsimpleloop + +1: + sub a0, a2, a3 + ret + +.size strcmp, .-strcmp +--
\ No newline at end of file diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index ca248f6..4cc36cd 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -306,8 +306,7 @@ These instructions use the CI format. C.LWSP loads a 32-bit value from memory into register _rd_. It computes an effective address by adding the _zero_-extended offset, scaled by 4, to the stack pointer, `x2`. It expands to `lw rd, offset(x2)`. C.LWSP is -only valid when _rd_≠x0 the code -points with _rd_=x0 are reserved. +only valid when _rd_≠x0 the code points with _rd_=x0 are reserved. C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register _rd_. It computes its effective address by diff --git a/src/calling-convention.adoc b/src/calling-convention.adoc new file mode 100644 index 0000000..f5cb079 --- /dev/null +++ b/src/calling-convention.adoc @@ -0,0 +1,29 @@ +[appendix] +== Calling Convention for Vector State (Not authoritative - Placeholder Only) + +NOTE: This Appendix is only a placeholder to help explain the +conventions used in the code examples, and is not considered frozen or +part of the ratification process. The official RISC-V psABI document +is being expanded to specify the vector calling conventions. + +In the RISC-V psABI, the vector registers `v0`-`v31` are all caller-saved. +The `vl` and `vtype` CSRs are also caller-saved. + +Procedures may assume that `vstart` is zero upon entry. Procedures may +assume that `vstart` is zero upon return from a procedure call. + +NOTE: Application software should normally not write `vstart` explicitly. +Any procedure that does explicitly write `vstart` to a nonzero value must +zero `vstart` before either returning or calling another procedure. + +The `vxrm` and `vxsat` fields of `vcsr` have thread storage duration. + +Executing a system call causes all caller-saved vector registers +(`v0`-`v31`, `vl`, `vtype`) and `vstart` to become unspecified. + +NOTE: This scheme allows system calls that cause context switches to avoid +saving and later restoring the vector registers. + +NOTE: Most OSes will choose to either leave these registers intact or reset +them to their initial state to avoid leaking information across process +boundaries. diff --git a/src/example/memcpy.s b/src/example/memcpy.s new file mode 100644 index 0000000..5f6318a --- /dev/null +++ b/src/example/memcpy.s @@ -0,0 +1,17 @@ + .text + .balign 4 + .global memcpy + # void *memcpy(void* dest, const void* src, size_t n) + # a0=dest, a1=src, a2=n + # + memcpy: + mv a3, a0 # Copy destination + loop: + vsetvli t0, a2, e8, m8, ta, ma # Vectors of 8b + vle8.v v0, (a1) # Load bytes + add a1, a1, t0 # Bump pointer + sub a2, a2, t0 # Decrement count + vse8.v v0, (a3) # Store bytes + add a3, a3, t0 # Bump pointer + bnez a2, loop # Any more? + ret # Return diff --git a/src/example/saxpy.s b/src/example/saxpy.s new file mode 100644 index 0000000..de7f224 --- /dev/null +++ b/src/example/saxpy.s @@ -0,0 +1,29 @@ + .text + .balign 4 + .global saxpy +# void +# saxpy(size_t n, const float a, const float *x, float *y) +# { +# size_t i; +# for (i=0; i<n; i++) +# y[i] = a * x[i] + y[i]; +# } +# +# register arguments: +# a0 n +# fa0 a +# a1 x +# a2 y + +saxpy: + vsetvli a4, a0, e32, m8, ta, ma + vle32.v v0, (a1) + sub a0, a0, a4 + slli a4, a4, 2 + add a1, a1, a4 + vle32.v v8, (a2) + vfmacc.vf v8, fa0, v0 + vse32.v v8, (a2) + add a2, a2, a4 + bnez a0, saxpy + ret diff --git a/src/example/sgemm.S b/src/example/sgemm.S new file mode 100644 index 0000000..e29cc8d --- /dev/null +++ b/src/example/sgemm.S @@ -0,0 +1,221 @@ + .text + .balign 4 + .global sgemm_nn +# RV64IDV system +# +# void +# sgemm_nn(size_t n, +# size_t m, +# size_t k, +# const float*a, // m * k matrix +# size_t lda, +# const float*b, // k * n matrix +# size_t ldb, +# float*c, // m * n matrix +# size_t ldc) +# +# c += a*b (alpha=1, no transpose on input matrices) +# matrices stored in C row-major order + +#define n a0 +#define m a1 +#define k a2 +#define ap a3 +#define astride a4 +#define bp a5 +#define bstride a6 +#define cp a7 +#define cstride t0 +#define kt t1 +#define nt t2 +#define bnp t3 +#define cnp t4 +#define akp t5 +#define bkp s0 +#define nvl s1 +#define ccp s2 +#define amp s3 + +# Use args as additional temporaries +#define ft12 fa0 +#define ft13 fa1 +#define ft14 fa2 +#define ft15 fa3 + +# This version holds a 16*VLMAX block of C matrix in vector registers +# in inner loop, but otherwise does not cache or TLB tiling. + +sgemm_nn: + addi sp, sp, -FRAMESIZE + sd s0, OFFSET(sp) + sd s1, OFFSET(sp) + sd s2, OFFSET(sp) + + # Check for zero size matrices + beqz n, exit + beqz m, exit + beqz k, exit + + # Convert elements strides to byte strides. + ld cstride, OFFSET(sp) # Get arg from stack frame + slli astride, astride, 2 + slli bstride, bstride, 2 + slli cstride, cstride, 2 + + slti t6, m, 16 + bnez t6, end_rows + +c_row_loop: # Loop across rows of C blocks + + mv nt, n # Initialize n counter for next row of C blocks + + mv bnp, bp # Initialize B n-loop pointer to start + mv cnp, cp # Initialize C n-loop pointer + +c_col_loop: # Loop across one row of C blocks + vsetvli nvl, nt, e32, ta, ma # 32-bit vectors, LMUL=1 + + mv akp, ap # reset pointer into A to beginning + mv bkp, bnp # step to next column in B matrix + + # Initalize current C submatrix block from memory. + vle32.v v0, (cnp); add ccp, cnp, cstride; + vle32.v v1, (ccp); add ccp, ccp, cstride; + vle32.v v2, (ccp); add ccp, ccp, cstride; + vle32.v v3, (ccp); add ccp, ccp, cstride; + vle32.v v4, (ccp); add ccp, ccp, cstride; + vle32.v v5, (ccp); add ccp, ccp, cstride; + vle32.v v6, (ccp); add ccp, ccp, cstride; + vle32.v v7, (ccp); add ccp, ccp, cstride; + vle32.v v8, (ccp); add ccp, ccp, cstride; + vle32.v v9, (ccp); add ccp, ccp, cstride; + vle32.v v10, (ccp); add ccp, ccp, cstride; + vle32.v v11, (ccp); add ccp, ccp, cstride; + vle32.v v12, (ccp); add ccp, ccp, cstride; + vle32.v v13, (ccp); add ccp, ccp, cstride; + vle32.v v14, (ccp); add ccp, ccp, cstride; + vle32.v v15, (ccp) + + + mv kt, k # Initialize inner loop counter + + # Inner loop scheduled assuming 4-clock occupancy of vfmacc instruction and single-issue pipeline + # Software pipeline loads + flw ft0, (akp); add amp, akp, astride; + flw ft1, (amp); add amp, amp, astride; + flw ft2, (amp); add amp, amp, astride; + flw ft3, (amp); add amp, amp, astride; + # Get vector from B matrix + vle32.v v16, (bkp) + + # Loop on inner dimension for current C block + k_loop: + vfmacc.vf v0, ft0, v16 + add bkp, bkp, bstride + flw ft4, (amp) + add amp, amp, astride + vfmacc.vf v1, ft1, v16 + addi kt, kt, -1 # Decrement k counter + flw ft5, (amp) + add amp, amp, astride + vfmacc.vf v2, ft2, v16 + flw ft6, (amp) + add amp, amp, astride + flw ft7, (amp) + vfmacc.vf v3, ft3, v16 + add amp, amp, astride + flw ft8, (amp) + add amp, amp, astride + vfmacc.vf v4, ft4, v16 + flw ft9, (amp) + add amp, amp, astride + vfmacc.vf v5, ft5, v16 + flw ft10, (amp) + add amp, amp, astride + vfmacc.vf v6, ft6, v16 + flw ft11, (amp) + add amp, amp, astride + vfmacc.vf v7, ft7, v16 + flw ft12, (amp) + add amp, amp, astride + vfmacc.vf v8, ft8, v16 + flw ft13, (amp) + add amp, amp, astride + vfmacc.vf v9, ft9, v16 + flw ft14, (amp) + add amp, amp, astride + vfmacc.vf v10, ft10, v16 + flw ft15, (amp) + add amp, amp, astride + addi akp, akp, 4 # Move to next column of a + vfmacc.vf v11, ft11, v16 + beqz kt, 1f # Don't load past end of matrix + flw ft0, (akp) + add amp, akp, astride +1: vfmacc.vf v12, ft12, v16 + beqz kt, 1f + flw ft1, (amp) + add amp, amp, astride +1: vfmacc.vf v13, ft13, v16 + beqz kt, 1f + flw ft2, (amp) + add amp, amp, astride +1: vfmacc.vf v14, ft14, v16 + beqz kt, 1f # Exit out of loop + flw ft3, (amp) + add amp, amp, astride + vfmacc.vf v15, ft15, v16 + vle32.v v16, (bkp) # Get next vector from B matrix, overlap loads with jump stalls + j k_loop + +1: vfmacc.vf v15, ft15, v16 + + # Save C matrix block back to memory + vse32.v v0, (cnp); add ccp, cnp, cstride; + vse32.v v1, (ccp); add ccp, ccp, cstride; + vse32.v v2, (ccp); add ccp, ccp, cstride; + vse32.v v3, (ccp); add ccp, ccp, cstride; + vse32.v v4, (ccp); add ccp, ccp, cstride; + vse32.v v5, (ccp); add ccp, ccp, cstride; + vse32.v v6, (ccp); add ccp, ccp, cstride; + vse32.v v7, (ccp); add ccp, ccp, cstride; + vse32.v v8, (ccp); add ccp, ccp, cstride; + vse32.v v9, (ccp); add ccp, ccp, cstride; + vse32.v v10, (ccp); add ccp, ccp, cstride; + vse32.v v11, (ccp); add ccp, ccp, cstride; + vse32.v v12, (ccp); add ccp, ccp, cstride; + vse32.v v13, (ccp); add ccp, ccp, cstride; + vse32.v v14, (ccp); add ccp, ccp, cstride; + vse32.v v15, (ccp) + + # Following tail instructions should be scheduled earlier in free slots during C block save. + # Leaving here for clarity. + + # Bump pointers for loop across blocks in one row + slli t6, nvl, 2 + add cnp, cnp, t6 # Move C block pointer over + add bnp, bnp, t6 # Move B block pointer over + sub nt, nt, nvl # Decrement element count in n dimension + bnez nt, c_col_loop # Any more to do? + + # Move to next set of rows + addi m, m, -16 # Did 16 rows above + slli t6, astride, 4 # Multiply astride by 16 + add ap, ap, t6 # Move A matrix pointer down 16 rows + slli t6, cstride, 4 # Multiply cstride by 16 + add cp, cp, t6 # Move C matrix pointer down 16 rows + + slti t6, m, 16 + beqz t6, c_row_loop + + # Handle end of matrix with fewer than 16 rows. + # Can use smaller versions of above decreasing in powers-of-2 depending on code-size concerns. +end_rows: + # Not done. + +exit: + ld s0, OFFSET(sp) + ld s1, OFFSET(sp) + ld s2, OFFSET(sp) + addi sp, sp, FRAMESIZE + ret diff --git a/src/example/strcmp.s b/src/example/strcmp.s new file mode 100644 index 0000000..c657703 --- /dev/null +++ b/src/example/strcmp.s @@ -0,0 +1,34 @@ + .text + .balign 4 + .global strcmp + # int strcmp(const char *src1, const char* src2) +strcmp: + ## Using LMUL=2, but same register names work for larger LMULs + li t1, 0 # Initial pointer bump +loop: + vsetvli t0, x0, e8, m2, ta, ma # Max length vectors of bytes + add a0, a0, t1 # Bump src1 pointer + vle8ff.v v8, (a0) # Get src1 bytes + add a1, a1, t1 # Bump src2 pointer + vle8ff.v v16, (a1) # Get src2 bytes + + vmseq.vi v0, v8, 0 # Flag zero bytes in src1 + vmsne.vv v1, v8, v16 # Flag if src1 != src2 + vmor.mm v0, v0, v1 # Combine exit conditions + + vfirst.m a2, v0 # ==0 or != ? + csrr t1, vl # Get number of bytes fetched + + bltz a2, loop # Loop if all same and no zero byte + + add a0, a0, a2 # Get src1 element address + lbu a3, (a0) # Get src1 byte from memory + + add a1, a1, a2 # Get src2 element address + lbu a4, (a1) # Get src2 byte from memory + + sub a0, a3, a4 # Return value. + + ret + + diff --git a/src/example/strcpy.s b/src/example/strcpy.s new file mode 100644 index 0000000..109112d --- /dev/null +++ b/src/example/strcpy.s @@ -0,0 +1,20 @@ + .text + .balign 4 + .global strcpy + # char* strcpy(char *dst, const char* src) +strcpy: + mv a2, a0 # Copy dst + li t0, -1 # Infinite AVL +loop: + vsetvli x0, t0, e8, m8, ta, ma # Max length vectors of bytes + vle8ff.v v8, (a1) # Get src bytes + csrr t1, vl # Get number of bytes fetched + vmseq.vi v1, v8, 0 # Flag zero bytes + vfirst.m a3, v1 # Zero found? + add a1, a1, t1 # Bump pointer + vmsif.m v0, v1 # Set mask up to and including zero byte. + vse8.v v8, (a2), v0.t # Write out bytes + add a2, a2, t1 # Bump pointer + bltz a3, loop # Zero byte not found, so loop + + ret diff --git a/src/example/strlen.s b/src/example/strlen.s new file mode 100644 index 0000000..1c3af4b --- /dev/null +++ b/src/example/strlen.s @@ -0,0 +1,22 @@ + .text + .balign 4 + .global strlen +# size_t strlen(const char *str) +# a0 holds *str + +strlen: + mv a3, a0 # Save start +loop: + vsetvli a1, x0, e8, m8, ta, ma # Vector of bytes of maximum length + vle8ff.v v8, (a3) # Load bytes + csrr a1, vl # Get bytes read + vmseq.vi v0, v8, 0 # Set v0[i] where v8[i] = 0 + vfirst.m a2, v0 # Find first set bit + add a3, a3, a1 # Bump pointer + bltz a2, loop # Not found? + + add a0, a0, a1 # Sum start + bump + add a3, a3, a2 # Add index + sub a0, a3, a0 # Subtract start address+bump + + ret diff --git a/src/example/strncpy.s b/src/example/strncpy.s new file mode 100644 index 0000000..87e5410 --- /dev/null +++ b/src/example/strncpy.s @@ -0,0 +1,36 @@ + .text + .balign 4 + .global strncpy + # char* strncpy(char *dst, const char* src, size_t n) +strncpy: + mv a3, a0 # Copy dst +loop: + vsetvli x0, a2, e8, m8, ta, ma # Vectors of bytes. + vle8ff.v v8, (a1) # Get src bytes + vmseq.vi v1, v8, 0 # Flag zero bytes + csrr t1, vl # Get number of bytes fetched + vfirst.m a4, v1 # Zero found? + vmsbf.m v0, v1 # Set mask up to before zero byte. + vse8.v v8, (a3), v0.t # Write out non-zero bytes + bgez a4, zero_tail # Zero remaining bytes. + sub a2, a2, t1 # Decrement count. + add a3, a3, t1 # Bump dest pointer + add a1, a1, t1 # Bump src pointer + bnez a2, loop # Anymore? + + ret + +zero_tail: + sub a2, a2, a4 # Subtract count on non-zero bytes. + add a3, a3, a4 # Advance past non-zero bytes. + vsetvli t1, a2, e8, m8, ta, ma # Vectors of bytes. + vmv.v.i v0, 0 # Splat zero. + +zero_loop: + vse8.v v0, (a3) # Store zero. + sub a2, a2, t1 # Decrement count. + add a3, a3, t1 # Bump pointer + vsetvli t1, a2, e8, m8, ta, ma # Vectors of bytes. + bnez a2, zero_loop # Anymore? + + ret diff --git a/src/example/vvaddint32.s b/src/example/vvaddint32.s new file mode 100644 index 0000000..22305d9 --- /dev/null +++ b/src/example/vvaddint32.s @@ -0,0 +1,22 @@ + .text + .balign 4 + .global vvaddint32 + # vector-vector add routine of 32-bit integers + # void vvaddint32(size_t n, const int*x, const int*y, int*z) + # { for (size_t i=0; i<n; i++) { z[i]=x[i]+y[i]; } } + # + # a0 = n, a1 = x, a2 = y, a3 = z + # Non-vector instructions are indented +vvaddint32: + vsetvli t0, a0, e32, ta, ma # Set vector length based on 32-bit vectors + vle32.v v0, (a1) # Get first vector + sub a0, a0, t0 # Decrement number done + slli t0, t0, 2 # Multiply number done by 4 bytes + add a1, a1, t0 # Bump pointer + vle32.v v1, (a2) # Get second vector + add a2, a2, t0 # Bump pointer + vadd.vv v2, v0, v1 # Sum vectors + vse32.v v2, (a3) # Store result + add a3, a3, t0 # Bump pointer + bnez a0, vvaddint32 # Loop back + ret # Finished diff --git a/src/fraclmul.adoc b/src/fraclmul.adoc new file mode 100644 index 0000000..6f12f58 --- /dev/null +++ b/src/fraclmul.adoc @@ -0,0 +1,174 @@ +=== Fractional Lmul example + +This appendix presents a non-normative example to help explain where +compilers can make good use of the fractional LMUL feature. + +Consider the following (admittedly contrived) loop written in C: + +---- +void add_ref(long N, + signed char *restrict c_c, signed char *restrict c_a, signed char *restrict c_b, + long *restrict l_c, long *restrict l_a, long *restrict l_b, + long *restrict l_d, long *restrict l_e, long *restrict l_f, + long *restrict l_g, long *restrict l_h, long *restrict l_i, + long *restrict l_j, long *restrict l_k, long *restrict l_l, + long *restrict l_m) { + long i; + for (i = 0; i < N; i++) { + c_c[i] = c_a[i] + c_b[i]; // Note this 'char' addition that creates a mixed type situation + l_c[i] = l_a[i] + l_b[i]; + l_f[i] = l_d[i] + l_e[i]; + l_i[i] = l_g[i] + l_h[i]; + l_l[i] = l_k[i] + l_j[i]; + l_m[i] += l_m[i] + l_c[i] + l_f[i] + l_i[i] + l_l[i]; + } +} +---- + +The example loop has a high register pressure due to the many input variables +and temporaries required. The compiler realizes there are two datatypes within +the loop: an 8-bit 'char' and a 64-bit 'long *'. Without fractional LMUL, the +compiler would be forced to use LMUL=1 for the 8-bit computation and LMUL=8 for +the 64-bit computation(s), to have equal number of elements on all computations +within the same loop iteration. Under LMUL=8, only 4 registers are available +to the register allocator. Given the large number of 64-bit variables and +temporaries required in this loop, the compiler ends up generating a lot of +spill code. The code below demonstrates this effect: + +---- +.LBB0_4: # %vector.body + # =>This Inner Loop Header: Depth=1 + add s9, a2, s6 + vsetvli s1, zero, e8,m1,ta,mu + vle8.v v25, (s9) + add s1, a3, s6 + vle8.v v26, (s1) + vadd.vv v25, v26, v25 + add s1, a1, s6 + vse8.v v25, (s1) + add s9, a5, s10 + vsetvli s1, zero, e64,m8,ta,mu + vle64.v v8, (s9) + add s1, a6, s10 + vle64.v v16, (s1) + add s1, a7, s10 + vle64.v v24, (s1) + add s1, s3, s10 + vle64.v v0, (s1) + sd a0, -112(s0) + ld a0, -128(s0) + vs8r.v v0, (a0) # Spill LMUL=8 + add s9, t6, s10 + add s11, t5, s10 + add ra, t2, s10 + add s1, t3, s10 + vle64.v v0, (s9) + ld s9, -136(s0) + vs8r.v v0, (s9) # Spill LMUL=8 + vle64.v v0, (s11) + ld s9, -144(s0) + vs8r.v v0, (s9) # Spill LMUL=8 + vle64.v v0, (ra) + ld s9, -160(s0) + vs8r.v v0, (s9) # Spill LMUL=8 + vle64.v v0, (s1) + ld s1, -152(s0) + vs8r.v v0, (s1) # Spill LMUL=8 + vadd.vv v16, v16, v8 + ld s1, -128(s0) + vl8r.v v8, (s1) # Reload LMUL=8 + vadd.vv v8, v8, v24 + ld s1, -136(s0) + vl8r.v v24, (s1) # Reload LMUL=8 + ld s1, -144(s0) + vl8r.v v0, (s1) # Reload LMUL=8 + vadd.vv v24, v0, v24 + ld s1, -128(s0) + vs8r.v v24, (s1) # Spill LMUL=8 + ld s1, -152(s0) + vl8r.v v0, (s1) # Reload LMUL=8 + ld s1, -160(s0) + vl8r.v v24, (s1) # Reload LMUL=8 + vadd.vv v0, v0, v24 + add s1, a4, s10 + vse64.v v16, (s1) + add s1, s2, s10 + vse64.v v8, (s1) + vadd.vv v8, v8, v16 + add s1, t4, s10 + ld s9, -128(s0) + vl8r.v v16, (s9) # Reload LMUL=8 + vse64.v v16, (s1) + add s9, t0, s10 + vadd.vv v8, v8, v16 + vle64.v v16, (s9) + add s1, t1, s10 + vse64.v v0, (s1) + vadd.vv v8, v8, v0 + vsll.vi v16, v16, 1 + vadd.vv v8, v8, v16 + vse64.v v8, (s9) + add s6, s6, s7 + add s10, s10, s8 + bne s6, s4, .LBB0_4 +---- + +If instead of using LMUL=1 for the 8-bit computation, the compiler is allowed +to use a fractional LMUL=1/2, then the 64-bit computations can be performed +using LMUL=4 (note that the same ratio of 64-bit elements and 8-bit elements is +preserved as in the previous example). Now the compiler has 8 available +registers to perform register allocation, resulting in no spill code, as +shown in the loop below: + +---- +.LBB0_4: # %vector.body + # =>This Inner Loop Header: Depth=1 + add s9, a2, s6 + vsetvli s1, zero, e8,mf2,ta,mu // LMUL=1/2 ! + vle8.v v25, (s9) + add s1, a3, s6 + vle8.v v26, (s1) + vadd.vv v25, v26, v25 + add s1, a1, s6 + vse8.v v25, (s1) + add s9, a5, s10 + vsetvli s1, zero, e64,m4,ta,mu // LMUL=4 + vle64.v v28, (s9) + add s1, a6, s10 + vle64.v v8, (s1) + vadd.vv v28, v8, v28 + add s1, a7, s10 + vle64.v v8, (s1) + add s1, s3, s10 + vle64.v v12, (s1) + add s1, t6, s10 + vle64.v v16, (s1) + add s1, t5, s10 + vle64.v v20, (s1) + add s1, a4, s10 + vse64.v v28, (s1) + vadd.vv v8, v12, v8 + vadd.vv v12, v20, v16 + add s1, t2, s10 + vle64.v v16, (s1) + add s1, t3, s10 + vle64.v v20, (s1) + add s1, s2, s10 + vse64.v v8, (s1) + add s9, t4, s10 + vadd.vv v16, v20, v16 + add s11, t0, s10 + vle64.v v20, (s11) + vse64.v v12, (s9) + add s1, t1, s10 + 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\ No newline at end of file diff --git a/src/images/wavedrom/v-inst-table.adoc b/src/images/wavedrom/v-inst-table.adoc new file mode 100644 index 0000000..0c02220 --- /dev/null +++ b/src/images/wavedrom/v-inst-table.adoc @@ -0,0 +1,210 @@ + +// [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +[cols="<,<,<,<,<,<,<,<,<,<,<,<,<",options="headers"] +|=== +5+| Integer 4+| Integer 4+| FP + +| funct3 | | | | | funct3 | | | | funct3 | | | +| OPIVV |V| | | | OPMVV{nbsp} |V| | | OPFVV |V| | +| OPIVX | |X| | | OPMVX{nbsp} | |X| | OPFVF | |F| +| OPIVI | | |I| | | | | | | | | +|=== + +[cols="<,<,<,<,<,<,<,<,<,<,<,<,<",options="headers"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 000000 |V|X|I| vadd | 000000 |V| | vredsum | 000000 |V|F| vfadd +| 000001 | | | | | 000001 |V| | vredand | 000001 |V| | vfredusum +| 000010 |V|X| | vsub | 000010 |V| | vredor | 000010 |V|F| vfsub +| 000011 | |X|I| vrsub | 000011 |V| | vredxor | 000011 |V| | vfredosum +| 000100 |V|X| | vminu | 000100 |V| | vredminu | 000100 |V|F| vfmin +| 000101 |V|X| | vmin | 000101 |V| | vredmin | 000101 |V| | vfredmin +| 000110 |V|X| | vmaxu | 000110 |V| | vredmaxu | 000110 |V|F| vfmax +| 000111 |V|X| | vmax | 000111 |V| | vredmax | 000111 |V| | vfredmax +| 001000 | | | | | 001000 |V|X| vaaddu | 001000 |V|F| vfsgnj +| 001001 |V|X|I| vand | 001001 |V|X| vaadd | 001001 |V|F| vfsgnjn +| 001010 |V|X|I| vor | 001010 |V|X| vasubu | 001010 |V|F| vfsgnjx +| 001011 |V|X|I| vxor | 001011 |V|X| vasub | 001011 | | | +| 001100 |V|X|I| vrgather | 001100 | | | | 001100 | | | +| 001101 | | | | | 001101 | | | | 001101 | | | +| 001110 | |X|I| vslideup | 001110 | |X| vslide1up | 001110 | |F| vfslide1up +| 001110 |V| | |vrgatherei16| | | | | | | | +| 001111 | |X|I| vslidedown | 001111 | |X| vslide1down | 001111 | |F| vfslide1down +|=== + +// [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 010000 |V|X|I| vadc | 010000 |V| | VWXUNARY0 | 010000 |V| | VWFUNARY0 +| | | | | | 010000 | |X| VRXUNARY0 | 010000 | |F| VRFUNARY0 +| 010001 |V|X|I| vmadc | 010001 | | | | 010001 | | | +| 010010 |V|X| | vsbc | 010010 |V| | VXUNARY0 | 010010 |V| | VFUNARY0 +| 010011 |V|X| | vmsbc | 010011 | | | | 010011 |V| | VFUNARY1 +| 010100 | | | | | 010100 |V| | VMUNARY0 | 010100 | | | +| 010101 | | | | | 010101 | | | | 010101 | | | +| 010110 | | | | | 010110 | | | | 010110 | | | +| 010111 |V|X|I| vmerge/vmv | 010111 |V| | vcompress | 010111 | |F| vfmerge/vfmv +| 011000 |V|X|I| vmseq | 011000 |V| | vmandn | 011000 |V|F| vmfeq +| 011001 |V|X|I| vmsne | 011001 |V| | vmand | 011001 |V|F| vmfle +| 011010 |V|X| | vmsltu | 011010 |V| | vmor | 011010 | | | +| 011011 |V|X| | vmslt | 011011 |V| | vmxor | 011011 |V|F| vmflt +| 011100 |V|X|I| vmsleu | 011100 |V| | vmorn | 011100 |V|F| vmfne +| 011101 |V|X|I| vmsle | 011101 |V| | vmnand | 011101 | |F| vmfgt +| 011110 | |X|I| vmsgtu | 011110 |V| | vmnor | 011110 | | | +| 011111 | |X|I| vmsgt | 011111 |V| | vmxnor | 011111 | |F| vmfge +|=== + +// [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 100000 |V|X|I| vsaddu | 100000 |V|X| vdivu | 100000 |V|F| vfdiv +| 100001 |V|X|I| vsadd | 100001 |V|X| vdiv | 100001 | |F| vfrdiv +| 100010 |V|X| | vssubu | 100010 |V|X| vremu | 100010 | | | +| 100011 |V|X| | vssub | 100011 |V|X| vrem | 100011 | | | +| 100100 | | | | | 100100 |V|X| vmulhu | 100100 |V|F| vfmul +| 100101 |V|X|I| vsll | 100101 |V|X| vmul | 100101 | | | +| 100110 | | | | | 100110 |V|X| vmulhsu | 100110 | | | +| 100111 |V|X| | vsmul | 100111 |V|X| vmulh | 100111 | |F| vfrsub +| 100111 | | |I| vmv<nr>r | | | | | | | | +| 101000 |V|X|I| vsrl | 101000 | | | | 101000 |V|F| vfmadd +| 101001 |V|X|I| vsra | 101001 |V|X| vmadd | 101001 |V|F| vfnmadd +| 101010 |V|X|I| vssrl | 101010 | | | | 101010 |V|F| vfmsub +| 101011 |V|X|I| vssra | 101011 |V|X| vnmsub | 101011 |V|F| vfnmsub +| 101100 |V|X|I| vnsrl | 101100 | | | | 101100 |V|F| vfmacc +| 101101 |V|X|I| vnsra | 101101 |V|X| vmacc | 101101 |V|F| vfnmacc +| 101110 |V|X|I| vnclipu | 101110 | | | | 101110 |V|F| vfmsac +| 101111 |V|X|I| vnclip | 101111 |V|X| vnmsac | 101111 |V|F| vfnmsac +|=== + +// [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 110000 |V| | | vwredsumu | 110000 |V|X| vwaddu | 110000 |V|F| vfwadd +| 110001 |V| | | vwredsum | 110001 |V|X| vwadd | 110001 |V| | vfwredusum +| 110010 | | | | | 110010 |V|X| vwsubu | 110010 |V|F| vfwsub +| 110011 | | | | | 110011 |V|X| vwsub | 110011 |V| | vfwredosum +| 110100 | | | | | 110100 |V|X| vwaddu.w | 110100 |V|F| vfwadd.w +| 110101 | | | | | 110101 |V|X| vwadd.w | 110101 | | | +| 110110 | | | | | 110110 |V|X| vwsubu.w | 110110 |V|F| vfwsub.w +| 110111 | | | | | 110111 |V|X| vwsub.w | 110111 | | | +| 111000 | | | | | 111000 |V|X| vwmulu | 111000 |V|F| vfwmul +| 111001 | | | | | 111001 | | | | 111001 | | | +| 111010 | | | | | 111010 |V|X| vwmulsu | 111010 | | | +| 111011 | | | | | 111011 |V|X| vwmul | 111011 | | | +| 111100 | | | | | 111100 |V|X| vwmaccu | 111100 |V|F| vfwmacc +| 111101 | | | | | 111101 |V|X| vwmacc | 111101 |V|F| vfwnmacc +| 111110 | | | | | 111110 | |X| vwmaccus | 111110 |V|F| vfwmsac +| 111111 | | | | | 111111 |V|X| vwmaccsu | 111111 |V|F| vfwnmsac +|=== + +<<< + +.VRXUNARY0 encoding space +[cols="2,14"] +|=== +| vs2 | + +| 00000 | vmv.s.x +|=== + +.VWXUNARY0 encoding space +[cols="2,14"] +|=== +| vs1 | + +| 00000 | vmv.x.s +| 10000 | vcpop +| 10001 | vfirst +|=== + +.VXUNARY0 encoding space +[cols="2,14"] +|=== +| vs1 | + +| 00010 | vzext.vf8 +| 00011 | vsext.vf8 +| 00100 | vzext.vf4 +| 00101 | vsext.vf4 +| 00110 | vzext.vf2 +| 00111 | vsext.vf2 +|=== + +.VRFUNARY0 encoding space +[cols="2,14"] +|=== +| vs2 | + +| 00000 | vfmv.s.f +|=== + +.VWFUNARY0 encoding space +[cols="2,14"] +|=== +| vs1 | + +| 00000 | vfmv.f.s +|=== + +.VFUNARY0 encoding space +[cols="2,14"] +|=== +| vs1 | name + +2+| single-width converts +| 00000 | vfcvt.xu.f.v +| 00001 | vfcvt.x.f.v +| 00010 | vfcvt.f.xu.v +| 00011 | vfcvt.f.x.v +| 00110 | vfcvt.rtz.xu.f.v +| 00111 | vfcvt.rtz.x.f.v +| | +2+| widening converts +| 01000 | vfwcvt.xu.f.v +| 01001 | vfwcvt.x.f.v +| 01010 | vfwcvt.f.xu.v +| 01011 | vfwcvt.f.x.v +| 01100 | vfwcvt.f.f.v +| 01110 | vfwcvt.rtz.xu.f.v +| 01111 | vfwcvt.rtz.x.f.v +| | +2+| narrowing converts +| 10000 | vfncvt.xu.f.w +| 10001 | vfncvt.x.f.w +| 10010 | vfncvt.f.xu.w +| 10011 | vfncvt.f.x.w +| 10100 | vfncvt.f.f.w +| 10101 | vfncvt.rod.f.f.w +| 10110 | vfncvt.rtz.xu.f.w +| 10111 | vfncvt.rtz.x.f.w +|=== + +.VFUNARY1 encoding space +[cols="2,14"] +|=== +| vs1 | name + +| 00000 | vfsqrt.v +| 00100 | vfrsqrt7.v +| 00101 | vfrec7.v +| 10000 | vfclass.v +|=== + + +.VMUNARY0 encoding space +[cols="2,14"] +|=== +| vs1 | + +| 00001 | vmsbf +| 00010 | vmsof +| 00011 | vmsif +| 10000 | viota +| 10001 | vid +|=== + + diff --git a/src/images/wavedrom/valu-format.adoc b/src/images/wavedrom/valu-format.adoc new file mode 100644 index 0000000..cdd3447 --- /dev/null +++ b/src/images/wavedrom/valu-format.adoc @@ -0,0 +1,104 @@ +Formats for Vector Arithmetic Instructions under OP-V major opcode + +//// +31 26 25 24 20 19 15 14 12 11 7 6 0 + funct6 | vm | vs2 | vs1 | 0 0 0 | vd |1010111| OP-V (OPIVV) + funct6 | vm | vs2 | vs1 | 0 0 1 | vd/rd |1010111| OP-V (OPFVV) + funct6 | vm | vs2 | vs1 | 0 1 0 | vd/rd |1010111| OP-V (OPMVV) + funct6 | vm | vs2 | imm[4:0] | 0 1 1 | vd |1010111| OP-V (OPIVI) + funct6 | vm | vs2 | rs1 | 1 0 0 | vd |1010111| OP-V (OPIVX) + funct6 | vm | vs2 | rs1 | 1 0 1 | vd |1010111| OP-V (OPFVF) + funct6 | vm | vs2 | rs1 | 1 1 0 | vd/rd |1010111| OP-V (OPMVX) + 6 1 5 5 3 5 7 +//// + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'OPIVV'}, + {bits: 5, name: 'vd', type: 2}, + {bits: 3, name: 0}, + {bits: 5, name: 'vs1', type: 2}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'OPFVV'}, + {bits: 5, name: 'vd / rd', type: 7}, + {bits: 3, name: 1}, + {bits: 5, name: 'vs1', type: 2}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'OPMVV'}, + {bits: 5, name: 'vd / rd', type: 7}, + {bits: 3, name: 2}, + {bits: 5, name: 'vs1', type: 2}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: ['OPIVI']}, + {bits: 5, name: 'vd', type: 2}, + {bits: 3, name: 3}, + {bits: 5, name: 'imm[4:0]', type: 5}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'OPIVX'}, + {bits: 5, name: 'vd', type: 2}, + {bits: 3, name: 4}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'OPFVF'}, + {bits: 5, name: 'vd', type: 2}, + {bits: 3, name: 5}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'OPMVX'}, + {bits: 5, name: 'vd / rd', type: 7}, + {bits: 3, name: 6}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'vs2', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 6, name: 'funct6'}, +]} +.... diff --git a/src/images/wavedrom/vcfg-format.adoc b/src/images/wavedrom/vcfg-format.adoc new file mode 100644 index 0000000..ac0353c --- /dev/null +++ b/src/images/wavedrom/vcfg-format.adoc @@ -0,0 +1,47 @@ +Formats for Vector Configuration Instructions under OP-V major opcode + +//// + 31 30 25 24 20 19 15 14 12 11 7 6 0 + 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli + 1 | 1| zimm[ 9:0] | uimm[4:0]| 1 1 1 | rd |1010111| vsetivli + 1 | 000000 | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl + 1 6 5 5 3 5 7 +//// + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'vsetvli'}, + {bits: 5, name: 'rd', type: 4}, + {bits: 3, name: 7}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 11, name: 'vtypei[10:0]', type: 5}, + {bits: 1, name: '0'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'vsetivli'}, + {bits: 5, name: 'rd', type: 4}, + {bits: 3, name: 7}, + {bits: 5, name: 'uimm[4:0]', type: 5}, + {bits: 10, name: 'vtypei[9:0]', type: 5}, + {bits: 1, name: '1'}, + {bits: 1, name: '1'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x57, attr: 'vsetvl'}, + {bits: 5, name: 'rd', type: 4}, + {bits: 3, name: 7}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'rs2', type: 4}, + {bits: 6, name: 0x00}, + {bits: 1, name: 1}, +]} +.... diff --git a/src/images/wavedrom/vfrec7.adoc b/src/images/wavedrom/vfrec7.adoc new file mode 100644 index 0000000..d33f44e --- /dev/null +++ b/src/images/wavedrom/vfrec7.adoc @@ -0,0 +1,136 @@ +.vfrec7.v common-case lookup table contents +[%autowidth,float="center",align="center",options="header"] +|=== + +| sig[MSB -: 7] | sig_out[MSB -: 7] + +| 0 | 127 +| 1 | 125 +| 2 | 123 +| 3 | 121 +| 4 | 119 +| 5 | 117 +| 6 | 116 +| 7 | 114 +| 8 | 112 +| 9 | 110 +| 10 | 109 +| 11 | 107 +| 12 | 105 +| 13 | 104 +| 14 | 102 +| 15 | 100 +| 16 | 99 +| 17 | 97 +| 18 | 96 +| 19 | 94 +| 20 | 93 +| 21 | 91 +| 22 | 90 +| 23 | 88 +| 24 | 87 +| 25 | 85 +| 26 | 84 +| 27 | 83 +| 28 | 81 +| 29 | 80 +| 30 | 79 +| 31 | 77 +| 32 | 76 +| 33 | 75 +| 34 | 74 +| 35 | 72 +| 36 | 71 +| 37 | 70 +| 38 | 69 +| 39 | 68 +| 40 | 66 +| 41 | 65 +| 42 | 64 +| 43 | 63 +| 44 | 62 +| 45 | 61 +| 46 | 60 +| 47 | 59 +| 48 | 58 +| 49 | 57 +| 50 | 56 +| 51 | 55 +| 52 | 54 +| 53 | 53 +| 54 | 52 +| 55 | 51 +| 56 | 50 +| 57 | 49 +| 58 | 48 +| 59 | 47 +| 60 | 46 +| 61 | 45 +| 62 | 44 +| 63 | 43 +| 64 | 42 +| 65 | 41 +| 66 | 40 +| 67 | 40 +| 68 | 39 +| 69 | 38 +| 70 | 37 +| 71 | 36 +| 72 | 35 +| 73 | 35 +| 74 | 34 +| 75 | 33 +| 76 | 32 +| 77 | 31 +| 78 | 31 +| 79 | 30 +| 80 | 29 +| 81 | 28 +| 82 | 28 +| 83 | 27 +| 84 | 26 +| 85 | 25 +| 86 | 25 +| 87 | 24 +| 88 | 23 +| 89 | 23 +| 90 | 22 +| 91 | 21 +| 92 | 21 +| 93 | 20 +| 94 | 19 +| 95 | 19 +| 96 | 18 +| 97 | 17 +| 98 | 17 +| 99 | 16 +| 100 | 15 +| 101 | 15 +| 102 | 14 +| 103 | 14 +| 104 | 13 +| 105 | 12 +| 106 | 12 +| 107 | 11 +| 108 | 11 +| 109 | 10 +| 110 | 9 +| 111 | 9 +| 112 | 8 +| 113 | 8 +| 114 | 7 +| 115 | 7 +| 116 | 6 +| 117 | 5 +| 118 | 5 +| 119 | 4 +| 120 | 4 +| 121 | 3 +| 122 | 3 +| 123 | 2 +| 124 | 2 +| 125 | 1 +| 126 | 1 +| 127 | 0 + +|=== diff --git a/src/images/wavedrom/vfrsqrt7.adoc b/src/images/wavedrom/vfrsqrt7.adoc new file mode 100644 index 0000000..8ebc621 --- /dev/null +++ b/src/images/wavedrom/vfrsqrt7.adoc @@ -0,0 +1,137 @@ +.vfrsqrt7.v common-case lookup table contents +[%autowidth,float=center,align=center,options="header"] +|=== + +|exp[0] | sig[MSB -: 6] | sig_out[MSB -: 7] + +| 0| 0 | 52 +| 0| 1 | 51 +| 0| 2 | 50 +| 0| 3 | 48 +| 0| 4 | 47 +| 0| 5 | 46 +| 0| 6 | 44 +| 0| 7 | 43 +| 0| 8 | 42 +| 0| 9 | 41 +| 0| 10 | 40 +| 0| 11 | 39 +| 0| 12 | 38 +| 0| 13 | 36 +| 0| 14 | 35 +| 0| 15 | 34 +| 0| 16 | 33 +| 0| 17 | 32 +| 0| 18 | 31 +| 0| 19 | 30 +| 0| 20 | 30 +| 0| 21 | 29 +| 0| 22 | 28 +| 0| 23 | 27 +| 0| 24 | 26 +| 0| 25 | 25 +| 0| 26 | 24 +| 0| 27 | 23 +| 0| 28 | 23 +| 0| 29 | 22 +| 0| 30 | 21 +| 0| 31 | 20 +| 0| 32 | 19 +| 0| 33 | 19 +| 0| 34 | 18 +| 0| 35 | 17 +| 0| 36 | 16 +| 0| 37 | 16 +| 0| 38 | 15 +| 0| 39 | 14 +| 0| 40 | 14 +| 0| 41 | 13 +| 0| 42 | 12 +| 0| 43 | 12 +| 0| 44 | 11 +| 0| 45 | 10 +| 0| 46 | 10 +| 0| 47 | 9 +| 0| 48 | 9 +| 0| 49 | 8 +| 0| 50 | 7 +| 0| 51 | 7 +| 0| 52 | 6 +| 0| 53 | 6 +| 0| 54 | 5 +| 0| 55 | 4 +| 0| 56 | 4 +| 0| 57 | 3 +| 0| 58 | 3 +| 0| 59 | 2 +| 0| 60 | 2 +| 0| 61 | 1 +| 0| 62 | 1 +| 0| 63 | 0 + +| 1| 0 | 127 +| 1| 1 | 125 +| 1| 2 | 123 +| 1| 3 | 121 +| 1| 4 | 119 +| 1| 5 | 118 +| 1| 6 | 116 +| 1| 7 | 114 +| 1| 8 | 113 +| 1| 9 | 111 +| 1| 10 | 109 +| 1| 11 | 108 +| 1| 12 | 106 +| 1| 13 | 105 +| 1| 14 | 103 +| 1| 15 | 102 +| 1| 16 | 100 +| 1| 17 | 99 +| 1| 18 | 97 +| 1| 19 | 96 +| 1| 20 | 95 +| 1| 21 | 93 +| 1| 22 | 92 +| 1| 23 | 91 +| 1| 24 | 90 +| 1| 25 | 88 +| 1| 26 | 87 +| 1| 27 | 86 +| 1| 28 | 85 +| 1| 29 | 84 +| 1| 30 | 83 +| 1| 31 | 82 +| 1| 32 | 80 +| 1| 33 | 79 +| 1| 34 | 78 +| 1| 35 | 77 +| 1| 36 | 76 +| 1| 37 | 75 +| 1| 38 | 74 +| 1| 39 | 73 +| 1| 40 | 72 +| 1| 41 | 71 +| 1| 42 | 70 +| 1| 43 | 70 +| 1| 44 | 69 +| 1| 45 | 68 +| 1| 46 | 67 +| 1| 47 | 66 +| 1| 48 | 65 +| 1| 49 | 64 +| 1| 50 | 63 +| 1| 51 | 63 +| 1| 52 | 62 +| 1| 53 | 61 +| 1| 54 | 60 +| 1| 55 | 59 +| 1| 56 | 59 +| 1| 57 | 58 +| 1| 58 | 57 +| 1| 59 | 56 +| 1| 60 | 56 +| 1| 61 | 55 +| 1| 62 | 54 +| 1| 63 | 53 + +|===
\ No newline at end of file diff --git a/src/images/wavedrom/vmem-format.adoc b/src/images/wavedrom/vmem-format.adoc new file mode 100644 index 0000000..f9b25ee --- /dev/null +++ b/src/images/wavedrom/vmem-format.adoc @@ -0,0 +1,108 @@ +Format for Vector Load Instructions under LOAD-FP major opcode + +//// +31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0 + nf | mew| mop | vm | lumop | rs1 | width | vd |0000111| VL* unit-stride + nf | mew| mop | vm | rs2 | rs1 | width | vd |0000111| VLS* strided + nf | mew| mop | vm | vs2 | rs1 | width | vd |0000111| VLX* indexed + 3 1 2 1 5 5 3 5 7 +//// + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x7, attr: 'VL* unit-stride'}, + {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'lumop'}, + {bits: 1, name: 'vm'}, + {bits: 2, name: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x7, attr: 'VLS* strided'}, + {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'rs2', attr: 'stride', type: 4}, + {bits: 1, name: 'vm'}, + {bits: 2, name: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x7, attr: 'VLX* indexed'}, + {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 2, name: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... +Format for Vector Store Instructions under STORE-FP major opcode + +//// +31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0 + nf | mew| mop | vm | sumop | rs1 | width | vs3 |0100111| VS* unit-stride + nf | mew| mop | vm | rs2 | rs1 | width | vs3 |0100111| VSS* strided + nf | mew| mop | vm | vs2 | rs1 | width | vs3 |0100111| VSX* indexed + 3 1 2 1 5 5 3 5 7 +//// + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x27, attr: 'VS* unit-stride'}, + {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'sumop'}, + {bits: 1, name: 'vm'}, + {bits: 2, name: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x27, attr: 'VSS* strided'}, + {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'rs2', attr: 'stride', type: 4}, + {bits: 1, name: 'vm'}, + {bits: 2, name: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x27, attr: 'VSX* indexed'}, + {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, + {bits: 1, name: 'vm'}, + {bits: 2, name: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... diff --git a/src/images/wavedrom/vtype-format.adoc b/src/images/wavedrom/vtype-format.adoc new file mode 100644 index 0000000..9e6ab34 --- /dev/null +++ b/src/images/wavedrom/vtype-format.adoc @@ -0,0 +1,28 @@ +[wavedrom,,svg] +.... +{reg: [ + {bits: 3, name: 'vlmul[2:0]'}, + {bits: 3, name: 'vsew[2:0]'}, + {bits: 1, name: 'vta'}, + {bits: 1, name: 'vma'}, + {bits: 23, name: 'reserved'}, + {bits: 1, name: 'vill'}, +]} +.... + +NOTE: This diagram shows the layout for RV32 systems, whereas in +general `vill` should be at bit XLEN-1. + +.`vtype` register layout +[cols=">2,4,10"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Bits | Name | Description + +| XLEN-1 | vill | Illegal value if set +| XLEN-2:8 | 0 | Reserved if non-zero +| 7 | vma | Vector mask agnostic +| 6 | vta | Vector tail agnostic +| 5:3 | vsew[2:0] | Selected element width (SEW) setting +| 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting +|=== diff --git a/src/resources/riscv-spec.bib b/src/resources/riscv-spec.bib index 1354344..db5bb1b 100644 --- a/src/resources/riscv-spec.bib +++ b/src/resources/riscv-spec.bib @@ -514,3 +514,1268 @@ address = {Toronto, Canada}} HAL_ID = {hal-01091186}, HAL_VERSION = {v1}, } + +@electronic{unpriv, + title = {RISC-V Instruction Set Manual, Volume I: Unprivileged ISA }, + url = {https://github.com/riscv/riscv-isa-manual}, + year = {} +} +@inproceedings{queue, + author = {Michael, Maged M. and Scott, Michael L.}, + title = {Simple, Fast, and Practical Non-Blocking and Blocking Concurrent Queue Algorithms}, + year = {1996}, + isbn = {0897918002}, + publisher = {Association for Computing Machinery}, + address = {New York, NY, USA}, + url = {https://doi.org/10.1145/248052.248106}, + doi = {10.1145/248052.248106}, + booktitle = {Proceedings of the Fifteenth Annual ACM Symposium on Principles of Distributed Computing}, + pages = {267–275}, + numpages = {9}, + keywords = {multiprogramming, compare_and_swap, non-blocking, concurrent queue, lock-free}, + location = {Philadelphia, Pennsylvania, USA}, + series = {PODC '96} +} + +// Bibliographical refs from Crypto + + +% +% RISC-V Specifications and draft specifications +% ----------------------------------------------------------------- + +@misc{riscv:policy:encodings, + title={RISC-V Instruction Encoding Allocation Policy}, + url={https://docs.google.com/document/d/1uC6QAyFmglGbO9kRR-X8LQWga6B3yBJR7-iw6ZXnfG8/edit#} +} + +@misc{riscv:bitmanip:repo, + title = {RISC-V Bit manipulation extension repository}, + url = {https://github.com/riscv/riscv-bitmanip} +} + +@misc{riscv:bitmanip:draft, + title = {RISC-V Bit manipulation extension draft proposal}, + url = {https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf} +} + +@article{riscv:spec:user, + title={The RISC-V instruction set manual}, + author={Waterman, Andrew and Lee, Yunsup and Patterson, David and Asanovic, Krste}, + journal={Volume I: User-Level ISA', version}, + volume={2}, + year={2014} +} + +@misc{sail, + title = {SAIL ISA Specification Language}, + url = {https://github.com/rems-project/sail} +} + +@inproceedings{LSYRR:04, + title={On permutation operations in cipher design}, + author={Lee, Ruby B and Shi, ZJ and Yin, Yiqun Lisa and Rivest, Ronald L and Robshaw, Matthew JB}, + booktitle={International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.}, + volume={2}, + pages={569--577}, + year={2004}, + organization={IEEE} +} +% +% NIST Specifications and recommendations +% ----------------------------------------------------------------- + +@misc{nist:gcm, + author = {Morris Dworkin}, + title = {Recommendation for Block Cipher Modes of Operation: + {Galois}/{Counter} {Mode} ({GCM}) and {GMAC}}, + howpublished = {NIST Special Publication SP 800-38D}, + url = {https://doi.org/10.6028/NIST.SP.800-38D}, + month = {November}, + year = {2007} +} + + +@misc{nist:fips:186:4, + author = {{NIST}}, + title = {Digital Signature Standard (DSS)}, + howpublished = {Federal Information Processing Standards Publication FIPS 186-4}, + url = {https://doi.org/10.6028/NIST.FIPS.186-4}, + month = {July}, + year = {2013} +} + +@misc{nist:fips:197, + author = {{NIST}}, + title = {{Advanced} {Encryption} {Standard} ({AES})}, + howpublished = {Federal Information Processing Standards Publication FIPS + 197}, + url = {https://doi.org/10.6028/NIST.FIPS.197}, + month = {November}, + year = {2001} +} + + +@misc{nist:fips:180:4, + author = {{NIST}}, + title = {Secure Hash Standard ({SHS})}, + howpublished = {Federal Information Processing Standards Publication FIPS 180-4}, + url = {https://doi.org/10.6028/NIST.FIPS.180-4}, + month = {August}, + year = {2015} +} + +@misc{nist:fips:202, + author = {{NIST}}, + title = {{SHA}-3 Standard: Permutation-Based Hash and Extendable-Output Functions}, + howpublished = {Federal Information Processing Standards Publication FIPS + 202}, + url = {https://doi.org/10.6028/NIST.FIPS.202}, + month = {August}, + year = {2015} +} + +% +% PRC Standards (which are also ISO/IEC standards) +% ----------------------------------------------------------------- + + +@Misc{gbt:sm3, + title = {{GB}/{T} 32905-2016: {SM3} Cryptographic Hash Algorithm}, + howpublished = {Also {GM}/{T} 0004-2012. Standardization Administration of China}, + url = {http://www.gmbz.org.cn/upload/2018-07-24/1532401392982079739.pdf}, + month = {August}, + year = {2016} +} + +@Misc{gbt:sm4, + title = {{GB}/{T} 32907-2016: {SM4} Block Cipher Algorithm}, + howpublished = {Also {GM}/{T} 0002-2012. Standardization Administration of China}, + url = {http://www.gmbz.org.cn/upload/2018-04-04/1522788048733065051.pdf}, + month = {August}, + year = {2016} +} + +@Misc{iso:sm3, + author = {ISO/IEC}, + title = {IT Security techniques -- Hash-functions -- Part 3: + Dedicated hash-functions}, + howpublished = {{ISO}/{IEC} Standard 10118-3:2018}, + year = {2018} +} + +@Misc{iso:sm4, + author = {ISO/IEC}, + title = {Information technology -- Security techniques -- + Encryption algorithms -- Part 3: Block ciphers. {Amendment} + 2: {SM4}}, + howpublished = {{ISO}/{IEC} Standard 18033-3:2010/DAmd 2 (en)}, + year = {2018} +} + + +% +% Miscellaneous Technical Reports +% ----------------------------------------------------------------- + +@techreport{MPP:19, + author = {Ben Marshall and Daniel Page and Thinh Pham}, + title = {{XCrypto}: a cryptographic {ISE} for {RISC-V}}, + number = {1.0.0}, + year = {2019}, + url = {https://github.com/scarv/xcrypto} +} + +% +% Academic Papers: Misc +% ----------------------------------------------------------------- + + +@article{MNPSW:20, +title={The design of scalar AES Instruction Set Extensions for RISC-V}, +volume={2021}, +url={https://tches.iacr.org/index.php/TCHES/article/view/8729}, +DOI={10.46586/tches.v2021.i1.109-136}, +number={1}, +journal={IACR Transactions on Cryptographic Hardware and Embedded Systems}, +author={Marshall, Ben and Newell, G. Richard and Page, Dan and Saarinen, Markku-Juhani O. and Wolf, Claire}, +year={2020}, +month={Dec.}, +pages={109-136} +} + +@inproceedings{TGMGD:19, + author = {Etienne Tehrani and Tarik Graba and Abdelmalek Si Merabet and Sylvain Guilley and Jean-Luc Danger}, + title = {Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations}, + year = {2019}, + month = {11}, + booktitle = {26th IEEE International Conference on Electronics Circuits and Systems} +} + +@inproceedings{TG:06, + title={Instruction set extensions for efficient AES implementation on 32-bit processors}, + author={Tillich, Stefan and Gro{\ss}sch{\"a}dl, Johann}, + booktitle={International workshop on cryptographic hardware and embedded systems}, + pages={270--284}, + year={2006}, + organization={Springer} +} + +@inproceedings{DPUVGB:16, + title={Design strategies for ARX with provable bounds: Sparx and LAX}, + author={Dinu, Daniel and Perrin, L{\'e}o and Udovenko, Aleksei and Velichkov, Vesselin and Gro{\ss}sch{\"a}dl, Johann and Biryukov, Alex}, + booktitle={International Conference on the Theory and Application of Cryptology and Information Security}, + pages={484--513}, + year={2016}, + organization={Springer} +} + +@inproceedings{LSYRR:04, + title={On permutation operations in cipher design}, + author={Lee, Ruby B and Shi, ZJ and Yin, Yiqun Lisa and Rivest, Ronald L and Robshaw, Matthew JB}, + booktitle={International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.}, + volume={2}, + pages={569--577}, + year={2004}, + organization={IEEE} +} + +@article{CDPA:16, + title={The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V}, + author={Celio, Christopher and Dabbelt, Palmer and Patterson, David A and Asanovi{\'c}, Krste}, + journal={arXiv preprint arXiv:1607.02318}, + year={2016} +} + + + +% +% Block Cipher Specifiations +% ----------------------------------------------------------------- + +@inproceedings{block:prince, + title={PRINCE--a low-latency block cipher for pervasive computing applications}, + author={Borghoff, Julia and Canteaut, Anne and G{\"u}neysu, Tim and Kavun, Elif Bilge and Knezevic, Miroslav and Knudsen, Lars R and Leander, Gregor and Nikov, Ventzislav and Paar, Christof and Rechberger, Christian and others}, + booktitle={International Conference on the Theory and Application of Cryptology and Information Security}, + pages={208--225}, + year={2012}, + organization={Springer} +} + +@inproceedings{block:present, + title={PRESENT: An ultra-lightweight block cipher}, + author={Bogdanov, Andrey and Knudsen, Lars R and Leander, Gregor and Paar, Christof and Poschmann, Axel and Robshaw, Matthew JB and Seurin, Yannick and Vikkelsoe, Charlotte}, + booktitle={International workshop on cryptographic hardware and embedded systems}, + pages={450--466}, + year={2007}, + organization={Springer} +} + +@incollection{block:salsa20, + title={The Salsa20 family of stream ciphers}, + author={Bernstein, Daniel J}, + booktitle={New stream cipher designs}, + pages={84--97}, + year={2008}, + publisher={Springer} +} + +@article{block:rectangle, + title={RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms}, + author={Zhang, Wentao and Bao, Zhenzhen and Lin, Dongdai and Rijmen, Vincent and Yang, Bohan and Verbauwhede, Ingrid}, + journal={Science China Information Sciences}, + volume={58}, + number={12}, + pages={1--15}, + year={2015}, + publisher={Springer} +} + +@inproceedings{block:gift, + title={GIFT: a small present}, + author={Banik, Subhadeep and Pandey, Sumit Kumar and Peyrin, Thomas and Sasaki, Yu and Sim, Siang Meng and Todo, Yosuke}, + booktitle={International Conference on Cryptographic Hardware and Embedded Systems}, + pages={321--345}, + year={2017}, + organization={Springer} +} + +@inproceedings{block:twine, + title={TWINE: A Lightweight Block Cipher for Multiple Platforms}, + author={Suzaki, Tomoyasu and Minematsu, Kazuhiko and Morioka, Sumio and Kobayashi, Eita}, + booktitle={International Conference on Selected Areas in Cryptography}, + pages={339--354}, + year={2012}, + organization={Springer} +} + +@inproceedings{block:skinny, + title={The SKINNY family of block ciphers and its low-latency variant MANTIS}, + author={Beierle, Christof and Jean, J{\'e}r{\'e}my and K{\"o}lbl, Stefan and Leander, Gregor and Moradi, Amir and Peyrin, Thomas and Sasaki, Yu and Sasdrich, Pascal and Sim, Siang Meng}, + booktitle={Annual International Cryptology Conference}, + pages={123--153}, + year={2016}, + organization={Springer} +} + +@inproceedings{block:midori, + title={Midori: A block cipher for low energy}, + author={Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}, + booktitle={International Conference on the Theory and Application of Cryptology and Information Security}, + pages={411--436}, + year={2015}, + organization={Springer} +} + +@inproceedings{block:camellia, + title={Camellia: A 128-bit block cipher suitable for multiple platforms—design andanalysis}, + author={Aoki, Kazumaro and Ichikawa, Tetsuya and Kanda, Masayuki and Matsui, Mitsuru and Moriai, Shiho and Nakajima, Junko and Tokita, Toshio}, + booktitle={International Workshop on Selected Areas in Cryptography}, + pages={39--56}, + year={2000}, + organization={Springer} +} + +@inproceedings{block:aria, + title={New block cipher: ARIA}, + author={Kwon, Daesung and Kim, Jaesung and Park, Sangwoo and Sung, Soo Hak and Sohn, Yaekwon and Song, Jung Hwan and Yeom, Yongjin and Yoon, E-Joong and Lee, Sangjin and Lee, Jaewon and others}, + booktitle={International Conference on Information Security and Cryptology}, + pages={432--445}, + year={2003}, + organization={Springer} +} + + + +% +% Online references +% ----------------------------------------------------------------- + +@misc{MJS:LWAES:20, + author = "Markku-Juhani O. Saarinen", + title = "Lightweight AES ISA", + howpublished = "\url{https://github.com/mjosaarinen/lwaes_isa}", + year = "2020", + month = "01", + note = "Retrieved 24th January, 2020.", +} + +@misc{MJS:LWSHA:20, + author = "Markku-Juhani O. Saarinen", + title = "Lightweight SHA ISA", + howpublished = "\url{https://github.com/mjosaarinen/lwsha_isa}", + year = "2020", + month = "03", + note = "Retrieved 26th March, 2020.", +} + + +@article{tls:1.3, + title={The transport layer security (TLS) protocol version 1.3}, + author={Rescorla, Eric and Dierks, Tim}, + year={2018}, + month={August}, + publisher={DOI 10.17487/RFC8446} +} + + +% +% Mostly academic, bibtool sorted (2020-07-08 mjos) +% ----------------------------------------------------------------- + + +@Misc{ AM17, + author = {{AMD}}, + title = {{AMD} Random Number Generator}, + howpublished = {AMD TechDocs}, + publisher = {Advanced Micro Devices}, + url = {https://www.amd.com/system/files/TechDocs/amd-random-number-generator.pdf}, + month = {June}, + year = {2017} +} + +@Misc{ AR17, + author = {{ARM}}, + title = {ARM TrustZone True Random Number Generator: Technical Reference Manual}, + howpublished = {ARM 100976\_0000\_00\_en (rev. r0p0)}, + publisher = {{ARM}}, + url = {http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100976_0000_00_en}, + month = {May}, + year = {2017} +} + +@Misc{ AR20, + author = {{ARM}}, + title = {Arm Architecture Registers: Armv8, for Armv8-A + architecture profile}, + howpublished = {ARM DDI 0595 (ID033020)}, + publisher = {{ARM}}, + url = {https://developer.arm.com/docs/ddi0595/g}, + month = {April}, + year = {2020} +} + +@Book{ An20, + author = {Ross J. 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Today}, + volume = {39}, + number = {12}, + pages = {38--45}, + doi = {10.1063/1.881047}, + publisher = {{AIP}}, + month = {December}, + year = {1986} +} + +@Misc{ BaBa19, + author = {Elaine Barker and William Barker}, + title = {Recommendation for Key Management: Part 2 -- Best + Practices for Key Management Organizations}, + howpublished = {NIST Special Publication SP 800-57 Part 2, Revision 1}, + doi = {10.6028/NIST.SP.800-57pt2r1}, + publisher = {{NIST}}, + month = {May}, + year = {2019} +} + +@Misc{ BaDa15, + author = {Elaine Barker and Quynh Dang}, + title = {Recommendation for Key Management, Part 3: + Application-Specific Key Management Guidance}, + howpublished = {NIST Special Publication SP 800-57 Part 3, Revision 1}, + doi = {10.6028/NIST.SP.800-57pt3r1}, + publisher = {{NIST}}, + month = {January}, + year = {2015} +} + +@InProceedings{ BaFoKa:12, + author = {Romain Bardou and Riccardo Focardi and Yusuke Kawamoto and + Lorenzo Simionato and Graham Steel and Joe{-}Kai Tsay}, + title = {Efficient Padding Oracle Attacks on Cryptographic + Hardware}, + booktitle = {Advances in Cryptology - {CRYPTO} 2012 - 32nd Annual + Cryptology Conference, Santa Barbara, CA, USA, August + 19-23, 2012. Proceedings}, + pages = {608--625}, + crossref = {_SaCa12}, + doi = {10.1007/978-3-642-32009-5\_36}, + year = {2012} +} + +@Misc{ BaKe15, + author = {Elaine Barker and John Kelsey}, + title = {Recommendation for Random Number Generation Using + Deterministic Random Bit Generators}, + howpublished = {NIST Special Publication SP 800-90A Revision 1}, + doi = {10.6028/NIST.SP.800-90Ar1}, + month = {June}, + year = {2015} +} + +@Misc{ BaKeRo:21, + author = {Elaine Barker and John Kelsey and Allen Roginsky and + Meltem Sönmez Turan and Darryl Buller and Aaron Kaufer}, + title = {Recommendation for Random Bit Generator ({RBG}) + Constructions}, + howpublished = {Draft NIST Special Publication SP 800-90C}, + month = {March}, + year = {2021} +} + +@Article{ BaLuMi:11, + author = {Mathieu Baudet and David Lubicz and Julien Micolod and + Andr{\'{e}} Tassiaux}, + title = {On the Security of Oscillator-Based Random Number + Generators}, + journal = {J. Cryptology}, + volume = {24}, + number = {2}, + pages = {398--425}, + doi = {10.1007/s00145-010-9089-3}, + year = {2011} +} + +@Article{ BeRePa:14, + author = {Georg T. Becker and Francesco Regazzoni and Christof Paar + and Wayne P. Burleson}, + title = {Stealthy dopant-level hardware Trojans: extended version}, + journal = {J. Cryptographic Engineering}, + volume = {4}, + number = {1}, + pages = {19--31}, + publisher = {Springer}, + doi = {10.1007/s13389-013-0068-0}, + year = {2014} +} + +@Article{ Bl86, + author = {Manuel Blum}, + title = {Independent unbiased coin flips from a correlated biased + source -- A finite state Markov chain}, + journal = {Combinatorica}, + volume = {6}, + number = {2}, + pages = {97--108}, + doi = {10.1007/BF02579167}, + year = {1986} +} + +@Article{ BlBlSh86, + author = {Lenore Blum and Manuel Blum and Mike Shub}, + title = {A Simple Unpredictable Pseudo-Random Number Generator}, + journal = {{SIAM} J. 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Very Large Scale Integr. Syst.}, + volume = {21}, + number = {12}, + pages = {2295--2306}, + doi = {10.1109/TVLSI.2012.2231707}, + publisher = {IEEE}, + year = {2013} +} + +@Misc{ KiSc01, + author = {Wolfgang Killmann and Werner Schindler}, + title = {A Proposal for: Functionality classes and evaluation + methodology for true (physical) random number generators}, + howpublished = {AIS 31, Version 3.1, English Translation, BSI}, + url = {https://www.bsi.bund.de/SharedDocs/Downloads/DE/BSI/Zertifizierung/Interpretationen/AIS_31_Functionality_classes_evaluation_methodology_for_true_RNG_e.html}, + publisher = {BSI}, + month = {September}, + year = {2001} +} + +@Misc{ KiSc11, + author = {Wolfgang Killmann and Werner Schindler}, + title = {A Proposal for: Functionality classes for random number + generators}, + howpublished = {AIS 20 / AIS 31, Version 2.0, English Translation, BSI}, + url = {https://www.bsi.bund.de/SharedDocs/Downloads/DE/BSI/Zertifizierung/Interpretationen/AIS_31_Functionality_classes_for_random_number_generators_e.html}, + publisher = {BSI}, + month = {September}, + year = {2011} +} + +@Misc{ KoXiHu:21, + author = {Nick Kossifidis and Joe Xie and Bill Huffman and Allen + Baum and Greg Favor and Tariq Kurd and Fumio Arakawa}, + title = {{PMP} Enhancements for memory access and execution + prevention on Machine mode}, + howpublished = {Version 0.9.1 -- {RISC}-{V} {TEE} Task Group}, + month = {May}, + year = {2021} +} +10.1007/978-3-540-71039-4\_21 +@InProceedings{ La08, + author = {Patrick Lacharme}, + title = {Post-Processing Functions for a Biased Physical Random + Number Generator}, + booktitle = {Fast Software Encryption, 15th International Workshop, + {FSE} 2008, Lausanne, Switzerland, February 10-13, 2008, + Revised Selected Papers}, + pages = {334--342}, + crossref = {_Ny08}, + doi = {10.1007/978-3-540-71039-4\_21}, + year = {2008} +} + +@Article{ LiBaBo:13, + author = {John S. Liberty and Adrian Barrera and David W. Boerstler + and Thomas B. Chadwick and Scott R. Cottier and H. Peter + Hofstee and Julie A. Rosser and Marty L. Tsai}, + title = {True hardware random number generation implemented in the + 32-nm {SOI} {POWER7+} processor}, + journal = {{IBM} J. Res. Dev.}, + volume = {57}, + number = {6}, + doi = {10.1147/JRD.2013.2279599}, + year = {2013} +} + +@InProceedings{ MaMo09, + author = {A. Theodore Markettos and Simon W. Moore}, + title = {The Frequency Injection Attack on Ring-Oscillator-Based + True Random Number Generators}, + booktitle = {Cryptographic Hardware and Embedded Systems - {CHES} 2009, + 11th International Workshop, Lausanne, Switzerland, + September 6-9, 2009, Proceedings}, + pages = {317--331}, + crossref = {_ClGa09}, + doi = {10.1007/978-3-642-04138-9\_23}, + year = {2009} +} + +@Misc{ Me18, + author = {John P. Mechalas}, + title = {Intel Digital Random Number Generator (DRNG) Software + Implementation Guide}, + howpublished = {Intel Technical Report, Version 2.1}, + url = {https://software.intel.com/content/www/us/en/develop/articles/intel-digital-random-number-generator-drng-software-implementation-guide.html}, + month = {October}, + year = {2018} +} + +@InProceedings{ MoSuEi:20, + author = {Daniel Moghimi and Berk Sunar and Thomas Eisenbarth and + Nadia Heninger}, + title = {{TPM}-{FAIL}: {TPM} meets Timing and Lattice Attacks}, + booktitle = {29th {USENIX} Security Symposium ({USENIX} Security 20)}, + url = {https://www.usenix.org/conference/usenixsecurity20/presentation/moghimi-tpm}, + pages = {To appear}, + publisher = {{USENIX} Association}, + month = {August}, + year = {2020} +} + +@Misc{ Mu20, + author = {Stephan M\"uller}, + title = {Documentation and Analysis of the Linux Random Number + Generator, Version 3.6}, + howpublished = {Prepared for BSI by atsec information security GmbH}, + url = {https://www.bsi.bund.de/SharedDocs/Downloads/EN/BSI/Publications/Studies/LinuxRNG/LinuxRNG_EN.pdf}, + month = {April}, + year = {2020} +} + +@Misc{ NC20, + author = {NCSC}, + title = {Quantum security technologies}, + howpublished = {White paper, Version 1.0. National Cyber Security Centre + (UK).}, + url = {https://www.ncsc.gov.uk/whitepaper/quantum-security-technologies}, + month = {March}, + year = {2020} +} + +@Misc{ NI16, + author = {{NIST}}, + title = {Submission Requirements and Evaluation Criteria for the + Post-Quantum Cryptography Standardization Process}, + howpublished = {Official Call for Proposals, National Institute for + Standards and Technology}, + url = {http://csrc.nist.gov/groups/ST/post-quantum-crypto/documents/call-for-proposals-final-dec-2016.pdf}, + month = {December}, + year = 2016 +} + +@Misc{ NI19, + author = {{NIST}}, + title = {Security Requirements for Cryptographic Modules}, + howpublished = {Federal Information Processing Standards Publication FIPS + 140-3}, + url = {https://doi.org/10.6028/NIST.FIPS.140-3}, + month = {March}, + year = {2019} +} + +@Misc{ NICC21, + author = {{NIST} and {CCCS}}, + title = {Implementation Guidance for {FIPS} 140-3 and the + Cryptographic Module Validation Program}, + howpublished = {CMVP}, + url = {https://csrc.nist.gov/CSRC/media/Projects/cryptographic-module-validation-program/documents/fips%20140-3/FIPS%20140-3%20IG.pdf}, + month = {May}, + year = {2021} +} + +@Misc{ NS15, + author = {{NSA}/{CSS}}, + title = {Commercial National Security Algorithm Suite}, + url = {https://apps.nsa.gov/iaarchive/programs/iad-initiatives/cnsa-suite.cfm}, + month = {August}, + year = 2015 +} + +@InCollection{ Ne51, + title = {Various Techniques Used in Connection with Random Digits}, + author = {von Neumann, John}, + booktitle = {Monte Carlo Method}, + editor = {Householder, A.~S. and Forsythe, G.~E. and Germond, + H.~H.}, + series = {National Bureau of Standards Applied Mathematics Series}, + volume = {12}, + chapter = {13}, + pages = {36--38}, + publisher = {US Government Printing Office}, + address = {Washington, DC}, + url = {https://mcnp.lanl.gov/pdf_files/nbs_vonneumann.pdf}, + year = {1951} +} + +@Misc{ Ra20, + author = {Rambus}, + title = {TRNG-IP-76 / EIP-76 Family of FIPS Approved True Random + Generators}, + howpublished = {Commercial Crypto IP. Formerly (2017) available from + Inside Secure.}, + url = {https://www.rambus.com/security/crypto-accelerator-hardware-cores/basic-crypto-blocks/trng-ip-76/}, + year = {2020} +} + +@InProceedings{ RaMiRa:21, + author = {Hany Ragab and Alyssa Milburn and Kaveh Razavi and Herbert + Bos and Cristiano Giuffrida}, + title = {CrossTalk : Speculative Data Leaks Across Cores Are Real}, + booktitle = {IEEE Symposium on Security \& Privacy 2021}, + url = {https://download.vusec.net/papers/crosstalk_sp21.pdf}, + pages = {To appear}, + publisher = {IEEE}, + month = {May}, + year = {2021} +} + +@Article{ Ri44, + author = {Stephen O. Rice}, + title = {Mathematical analysis of random noise (Parts I-II)}, + journal = {The Bell System Technical Journal}, + volume = {23}, + number = {3}, + pages = {282--332}, + doi = {10.1002/j.1538-7305.1944.tb00874.x}, + month = {July}, + year = {1944} +} + +@Article{ Ri45, + author = {Stephen O. Rice}, + title = {Mathematical analysis of random noise (Parts III-IV))}, + journal = {The Bell System Technical Journal}, + volume = {24}, + number = {1}, + pages = {46--156}, + doi = {10.1002/j.1538-7305.1945.tb00453.x}, + month = {January}, + year = {1945} +} + +@Misc{ RuSoNe:10, + author = {Andrew Rukhin and Juan Soto and James Nechvatal and Miles + Smid and Elaine Barker and Stefan Leigh and Mark Levenson + and Mark Vangel and David Banks and Alan Heckert and + JamesDray and San Vo}, + title = {A Statistical Test Suite for Random and Pseudorandom + Number Generators for Cryptographic Applications}, + doi = {10.6028/NIST.SP.800-22r1a}, + month = {April}, + year = {2010} +} + +@Misc{ Sa19, + author = {Jim Salter}, + title = {How a months-old {AMD} microcode bug destroyed my + weekend}, + howpublished = {Ars Technica}, + url = {https://arstechnica.com/gadgets/2019/10/how-a-months-old-amd-microcode-bug-destroyed-my-weekend/}, + month = {October}, + year = {2019} +} + +@InProceedings{ Sa20, + author = {Markku-Juhani O. Saarinen}, + title = {A Lightweight ISA Extension for {AES} and {SM4}}, + booktitle = {First International Workshop on Secure RISC-V Architecture + Design Exploration (SECRISC-V'20)}, + url = {https://arxiv.org/abs/2002.07041}, + publisher = {IEEE}, + month = {August}, + year = {2020} +} + + +@InProceedings{ SaNeMa20, + author = {Markku-Juhani O. Saarinen and G. Richard Newell and Ben + Marshall}, + title = {Building a Modern {TRNG}: An Entropy Source Interface for + {RISC}-{V}}, + booktitle = {4th Workshop on Attacks and Solutions in Hardware Security + (ASHES’20), November 13, 2020, Virtual Event, USA.}, + doi = {10.1145/3411504.3421212}, + publisher = {ACM}, + pages = {93--102}, + month = {November}, + year = 2020 +} + +@Misc{ Sa21, + author = {Markku-Juhani O. Saarinen}, + title = {On Entropy and Bit Patterns of Ring Oscillator Jitter}, + url = {https://arxiv.org/abs/2102.02196}, + howpublished = {Preprint}, + month = {February}, + year = 2021 +} + +@Misc{ SaNeMa21, + author = {Markku-Juhani O. Saarinen and G. Richard Newell and Ben + Marshall}, + title = {Development of The {RISC}-{V} Entropy Source Interface}, + howpublished = {{IACR} ePrint 2020/866}, + url = {https://eprint.iacr.org/2029/866}, + publisher = {Submitted For Publication}, + month = {June}, + year = 2021 +} + +@Misc{ Sc99, + author = {Werner Schindler}, + title = {Functionality classes and evaluation methodology for + deterministic random number generators}, + howpublished = {AIS 20, Version 2.0, English Translation, BSI}, + publisher = {BSI}, + url = {https://www.bsi.bund.de/SharedDocs/Downloads/DE/BSI/Zertifizierung/Interpretationen/AIS_20_Functionality_Classes_Evaluation_Methodology_DRNG_e.html}, + month = {December}, + year = {1999} +} + +@InProceedings{ Sh94, + author = {Peter W. Shor}, + title = {Algorithms for quantum computation: Discrete logarithms + and factoring}, + booktitle = {35th Annual Symposium on Foundations of Computer Science, + Santa Fe, New Mexico, USA, 20-22 November 1994}, + pages = {124--134}, + publisher = {IEEE}, + doi = {10.1109/SFCS.1994.365700}, + url = {https://arxiv.org/abs/quant-ph/9508027}, + year = 1994 +} + +@Misc{ TG20, + author = {{RISC-V} {Crypto} {TG}}, + title = {RISC-V Cryptography Extensions}, + url = {https://github.com/riscv/riscv-crypto}, + howpublished = {Editor's location -- to be integrated with main + specifications}, + year = {2020} +} + +@Misc{TuBaKe:18, + author = {Meltem S\"onmez Turan and Elaine Barker and John Kelsey and + Kerry A. McKay and Mary L. Baish and Mike Boyle}, + title = {Recommendation for the Entropy Sources Used for Random Bit + Generation}, + howpublished = {NIST Special Publication SP 800-90B}, + doi = {10.6028/NIST.SP.800-90B}, + month = {January}, + year = {2018} +} + +@InProceedings{ VaDr10, + author = {Michal Varchola and Milos Drutarovsk{\'{y}}}, + title = {New High Entropy Element for {FPGA} Based True Random + Number Generators}, + booktitle = {Cryptographic Hardware and Embedded Systems, {CHES} 2010, + 12th International Workshop, Santa Barbara, CA, USA, August + 17-20, 2010. Proceedings}, + pages = {351--365}, + crossref = {_MaSt10}, + doi = {10.1007/978-3-642-15031-9\_24}, + year = {2010} +} + +@InProceedings{ VaFiAu:10, + author = {Boyan Valtchanov and Viktor Fischer and Alain Aubert and + Florent Bernard}, + title = {Characterization of randomness sources in ring + oscillator-based true random number generators in FPGAs}, + booktitle = {13th {IEEE} International Symposium on Design and + Diagnostics of Electronic Circuits and Systems, {DDECS} + 2010, Vienna, Austria, April 14-16, 2010}, + pages = {48--53}, + crossref = {_GrKoSt:10}, + doi = {10.1109/DDECS.2010.5491819}, + year = {2010} +} + +@Proceedings{ _CaIs20, + editor = {Anne Canteaut and Yuval Ishai}, + title = {Advances in Cryptology - {EUROCRYPT} 2020 - 39th Annual + International Conference on the Theory and Applications of + Cryptographic Techniques, Zagreb, Croatia, May 10-14, 2020, + Proceedings, Part {II}}, + series = {Lecture Notes in Computer Science}, + volume = {12106}, + publisher = {Springer}, + doi = {10.1007/978-3-030-45724-2}, + isbn = {978-3-030-45723-5}, + year = {2020} +} + +@Proceedings{ _ClGa09, + editor = {Christophe Clavier and Kris Gaj}, + title = {Cryptographic Hardware and Embedded Systems - {CHES} 2009, + 11th International Workshop, Lausanne, Switzerland, + September 6-9, 2009, Proceedings}, + series = {Lecture Notes in Computer Science}, + volume = {5747}, + publisher = {Springer}, + doi = {10.1007/978-3-642-04138-9}, + isbn = {978-3-642-04137-2}, + year = {2009} +} + +@Proceedings{ _GrKoSt:10, + editor = {Elena Gramatov{\'{a}} and Zdenek Kot{\'{a}}sek and Andreas + Steininger and Heinrich Theodor Vierhaus and Horst + Zimmermann}, + title = {13th {IEEE} International Symposium on Design and + Diagnostics of Electronic Circuits and Systems, {DDECS} + 2010, Vienna, Austria, April 14-16, 2010}, + publisher = {{IEEE} Computer Society}, + url = {https://ieeexplore.ieee.org/xpl/conhome/5484099/proceeding}, + isbn = {978-1-4244-6612-2}, + year = {2010} +} + +@Proceedings{ _MaSt10, + editor = {Stefan Mangard and Fran{\c{c}}ois{-}Xavier Standaert}, + title = {Cryptographic Hardware and Embedded Systems, {CHES} 2010, + 12th International Workshop, Santa Barbara, CA, USA, August + 17-20, 2010. Proceedings}, + series = {Lecture Notes in Computer Science}, + volume = {6225}, + publisher = {Springer}, + doi = {10.1007/978-3-642-15031-9}, + isbn = {978-3-642-15030-2}, + year = {2010} +} + +@Proceedings{ _Ny08, + editor = {Kaisa Nyberg}, + title = {Fast Software Encryption, 15th International Workshop, + {FSE} 2008, Lausanne, Switzerland, February 10-13, 2008, + Revised Selected Papers}, + series = {Lecture Notes in Computer Science}, + volume = {5086}, + publisher = {Springer}, + doi = {10.1007/978-3-540-71039-4}, + isbn = {978-3-540-71038-7}, + year = {2008} +} + +@Proceedings{ _SaCa12, + editor = {Reihaneh Safavi{-}Naini and Ran Canetti}, + title = {Advances in Cryptology - {CRYPTO} 2012 - 32nd Annual + Cryptology Conference, Santa Barbara, CA, USA, August + 19-23, 2012. Proceedings}, + series = {Lecture Notes in Computer Science}, + volume = {7417}, + publisher = {Springer}, + doi = {10.1007/978-3-642-32009-5}, + isbn = {978-3-642-32008-8}, + year = {2012} +} + +@Proceedings{ _Ta16, + editor = {Tsuyoshi Takagi}, + title = {Post-Quantum Cryptography - 7th International Workshop, + PQCrypto 2016, Fukuoka, Japan, February 24-26, 2016, + Proceedings}, + series = {Lecture Notes in Computer Science}, + volume = {9606}, + publisher = {Springer}, + doi = {10.1007/978-3-319-29360-8}, + isbn = {978-3-319-29359-2}, + year = {2016} +} + +@Book{ _WaAs19, + editor = {Andrew Waterman and Krste Asanovi\'c}, + title = {The {RISC}-{V} Instruction Set Manual, Volume I: + User-Level {ISA}}, + note = {Document Version 20191213}, + publisher = {RISC-V Foundation}, + url = {https://riscv.org/specifications/}, + month = {December}, + year = 2019 +} + +@Book{ _WaAs19A, + editor = {Andrew Waterman and Krste Asanovi\'c}, + title = {The {RISC}-{V} Instruction Set Manual, Volume II: + Privileged Architecture}, + note = {Document Version 20190608-Priv-MSU-Ratified}, + publisher = {RISC-V Foundation}, + url = {https://riscv.org/specifications/}, + month = {June}, + year = 2019 +} + +@Proceedings{ _WeKaKr:16, + editor = {Edgar R. Weippl and Stefan Katzenbeisser and Christopher + Kruegel and Andrew C. Myers and Shai Halevi}, + title = {Proceedings of the 2016 {ACM} {SIGSAC} Conference on + Computer and Communications Security, Vienna, Austria, + October 24-28, 2016}, + publisher = {{ACM}}, + url = {http://dl.acm.org/citation.cfm?id=2976749}, + isbn = {978-1-4503-4139-4}, + year = {2016} +} diff --git a/src/resources/themes/riscv-spec.yml b/src/resources/themes/riscv-spec.yml index 5cb07c9..e8332fc 100644 --- a/src/resources/themes/riscv-spec.yml +++ b/src/resources/themes/riscv-spec.yml @@ -250,6 +250,7 @@ figure: align: center table: background_color: $page_background_color + font-size: 9 #head_background_color: #2596be #head_font_color: $base_font_color head_font_style: bold diff --git a/src/riscv-privileged.adoc b/src/riscv-privileged.adoc index bddef4f..7e6665c 100644 --- a/src/riscv-privileged.adoc +++ b/src/riscv-privileged.adoc @@ -51,17 +51,22 @@ endif::[] :hide-uri-scheme: :stem: latexmath :footnote: +:le: ≤ +:ge: ≥ +:ne: ≠ +:approx: ≈ +:inf: ∞ _Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Krste Asanović, Peter Ashenden, Rimas Avižienis, Jacob Bachmeyer, Allen J. Baum, Jonathan Behrens, Paolo Bonzini, Ruslan Bukin, Christopher Celio, Chuanhua Chang, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte -Dalrymple, Paul Donahue, Greg Favor, Dennis Ferguson, Marc Gauthier, Andy Glew, -Gary Guo, Mike Frysinger, John Hauser, David Horner, Olof -Johansson, David Kruckemyer, Yunsup Lee, Daniel Lustig, Andrew Lutomirski, Prashanth Mundkur, +Dalrymple, Paul Donahue, Ken Dockser, Aaron Durbin, Greg Favor, Dennis Ferguson, Marc Gauthier, Andy Glew, +Gary Guo, Mike Frysinger, John Hauser, David Horner, John Ingalls, Olof +Johansson, Earl Killian, David Kruckemyer, Yunsup Lee, Daniel Lustig, Andrew Lutomirski, Prashanth Mundkur, Jonathan Neuschäfer, Rishiyur Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Dmitri -Pavlov, Kade Phillips, Josh Scheid, Colin Schmidt, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray +Pavlov, Kade Phillips, Josh Scheid, Colin Schmidt, Ved Shanbhogue, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker, Megan Wachs, Steve Wallach, Andrew Waterman, Claire Wolf, and Reinoud Zandijk.._ @@ -89,6 +94,8 @@ include::rnmi.adoc[] //supervisor.tex include::supervisor.adoc[] include::sscofpmt.adoc[] +include::smcntrpmf.adoc[] +include::svadu.adoc[] //hypervisor.tex include::hypervisor.adoc[] include::sstc.adoc[] diff --git a/src/riscv-unprivileged.adoc b/src/riscv-unprivileged.adoc index 839967f..6d7864d 100644 --- a/src/riscv-unprivileged.adoc +++ b/src/riscv-unprivileged.adoc @@ -32,7 +32,7 @@ :listing-caption: Example :sectnums: :toc: left -:toclevels: 4 +:toclevels: 5 :source-highlighter: pygments ifdef::backend-pdf[] :source-highlighter: rouge @@ -47,24 +47,32 @@ endif::[] :hide-uri-scheme: :stem: latexmath :footnote: +:le: ≤ +:ge: ≥ +:ne: ≠ +:approx: ≈ +:inf: ∞ :csrname: envcfg _Contributors to all versions of the spec in alphabetical order (please contact editors to suggest -corrections): Arvind, - Krste Asanović, - Rimas Avižienis, +corrections): Derek Atkins, +Arvind, +Krste Asanović, +Rimas Avižienis, Jacob Bachmeyer, Christopher F. Batten, Allen J. Baum, Abel Bernabeu, Alex Bradbury, Scott Beamer, +Hans Boehm, Preston Briggs, Christopher Celio, Chuanhua Chang, David Chisnall, Paul Clayton, Palmer Dabbelt, +L Peter Deutsch, Ken Dockser, Paul Donahue, Aaron Durbin, @@ -76,6 +84,7 @@ Stefan Freudenberger, Marc Gauthier, Andy Glew, Jan Gray, +Gianluca Guida, Michael Hamburg, John Hauser, John Ingalls, @@ -92,16 +101,20 @@ Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget, +Ben Marshall, Margaret Martonosi, Phil McCoy, +Nathan Menhorn, Christoph Müllner, Joseph Myers, Vijayanand Nagarajan, Rishiyur Nikhil, Jonas Oberhauser, Stefan O'Rear, +Markku-Juhani O. Saarinen, Albert Ou, John Ousterhout, +Daniel Page, David Patterson, Christopher Pulte, Jose Renau, @@ -110,6 +123,7 @@ Colin Schmidt, Peter Sewell, Susmit Sarkar, Ved Shanbhogue, +Brent Spinney, Brendan Sweeney, Michael Taylor, Wesley Terpstra, @@ -125,6 +139,7 @@ Andrew Waterman, Robert Watson, David Weaver, Derek Williams, +Claire Wolf, Andrew Wright, Reinoud Zandijk, and Sizhuo Zhang._ @@ -192,12 +207,13 @@ include::zfa.adoc[] //zfa.tex include::ztso-st-ext.adoc[] //ztso.tex +include::scalar-crypto.adoc[] +include::vector-crypto.adoc[] +include::zacas.adoc[] include::zicond.adoc[] include::cmo.adoc[] include::zawrs.adoc[] - include::zc.adoc[] - include::rv-32-64g.adoc[] //gmaps.tex include::extending.adoc[] @@ -210,6 +226,11 @@ include::mm-eplan.adoc[] //memory.tex include::mm-formal.adoc[] //end of memory.tex, memory-model-alloy.tex, memory-model-herd.tex +//Appendices for Vector +include::vector-examples.adoc[] +include::calling-convention.adoc[] +//include::fraclmul.adoc[] +//End of Vector appendices include::index.adoc[] // this is generated generated from index markers. include::bibliography.adoc[] diff --git a/src/rnmi.adoc b/src/rnmi.adoc index 705fb7d..f505f56 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -1,9 +1,9 @@ [[rnmi]] -== "Smrnmi" Standard Extension for Resumable Non-Maskable Interrupts, Version 0.4 +== "Smrnmi" Standard Extension for Resumable Non-Maskable Interrupts, Version 0.5 [WARNING] ==== -*Warning! This draft specification may change before being accepted as +*Warning! This frozen specification may change before being accepted as standard by RISC-V International.* ==== diff --git a/src/scalar-crypto.adoc b/src/scalar-crypto.adoc new file mode 100644 index 0000000..a486622 --- /dev/null +++ b/src/scalar-crypto.adoc @@ -0,0 +1,5776 @@ +== Cryptography Extensions Volume I: Scalar & Entropy Source Instructions, Version 1.0.1 + +=== Changelog + +[cols="1,5"] +|=== +| Version | Changes + +| `v1.0.1` +| Fix typos to show that + `c.srli`, `c.srai`, and `c.slli` are Zkt instructions in RV64. + +| `v1.0.0` +| Initial Release +|=== + +[[crypto_scalar_introduction]] +=== Introduction + +This document describes the _scalar_ cryptography +extension for RISC-V. +All instructions described herein use the general-purpose `X` +registers, and obey the 2-read-1-write register access constraint. +These instructions are designed to be lightweight and suitable +for `32` and `64` bit base architectures; from embedded IoT class +cores to large, application class cores which do not implement a +vector unit. + +This document also describes the architectural interface to an +Entropy Source, which can be used to generate cryptographic secrets. +This is found in <<crypto_scalar_es>>. + +It also contains a mechanism allowing core implementers to provide +_"Constant Time Execution"_ guarantees in <<crypto_scalar_zkt>>. + +A companion document _Volume II: Vector Instructions_, describes +instruction proposals which build on the RISC-V Vector Extension. +The Vector Cryptography extension is currently a work in progress +waiting for the base Vector extension to stabilise. +We expect to pick up this work in earnest in Q4-2021 or Q1-2022. + +[[crypto_scalar_audience]] +==== Intended Audience + +Cryptography is a specialised subject, requiring people with many different +backgrounds to cooperate in its secure and efficient implementation. +Where possible, we have written this specification to be understandable by +all, though we recognise that the motivations and references to +algorithms or other specifications and standards may be unfamiliar to those +who are not domain experts. + +This specification anticipates being read and acted on by various people +with different backgrounds. +We have tried to capture these backgrounds +here, with a brief explanation of what we expect them to know, and how +it relates to the specification. +We hope this aids people's understanding of which aspects of the specification +are particularly relevant to them, and which they may (safely!) ignore or +pass to a colleague. + +Cryptographers and cryptographic software developers:: +These are the people we expect to write code using the instructions +in this specification. +They should understand fairly obviously the motivations for the +instructions we include, and be familiar with most of the algorithms +and outside standards to which we refer. +We expect the sections on constant time execution +(<<crypto_scalar_zkt>>) +and the entropy source +(<<crypto_scalar_es>>) +to be chiefly understood with their help. + +Computer architects:: +We do not expect architects to have a cryptography background. +We nonetheless expect architects to be able to examine our instructions +for implementation issues, understand how the instructions will be used +in context, and advise on how best to fit the functionality the +cryptographers want to the ISA interface. + +Digital design engineers & micro-architects:: +These are the people who will implement the specification inside a +core. Again, no cryptography expertise is assumed, but we expect them to +interpret the specification and anticipate any hardware implementation +issues, e.g., where high-frequency design considerations apply, or where +latency/area tradeoffs exist etc. +In particular, they should be aware of the literature around efficiently +implementing AES and SM4 SBoxes in hardware. + +Verification engineers:: +Responsible for ensuring the correct implementation of the extension +in hardware. +No cryptography background is assumed. +We expect them to identify interesting test cases from the +specification. An understanding of their real-world usage will help with this. +We do not expect verification engineers in this sense to be experts +in entropy source design or certification, since this is a very +specialised area. +We do expect them however to identify all of the _architectural_ +test cases around the entropy source interface. + +These are by no means the only people concerned with the specification, +but they are the ones we considered most while writing it. + +[[crypto_scalar_sail_specifications]] +==== Sail Specifications + +RISC-V maintains a +link:https://github.com/riscv/sail-riscv[formal model] +of the ISA specification, +implemented in the Sail ISA specification language +cite:[sail]. +Note that _Sail_ refers to the specification language itself, +and that there is a _model of RISC-V_, written using Sail. +It is not correct to refer to "the Sail model". +This is ambiguous, given there are many models of different ISAs implemented +using Sail. We refer to the Sail implementation of RISC-V as +"the RISC-V Sail model". + +The Cryptography extension uses inline Sail code snippets from the +actual model to give canonical descriptions of instruction +functionality. +Each instruction is accompanied by its expression in Sail, and includes +calls to supporting functions which are too verbose to include directly +in the specification. +This supporting code is listed in +<<crypto_scalar_appx_sail>>. +The +link:https://github.com/rems-project/sail/blob/sail2/manual.pdf[Sail Manual] +is recommended reading in order to best understand the code snippets. + +Note that this document contains only a subset of the formal model: refer to +the formal model Github +link:https://github.com/riscv/sail-riscv[repository] +for the complete model. + +[[crypto_scalar_policies]] +==== Policies + +In creating this proposal, we tried to adhere to the following +policies: + +* Where there is a choice between: + . supporting diverse implementation strategies for an algorithm + or + . supporting a single implementation style which is more performant / + less expensive; + the crypto extension will pick the more constrained but performant + option. + This fits a common pattern in other parts of the RISC-V specification, + where recommended (but not required) instruction sequences for performing + particular tasks are given as an example, such that both hardware and + software implementers can optimise for only a single use-case. + +* The extension will be designed to support _existing_ standardised + cryptographic constructs well. + It will not try to support proposed standards, or cryptographic + constructs which exist only in academia. + Cryptographic standards which are settled upon concurrently with or after + the RISC-V cryptographic extension standardisation will be dealt with + by future additions to, or versions of, the RISC-V cryptographic + standard extension. It is anticipated that the NIST Lightweight + Cryptography contest and the NIST Post-Quantum Cryptography contest + may be dealt with this way, depending on timescales. + +* Historically, there has been some discussion + cite:[LSYRR:04] + on how newly supported operations in general-purpose computing might + enable new bases for cryptographic algorithms. + The standard will not try to anticipate new useful low-level + operations which _may_ be useful as building blocks for + future cryptographic constructs. + +* Regarding side-channel countermeasures: + Where relevant, proposed instructions must aim to remove the + possibility of any timing side-channels. + For side-channels based on power or electro-magnetic (EM) measurements, + the extension will not aim to support countermeasures which are + implemented above the ISA abstraction layer. + Recommendations will be given where relevant on how micro-architectures + can implement instructions in a power/EM side-channel resistant way. + +[[crypto_scalar_extensions]] +=== Extensions Overview + +The group of extensions introduced by the Scalar Cryptography Instruction Set +Extension is listed here. + +Detection of individual cryptography extensions uses the +unified software-based RISC-V discovery method. + +[NOTE] +==== +At the time of writing, these discovery mechanisms are still a work in +progress. +==== + +.A note on extension rationale +[NOTE, caption="SH"] +==== +Specialist encryption and decryption instructions are separated into different +functional groups because some use cases (e.g., Galois/Counter +Mode in TLS 1.3) do not require decryption functionality. + +The NIST and ShangMi algorithms suites are separated because their +usefulness is heavily dependent on the countries a device is expected to +operate in. NIST ciphers are a part of most standardised internet +protocols, while ShangMi ciphers are required for use in China. +==== + +[[zbkb,Zbkb]] +==== `Zbkb` - Bitmanip instructions for Cryptography + +These are a subset of the Bitmanipulation Extension `Zbb` which are +particularly useful for Cryptography. + +NOTE: Some of these instructions are defined in the first Bitmanip +ratification package, and some are not ( +<<insns-pack,pack>>, +<<insns-packh,packh>>, +<<insns-packw,packw>>, +<<insns-brev8,brev8>>, +<<insns-zip,zip>>, +<<insns-unzip,unzip>>). +All of the instructions in <<zbkb>> have their complete specification included +in this document, including those _not_ present in the initial +Bitmanip ratification package. +This is to make the present specification complete as a standalone document. +Inevitably there might be small divergences between the Bitmanip and +Scalar Cryptography specification documents as they move at different +paces. +When this happens, assume that the Bitmanip specification has the +most up-to-date version of Bitmanip instructions. +This is an unfortunate but necessary stop-gap while Scalar Cryptography +and Bitmanip are being rapidly iterated on prior to public review. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | ror | <<insns-ror>> +| ✓ | ✓ | rol | <<insns-rol>> +| ✓ | ✓ | rori | <<insns-rori>> +| | ✓ | rorw | <<insns-rorw>> +| | ✓ | rolw | <<insns-rolw>> +| | ✓ | roriw | <<insns-roriw>> +| ✓ | ✓ | andn | <<insns-andn>> +| ✓ | ✓ | orn | <<insns-orn>> +| ✓ | ✓ | xnor | <<insns-xnor>> +| ✓ | ✓ | pack | <<insns-pack>> +| ✓ | ✓ | packh | <<insns-packh>> +| | ✓ | packw | <<insns-packw>> +| ✓ | ✓ | brev8 | <<insns-brev8>> +| ✓ | ✓ | rev8 | <<insns-rev8>> +| ✓ | | zip | <<insns-zip>> +| ✓ | | unzip | <<insns-unzip>> +|=== + +[[zbkc,Zbkc]] +==== `Zbkc` - Carry-less multiply instructions + +Constant time carry-less multiply for Galois/Counter Mode. +These are separated from the <<zbkb>> because they +have a considerable implementation overhead which cannot be amortised +across other instructions. + +NOTE: These instructions are defined in the first Bitmanip +ratification package for the `Zbc` extension. +All of the instructions in <<zbkc>> have their complete specification included +in this document, including those _not_ present in the initial +Bitmanip ratification package. +This is to make the present specification complete as a standalone document. +Inevitably there might be small divergences between the Bitmanip and +Scalar Cryptography specification documents as they move at different +paces. +When this happens, assume that the Bitmanip specification has the +most up-to-date version of Bitmanip instructions. +This is an unfortunate but necessary stop-gap while Scalar Cryptography +and Bitmanip are being rapidly iterated on prior to public review. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | clmul | <<insns-clmul>> +| ✓ | ✓ | clmulh | <<insns-clmulh>> +|=== + +[[zbkx,Zbkx]] +==== `Zbkx` - Crossbar permutation instructions + +These instructions are useful for implementing SBoxes in constant time, and +potentially with DPA protections. +These are separated from the <<zbkb>> because they +have an implementation overhead which cannot be amortised +across other instructions. + +NOTE: All of these instructions are missing from the first Bitmanip +ratification package. +Hence, all of the instructions in <<zbkx>> have their complete specification +included in this document. +This is to make the present specification complete as a standalone document. +Inevitably there might be small divergences between the Bitmanip and +Scalar Cryptography specification documents as they move at different +paces. +When this happens, assume that the Bitmanip specification has the +most up-to-date version of Bitmanip instructions. +This is an unfortunate but necessary stop-gap while Scalar Cryptography +and Bitmanip are being rapidly iterated on prior to public review. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | xperm8 | <<insns-xperm8>> +| ✓ | ✓ | xperm4 | <<insns-xperm4>> +|=== + +[[zknd,Zknd]] +==== `Zknd` - NIST Suite: AES Decryption + +Instructions for accelerating the decryption and key-schedule functions of +the AES block cipher. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | | aes32dsi | <<insns-aes32dsi>> +| ✓ | | aes32dsmi | <<insns-aes32dsmi>> +| | ✓ | aes64ds | <<insns-aes64ds>> +| | ✓ | aes64dsm | <<insns-aes64dsm>> +| | ✓ | aes64im | <<insns-aes64im>> +| | ✓ | aes64ks1i | <<insns-aes64ks1i>> +| | ✓ | aes64ks2 | <<insns-aes64ks2>> +|=== + +NOTE: The <<insns-aes64ks1i>> and <<insns-aes64ks2>> instructions are +present in both the <<zknd>> and <<zkne>> extensions. + +[[zkne,Zkne]] +==== `Zkne` - NIST Suite: AES Encryption + +Instructions for accelerating the encryption and key-schedule functions of +the AES block cipher. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | | aes32esi | <<insns-aes32esi>> +| ✓ | | aes32esmi | <<insns-aes32esmi>> +| | ✓ | aes64es | <<insns-aes64es>> +| | ✓ | aes64esm | <<insns-aes64esm>> +| | ✓ | aes64ks1i | <<insns-aes64ks1i>> +| | ✓ | aes64ks2 | <<insns-aes64ks2>> +|=== + +NOTE: The +<<insns-aes64ks1i,`aes64ks1i`>> +and +<<insns-aes64ks2,`aes64ks2`>> +instructions are present in both the <<zknd>> and <<zkne>> extensions. + +[[zknh,Zknh]] +==== `Zknh` - NIST Suite: Hash Function Instructions + +Instructions for accelerating the SHA2 family of cryptographic hash functions, +as specified in cite:[nist:fips:180:4]. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | sha256sig0 | <<insns-sha256sig0>> +| ✓ | ✓ | sha256sig1 | <<insns-sha256sig1>> +| ✓ | ✓ | sha256sum0 | <<insns-sha256sum0>> +| ✓ | ✓ | sha256sum1 | <<insns-sha256sum1>> +| ✓ | | sha512sig0h | <<insns-sha512sig0h>> +| ✓ | | sha512sig0l | <<insns-sha512sig0l>> +| ✓ | | sha512sig1h | <<insns-sha512sig1h>> +| ✓ | | sha512sig1l | <<insns-sha512sig1l>> +| ✓ | | sha512sum0r | <<insns-sha512sum0r>> +| ✓ | | sha512sum1r | <<insns-sha512sum1r>> +| | ✓ | sha512sig0 | <<insns-sha512sig0>> +| | ✓ | sha512sig1 | <<insns-sha512sig1>> +| | ✓ | sha512sum0 | <<insns-sha512sum0>> +| | ✓ | sha512sum1 | <<insns-sha512sum1>> +|=== + +[[zksed,Zksed]] +==== `Zksed` - ShangMi Suite: SM4 Block Cipher Instructions + +Instructions for accelerating the SM4 Block Cipher. +Note that unlike AES, this cipher uses the same core operation for +encryption and decryption, hence there is only one +extension for it. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | sm4ed | <<insns-sm4ed>> +| ✓ | ✓ | sm4ks | <<insns-sm4ks>> +|=== + +[[zksh,Zksh]] +==== `Zksh` - ShangMi Suite: SM3 Hash Function Instructions + +Instructions for accelerating the SM3 hash function. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | sm3p0 | <<insns-sm3p0>> +| ✓ | ✓ | sm3p1 | <<insns-sm3p1>> +|=== + +[[zkr,Zkr]] +==== `Zkr` - Entropy Source Extension + +The entropy source extension defines the `seed` CSR at address `0x015`. +This CSR provides up to 16 physical `entropy` bits that can be used to +seed cryptographic random bit generators. + +See <<crypto_scalar_es>> for the normative specification and access control +notes. <<crypto_scalar_appx_es>> contains design rationale and further +recommendations to implementers. + +[[zkn,Zkn]] +==== `Zkn` - NIST Algorithm Suite + +This extension is shorthand for the following set of other extensions: + +[%header,cols="^1,4"] +|=== +|Included Extension +|Description + +| <<zbkb>> | Bitmanipulation instructions for cryptography. +| <<zbkc>> | Carry-less multiply instructions. +| <<zbkx>> | Cross-bar Permutation instructions. +| <<zkne>> | AES encryption instructions. +| <<zknd>> | AES decryption instructions. +| <<zknh>> | SHA2 hash function instructions. +|=== + +A core which implements `Zkn` must implement all of the above extensions. + +[[zks,Zks]] +==== `Zks` - ShangMi Algorithm Suite + +This extension is shorthand for the following set of other extensions: + +[%header,cols="^1,4"] +|=== +|Included Extension +|Description + +| <<zbkb>> | Bitmanipulation instructions for cryptography. +| <<zbkc>> | Carry-less multiply instructions. +| <<zbkx>> | Cross-bar Permutation instructions. +| <<zksed>> | SM4 block cipher instructions. +| <<zksh>> | SM3 hash function instructions. +|=== + +A core which implements `Zks` must implement all of the above extensions. + +[[zk,Zk]] +==== `Zk` - Standard scalar cryptography extension + +This extension is shorthand for the following set of other extensions: + +[%header,cols="^1,4"] +|=== +|Included Extension +|Description + +| <<zkn>> | NIST Algorithm suite extension. +| <<zkr>> | Entropy Source extension. +| <<crypto_scalar_zkt,Zkt>> | Data independent execution latency extension. +|=== + +A core which implements `Zk` must implement all of the above extensions. + +==== `Zkt` - Data Independent Execution Latency + +This extension allows CPU implementers to indicate to +cryptographic software developers that a subset of RISC-V instructions +are guaranteed to be implemented such that their execution latency +is independent of the data values they operate on. +A complete description of this extension is found in +<<crypto_scalar_zkt>>. + +// ------------------------------------------------------------ + +[[crypto_scalar_insns, reftext="Scalar Cryptography Instructions"]] +=== Instructions + +[#insns-aes32dsi, reftext="AES final round decrypt (RV32)"] +==== aes32dsi + +Synopsis:: +AES final round decryption instruction for RV32. + +Mnemonic:: +aes32dsi rd, rs1, rs2, bs + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x15}, +{bits: 2, name: 'bs'}, +]} +.... + +Description:: +This instruction sources a single byte from `rs2` according to `bs`. +To this it applies the inverse AES SBox operation, and XOR's the result with +`rs1`. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (AES32DSI (bs,rs2,rs1,rd)) = { + let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */ + let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; /* SBox Input */ + let so : bits(32) = 0x000000 @ aes_sbox_inv(si); + let result : bits(32) = X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); + X(rd) = EXTS(result); RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknd>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes32dsmi, reftext="AES middle round decrypt (RV32)"] +==== aes32dsmi + +Synopsis:: +AES middle round decryption instruction for RV32. + +Mnemonic:: +aes32dsmi rd, rs1, rs2, bs + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x17}, +{bits: 2, name: 'bs'}, +]} +.... + +Description:: +This instruction sources a single byte from `rs2` according to `bs`. +To this it applies the inverse AES SBox operation, and a partial inverse +MixColumn, before XOR'ing the result with `rs1`. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (AES32DSMI (bs,rs2,rs1,rd)) = { + let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */ + let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; /* SBox Input */ + let so : bits( 8) = aes_sbox_inv(si); + let mixed : bits(32) = aes_mixcolumn_byte_inv(so); + let result : bits(32) = X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); + X(rd) = EXTS(result); RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknd>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes32esi, reftext="AES final round encrypt (RV32)"] +==== aes32esi + +Synopsis:: +AES final round encryption instruction for RV32. + +Mnemonic:: +aes32esi rd, rs1, rs2, bs + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x11}, +{bits: 2, name: 'bs'}, +]} +.... + +Description:: +This instruction sources a single byte from `rs2` according to `bs`. +To this it applies the forward AES SBox operation, +before XOR'ing the result with `rs1`. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (AES32ESI (bs,rs2,rs1,rd)) = { + let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */ + let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; /* SBox Input */ + let so : bits(32) = 0x000000 @ aes_sbox_fwd(si); + let result : bits(32) = X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); + X(rd) = EXTS(result); RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zkne>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes32esmi, reftext="AES middle round encrypt (RV32)"] +==== aes32esmi + +Synopsis:: +AES middle round encryption instruction for RV32. + +Mnemonic:: +aes32esmi rd, rs1, rs2, bs + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x13}, +{bits: 2, name: 'bs'}, +]} +.... + +Description:: +This instruction sources a single byte from `rs2` according to `bs`. +To this it applies the forward AES SBox operation, and a partial forward +MixColumn, before XOR'ing the result with `rs1`. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (AES32ESMI (bs,rs2,rs1,rd)) = { + let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */ + let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; /* SBox Input */ + let so : bits( 8) = aes_sbox_fwd(si); + let mixed : bits(32) = aes_mixcolumn_byte_fwd(so); + let result : bits(32) = X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); + X(rd) = EXTS(result); RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zkne>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64ds, reftext="AES decrypt final round (RV64)"] +==== aes64ds + +Synopsis:: +AES final round decryption instruction for RV64. + +Mnemonic:: +aes64ds rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x1d}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +Uses the two 64-bit source registers to represent the entire AES state, +and produces _half_ of the next round output, applying the Inverse ShiftRows +and SubBytes steps. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +.Note To Software Developers +[NOTE,caption="SH"] +==== +The following code snippet shows the final round of the AES block decryption. +`t0` and `t1` hold the current round state. +`t2` and `t3` hold the next round state. + + aes64ds t2, t0, t1 + aes64ds t3, t1, t0 + +Note the reversed register order of the second instruction. +==== + +Operation:: +[source,sail] +-- +function clause execute (AES64DS(rs2, rs1, rd)) = { + let sr : bits(64) = aes_rv64_shiftrows_inv(X(rs2)[63..0], X(rs1)[63..0]); + let wd : bits(64) = sr[63..0]; + X(rd) = aes_apply_inv_sbox_to_each_byte(wd); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknd>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64dsm, reftext="AES decrypt middle round (RV64)"] +==== aes64dsm + +Synopsis:: +AES middle round decryption instruction for RV64. + +Mnemonic:: +aes64dsm rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x1f}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +Uses the two 64-bit source registers to represent the entire AES state, +and produces _half_ of the next round output, applying the Inverse ShiftRows, +SubBytes and MixColumns steps. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +.Note To Software Developers +[NOTE,caption="SH"] +==== +The following code snippet shows one middle round of the AES block decryption. +`t0` and `t1` hold the current round state. +`t2` and `t3` hold the next round state. + + aes64dsm t2, t0, t1 + aes64dsm t3, t1, t0 + +Note the reversed register order of the second instruction. +==== + +Operation:: +[source,sail] +-- +function clause execute (AES64DSM(rs2, rs1, rd)) = { + let sr : bits(64) = aes_rv64_shiftrows_inv(X(rs2)[63..0], X(rs1)[63..0]); + let wd : bits(64) = sr[63..0]; + let sb : bits(64) = aes_apply_inv_sbox_to_each_byte(wd); + X(rd) = aes_mixcolumn_inv(sb[63..32]) @ aes_mixcolumn_inv(sb[31..0]); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknd>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64es, reftext="AES encrypt final round instruction (RV64)"] +==== aes64es + +Synopsis:: +AES final round encryption instruction for RV64. + +Mnemonic:: +aes64es rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x19}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +Uses the two 64-bit source registers to represent the entire AES state, +and produces _half_ of the next round output, applying the ShiftRows and +SubBytes steps. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +.Note To Software Developers +[NOTE,caption="SH"] +==== +The following code snippet shows the final round of the AES block encryption. +`t0` and `t1` hold the current round state. +`t2` and `t3` hold the next round state. + + aes64es t2, t0, t1 + aes64es t3, t1, t0 + +Note the reversed register order of the second instruction. +==== + +Operation:: +[source,sail] +-- +function clause execute (AES64ES(rs2, rs1, rd)) = { + let sr : bits(64) = aes_rv64_shiftrows_fwd(X(rs2)[63..0], X(rs1)[63..0]); + let wd : bits(64) = sr[63..0]; + X(rd) = aes_apply_fwd_sbox_to_each_byte(wd); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zkne>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64esm, reftext="AES encrypt middle round instruction (RV64)"] +==== aes64esm + +Synopsis:: +AES middle round encryption instruction for RV64. + +Mnemonic:: +aes64esm rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x1b}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +Uses the two 64-bit source registers to represent the entire AES state, +and produces _half_ of the next round output, applying the ShiftRows, +SubBytes and MixColumns steps. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +.Note To Software Developers +[NOTE,caption="SH"] +==== +The following code snippet shows one middle round of the AES block encryption. +`t0` and `t1` hold the current round state. +`t2` and `t3` hold the next round state. + + aes64esm t2, t0, t1 + aes64esm t3, t1, t0 + +Note the reversed register order of the second instruction. +==== + +Operation:: +[source,sail] +-- +function clause execute (AES64ESM(rs2, rs1, rd)) = { + let sr : bits(64) = aes_rv64_shiftrows_fwd(X(rs2)[63..0], X(rs1)[63..0]); + let wd : bits(64) = sr[63..0]; + let sb : bits(64) = aes_apply_fwd_sbox_to_each_byte(wd); + X(rd) = aes_mixcolumn_fwd(sb[63..32]) @ aes_mixcolumn_fwd(sb[31..0]); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zkne>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64im, reftext="AES Decrypt KeySchedule MixColumns (RV64)"] +==== aes64im + +Synopsis:: +This instruction accelerates the inverse MixColumns step of the AES +Block Cipher, and is used to aid creation of the decryption KeySchedule. + +Mnemonic:: +aes64im rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x0}, +{bits: 5, name: 0x18}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +The instruction applies the inverse MixColumns +transformation to two columns of the state array, packed into a single +64-bit register. +It is used to create the inverse cipher KeySchedule, according to +the equivalent inverse cipher construction in +cite:[nist:fips:197] (Page 23, Section 5.3.5). +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (AES64IM(rs1, rd)) = { + let w0 : bits(32) = aes_mixcolumn_inv(X(rs1)[31.. 0]); + let w1 : bits(32) = aes_mixcolumn_inv(X(rs1)[63..32]); + X(rd) = w1 @ w0; + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknd>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64ks1i, reftext="AES Key Schedule Instruction 1 (RV64)"] +==== aes64ks1i + +Synopsis:: +This instruction implements part of the KeySchedule operation for the +AES Block cipher involving the SBox operation. + +Mnemonic:: +aes64ks1i rd, rs1, rnum + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 4, name: 'rnum'}, +{bits: 1, name: 0x1}, +{bits: 5, name: 0x18}, +{bits: 2, name: 0}, +]} +.... + +Description:: +This instruction implements the rotation, SubBytes and Round Constant +addition steps of the AES block cipher Key Schedule. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. +Note that `rnum` must be in the range `0x0..0xA`. +The values `0xB..0xF` are reserved. + +Operation:: +[source,sail] +-- +function clause execute (AES64KS1I(rnum, rs1, rd)) = { + if(unsigned(rnum) > 10) then { + handle_illegal(); RETIRE_SUCCESS + } else { + let tmp1 : bits(32) = X(rs1)[63..32]; + let rc : bits(32) = aes_decode_rcon(rnum); /* round number -> round constant */ + let tmp2 : bits(32) = if (rnum ==0xA) then tmp1 else ror32(tmp1, 8); + let tmp3 : bits(32) = aes_subword_fwd(tmp2); + let result : bits(64) = (tmp3 ^ rc) @ (tmp3 ^ rc); + X(rd) = EXTZ(result); + RETIRE_SUCCESS + } +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zkne>> (RV64) +| v1.0.0 +| Frozen +| <<zknd>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-aes64ks2, reftext="AES Key Schedule Instruction 2 (RV64)"] +==== aes64ks2 + +Synopsis:: +This instruction implements part of the KeySchedule operation for the +AES Block cipher. + +Mnemonic:: +aes64ks2 rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x1f}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction implements the additional XOR'ing of key words as +part of the AES block cipher Key Schedule. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (AES64KS2(rs2, rs1, rd)) = { + let w0 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0]; + let w1 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0] ^ X(rs2)[63..32]; + X(rd) = w1 @ w0; + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zkne>> (RV64) +| v1.0.0 +| Frozen +| <<zknd>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-andn,reftext="AND with inverted operand"] +==== andn + +Synopsis:: +AND with inverted operand + +Mnemonic:: +andn _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['ANDN']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x20, attr: ['ANDN'] }, +]} +.... + +Description:: +This instruction performs the bitwise logical AND operation between _rs1_ and the bitwise inversion of _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs1) & ~X(rs2); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-brev8,reftext="Reverse bits in bytes"] +==== brev8 + +Synopsis:: +Reverse the bits in each byte of a source register. + +Mnemonic:: +brev8, _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x65 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x687 }, +]} +.... + +Description:: +This instruction reverses the order of the bits in every byte of a register. + +[NOTE] +==== +This instruction is a specific encoding of a more generic instruction which was originally +proposed as part of the RISC-V Bitmanip extension (grevi). Eventually, the more generic +instruction may be standardised. Until then, only the most common instances of it, such as +this, are being included in specifications. +==== + +Operation:: +[source,sail] +-- +result : xlenbits = EXTZ(0b0); +foreach (i from 0 to sizeof(xlen) by 8) { +result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]); +}; +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-clmul,reftext="Carry-less multiply (low-part)"] +==== clmul + +Synopsis:: +Carry-less multiply (low-part) + +Mnemonic:: +clmul _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['CLMUL'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +clmul produces the lower half of the 2·XLEN carry-less product. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); +let output : xlenbits = 0; + +foreach (i from 0 to (xlen - 1) by 1) { + output = if ((rs2_val >> i) & 1) + then output ^ (rs1_val << i); + else output; +} + +X[rd] = output +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbc (<<#zbc>>) +|1.0.0 +|Frozen + +|Zbkc (<<#zbkc>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-clmulh,reftext="Carry-less multiply (high-part)"] +==== clmulh + +Synopsis:: +Carry-less multiply (high-part) + +Mnemonic:: +clmulh _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x3, attr: ['CLMULH'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, +]} +.... + +Description:: +clmulh produces the upper half of the 2·XLEN carry-less product. + +Operation:: +[source,sail] +-- +let rs1_val = X(rs1); +let rs2_val = X(rs2); +let output : xlenbits = 0; + +foreach (i from 1 to xlen by 1) { + output = if ((rs2_val >> i) & 1) + then output ^ (rs1_val >> (xlen - i)); + else output; +} + +X[rd] = output +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbc (<<#zbc>>) +|1.0.0 +|Frozen + +|Zbkc (<<#zbkc>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-orn,reftext="OR with inverted operand"] +==== orn + +Synopsis:: +OR with inverted operand + +Mnemonic:: +orn _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['ORN']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x20, attr: ['ORN'] }, +]} +.... + +Description:: +This instruction performs the bitwise logical OR operation between _rs1_ and the bitwise inversion of _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = X(rs1) | ~X(rs2); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-pack,reftext="Pack low halves of registers"] +==== pack + +Synopsis:: +Pack the low halves of _rs1_ and _rs2_ into _rd_. + +Mnemonic:: +pack _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + {bits: 7, name: 0x33, attr: ['OP'] }, + {bits: 5, name: 'rd'}, + {bits: 3, name: 0x4, attr:['PACK']}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 0x4, attr:['PACK']}, +]} +.... + +Description:: +The pack instruction packs the XLEN/2-bit lower halves of _rs1_ and _rs2_ into +_rd_, with _rs1_ in the lower half and _rs2_ in the upper half. + +Operation:: +[source,sail] +-- +let lo_half : bits(xlen/2) = X(rs1)[xlen/2-1..0]; +let hi_half : bits(xlen/2) = X(rs2)[xlen/2-1..0]; +X(rd) = EXTZ(hi_half @ lo_half); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-packh,reftext="Pack low bytes of registers"] +==== packh + +Synopsis:: +Pack the low bytes of _rs1_ and _rs2_ into _rd_. + +Mnemonic:: +packh _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + {bits: 7, name: 0x33, attr: ['OP'] }, + {bits: 5, name: 'rd'}, + {bits: 3, name: 0x7, attr: ['PACKH']}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 0x4, attr: ['PACKH']}, +]} +.... + +Description:: +And the packh instruction packs the least-significant bytes of +_rs1_ and _rs2_ into the 16 least-significant bits of _rd_, +zero extending the rest of _rd_. + +Operation:: +[source,sail] +-- +let lo_half : bits(8) = X(rs1)[7..0]; +let hi_half : bits(8) = X(rs2)[7..0]; +X(rd) = EXTZ(hi_half @ lo_half); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-packw,reftext="Pack low 16-bits of registers (RV64)"] +==== packw + +Synopsis:: +Pack the low 16-bits of _rs1_ and _rs2_ into _rd_ on RV64. + +Mnemonic:: +packw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 2, name: 0x3}, +{bits: 5, name: 0xe}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x4}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 7, name: 0x4}, +]} +.... + +Description:: +This instruction packs the low 16 bits of +_rs1_ and _rs2_ into the 32 least-significant bits of _rd_, +sign extending the 32-bit result to the rest of _rd_. +This instruction only exists on RV64 based systems. + +Operation:: +[source,sail] +-- +let lo_half : bits(16) = X(rs1)[15..0]; +let hi_half : bits(16) = X(rs2)[15..0]; +X(rd) = EXTS(hi_half @ lo_half); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-rev8,reftext="Byte-reverse register"] +==== rev8 + +Synopsis:: +Byte-reverse register + +Mnemonic:: +rev8 _rd_, _rs_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x698 } +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5 }, + { bits: 5, name: 'rs' }, + { bits: 12, name: 0x6b8 } +]} +.... + +Description:: +This instruction reverses the order of the bytes in _rs_. + +Operation:: +[source,sail] +-- +let input = X(rs); +let output : xlenbits = 0; +let j = xlen - 1; + +foreach (i from 0 to (xlen - 8) by 8) { + output[i..(i + 7)] = input[(j - 7)..j]; + j = j - 8; +} + +X[rd] = output +-- + +.Note +[NOTE, caption="A" ] +=============================================================== +The *rev8* mnemonic corresponds to different instruction encodings in RV32 and RV64. +=============================================================== + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +The byte-reverse operation is only available for the full register +width. To emulate word-sized and halfword-sized byte-reversal, +perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K is +XLEN-32 and XLEN-16, respectively. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-rol,reftext="Rotate left (Register)"] +==== rol + +Synopsis:: +Rotate Left (Register) + +Mnemonic:: +rol _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['ROL']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['ROL'] }, +]} +.... + +Description:: +This instruction performs a rotate left of _rs1_ by the amount in least-significant log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let shamt = if xlen == 32 + then X(rs2)[4..0] + else X(rs2)[5..0]; +let result = (X(rs1) << shamt) | (X(rs1) >> (xlen - shamt)); + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-rolw,reftext="Rotate Left Word (Register)"] +==== rolw + +Synopsis:: +Rotate Left Word (Register) + +Mnemonic:: +rolw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['ROLW']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['ROLW'] }, +]} +.... + +Description:: +This instruction performs a rotate left on the least-significant word of _rs1_ by the amount in least-significant 5 bits of _rs2_. +The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits. + +Operation:: +[source,sail] +-- +let rs1 = EXTZ(X(rs1)[31..0]) +let shamt = X(rs2)[4..0]; +let result = (rs1 << shamt) | (rs1 >> (32 - shamt)); +X(rd) = EXTS(result[31..0]); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-ror, reftext="Rotate right (Register)"] +==== ror + +Synopsis:: +Rotate Right + +Mnemonic:: +ror _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['ROR']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['ROR'] }, +]} +.... + +Description:: +This instruction performs a rotate right of _rs1_ by the amount in least-significant log2(XLEN) bits of _rs2_. + +Operation:: +[source,sail] +-- +let shamt = if xlen == 32 + then X(rs2)[4..0] + else X(rs2)[5..0]; +let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt)); + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-rori,reftext="Rotate right (Immediate)"] +==== rori + +Synopsis:: +Rotate Right (Immediate) + +Mnemonic:: +rori _rd_, _rs1_, _shamt_ + +Encoding (RV32):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORI']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x30, attr: ['RORI'] }, +]} +.... + +Encoding (RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x13, attr: ['OP-IMM'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORI']}, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'shamt' }, + { bits: 6, name: 0x18, attr: ['RORI'] }, +]} +.... + +Description:: +This instruction performs a rotate right of _rs1_ by the amount in the least-significant log2(XLEN) bits of _shamt_. +For RV32, the encodings corresponding to shamt[5]=1 are reserved. + +Operation:: +[source,sail] +-- +let shamt = if xlen == 32 + then shamt[4..0] + else shamt[5..0]; +let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt)); + +X(rd) = result; +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-roriw,reftext="Rotate right Word (Immediate)"] +==== roriw + +Synopsis:: +Rotate Right Word by Immediate + +Mnemonic:: +roriw _rd_, _rs1_, _shamt_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORIW']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'shamt' }, + { bits: 7, name: 0x30, attr: ['RORIW'] }, +]} +.... + +Description:: +This instruction performs a rotate right on the least-significant word +of _rs1_ by the amount in the least-significant log2(XLEN) bits of +_shamt_. +The resulting word value is sign-extended by copying bit 31 to all of +the more-significant bits. + + +Operation:: +[source,sail] +-- +let rs1_data = EXTZ(X(rs1)[31..0]; +let result = (rs1_data >> shamt) | (rs1_data << (32 - shamt)); +X(rd) = EXTS(result[31..0]); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-rorw,reftext="Rotate right Word (Register)"] +==== rorw + +Synopsis:: +Rotate Right Word (Register) + +Mnemonic:: +rorw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x3b, attr: ['OP-32'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['RORW']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x30, attr: ['RORW'] }, +]} +.... + +Description:: +This instruction performs a rotate right on the least-significant word of _rs1_ by the amount in least-significant 5 bits of _rs2_. +The resultant word is sign-extended by copying bit 31 to all of the more-significant bits. + +Operation:: +[source,sail] +-- +let rs1 = EXTZ(X(rs1)[31..0]) +let shamt = X(rs2)[4..0]; +let result = (rs1 >> shamt) | (rs1 << (32 - shamt)); +X(rd) = EXTS(result); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-sha256sig0, reftext="SHA2-256 Sigma0 instruction"] +==== sha256sig0 + +Synopsis:: +Implements the Sigma0 transformation function as used in +the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2). + +Mnemonic:: +sha256sig0 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x2}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for both RV32 and RV64 base architectures. +For RV32, the entire `XLEN` source register is operated on. +For RV64, the low `32` bits of the source register are operated on, and the +result sign extended to `XLEN` bits. +Though named for SHA2-256, the instruction works for both the +SHA2-224 and SHA2-256 parameterisations as described in +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA256SIG0(rs1,rd)) = { + let inb : bits(32) = X(rs1)[31..0]; + let result : bits(32) = ror32(inb, 7) ^ ror32(inb, 18) ^ (inb >> 3); + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> +| v1.0.0 +| Frozen +| <<zkn>> +| v1.0.0 +| Frozen +| <<zk>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha256sig1, reftext="SHA2-256 Sigma1 instruction"] +==== sha256sig1 + +Synopsis:: +Implements the Sigma1 transformation function as used in +the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2). + +Mnemonic:: +sha256sig1 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x3}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for both RV32 and RV64 base architectures. +For RV32, the entire `XLEN` source register is operated on. +For RV64, the low `32` bits of the source register are operated on, and the +result sign extended to `XLEN` bits. +Though named for SHA2-256, the instruction works for both the +SHA2-224 and SHA2-256 parameterisations as described in +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA256SIG1(rs1,rd)) = { + let inb : bits(32) = X(rs1)[31..0]; + let result : bits(32) = ror32(inb, 17) ^ ror32(inb, 19) ^ (inb >> 10); + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> +| v1.0.0 +| Frozen +| <<zkn>> +| v1.0.0 +| Frozen +| <<zk>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha256sum0, reftext="SHA2-256 Sum0 instruction"] +==== sha256sum0 + +Synopsis:: +Implements the Sum0 transformation function as used in +the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2). + +Mnemonic:: +sha256sum0 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x0}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for both RV32 and RV64 base architectures. +For RV32, the entire `XLEN` source register is operated on. +For RV64, the low `32` bits of the source register are operated on, and the +result sign extended to `XLEN` bits. +Though named for SHA2-256, the instruction works for both the +SHA2-224 and SHA2-256 parameterisations as described in +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA256SUM0(rs1,rd)) = { + let inb : bits(32) = X(rs1)[31..0]; + let result : bits(32) = ror32(inb, 2) ^ ror32(inb, 13) ^ ror32(inb, 22); + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> +| v1.0.0 +| Frozen +| <<zkn>> +| v1.0.0 +| Frozen +| <<zk>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha256sum1, reftext="SHA2-256 Sum1 instruction"] +==== sha256sum1 + +Synopsis:: +Implements the Sum1 transformation function as used in +the SHA2-256 hash function cite:[nist:fips:180:4] (Section 4.1.2). + +Mnemonic:: +sha256sum1 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x1}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for both RV32 and RV64 base architectures. +For RV32, the entire `XLEN` source register is operated on. +For RV64, the low `32` bits of the source register are operated on, and the +result sign extended to `XLEN` bits. +Though named for SHA2-256, the instruction works for both the +SHA2-224 and SHA2-256 parameterisations as described in +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA256SUM1(rs1,rd)) = { + let inb : bits(32) = X(rs1)[31..0]; + let result : bits(32) = ror32(inb, 6) ^ ror32(inb, 11) ^ ror32(inb, 25); + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> +| v1.0.0 +| Frozen +| <<zkn>> +| v1.0.0 +| Frozen +| <<zk>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sig0h, reftext="SHA2-512 Sigma0 high (RV32)"] +==== sha512sig0h + +Synopsis:: +Implements the _high half_ of the Sigma0 transformation, as +used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sig0h rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0xe}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction is implemented on RV32 only. +Used to compute the Sigma0 transform of the SHA2-512 hash function +in conjunction with the <<insns-sha512sig0l,`sha512sig0l`>> instruction. +The transform is a 64-bit to 64-bit function, so the input and output +are each represented by two 32-bit registers. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +[TIP] +.Note to software developers +==== +The entire Sigma0 transform for SHA2-512 may be computed on RV32 +using the following instruction sequence: + + sha512sig0l t0, a0, a1 + sha512sig0h t1, a1, a0 + +==== + +Operation:: +[source,sail] +-- +function clause execute (SHA512SIG0H(rs2, rs1, rd)) = { + X(rd) = EXTS((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^ + (X(rs2) << 31) ^ (X(rs2) << 24) ); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sig0l, reftext="SHA2-512 Sigma0 low (RV32)"] +==== sha512sig0l + +Synopsis:: +Implements the _low half_ of the Sigma0 transformation, as +used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sig0l rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0xa}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction is implemented on RV32 only. +Used to compute the Sigma0 transform of the SHA2-512 hash function +in conjunction with the <<insns-sha512sig0h,`sha512sig0h`>> instruction. +The transform is a 64-bit to 64-bit function, so the input and output +are each represented by two 32-bit registers. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +[TIP] +.Note to software developers +==== +The entire Sigma0 transform for SHA2-512 may be computed on RV32 +using the following instruction sequence: + + sha512sig0l t0, a0, a1 + sha512sig0h t1, a1, a0 + +==== + +Operation:: +[source,sail] +-- +function clause execute (SHA512SIG0L(rs2, rs1, rd)) = { + X(rd) = EXTS((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^ + (X(rs2) << 31) ^ (X(rs2) << 25) ^ (X(rs2) << 24) ); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sig1h, reftext="SHA2-512 Sigma1 high (RV32)"] +==== sha512sig1h + +Synopsis:: +Implements the _high half_ of the Sigma1 transformation, as +used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sig1h rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0xf}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction is implemented on RV32 only. +Used to compute the Sigma1 transform of the SHA2-512 hash function +in conjunction with the <<insns-sha512sig1l,`sha512sig1l`>> instruction. +The transform is a 64-bit to 64-bit function, so the input and output +are each represented by two 32-bit registers. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +[TIP] +.Note to software developers +==== +The entire Sigma1 transform for SHA2-512 may be computed on RV32 +using the following instruction sequence: + + sha512sig1l t0, a0, a1 + sha512sig1h t1, a1, a0 + +==== + +Operation:: +[source,sail] +-- +function clause execute (SHA512SIG1H(rs2, rs1, rd)) = { + X(rd) = EXTS((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^ + (X(rs2) >> 29) ^ (X(rs2) << 13) ); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sig1l, reftext="SHA2-512 Sigma1 low (RV32)"] +==== sha512sig1l + +Synopsis:: +Implements the _low half_ of the Sigma1 transformation, as +used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sig1l rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0xb}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction is implemented on RV32 only. +Used to compute the Sigma1 transform of the SHA2-512 hash function +in conjunction with the <<insns-sha512sig1h,`sha512sig1h`>> instruction. +The transform is a 64-bit to 64-bit function, so the input and output +are each represented by two 32-bit registers. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +[TIP] +.Note to software developers +==== +The entire Sigma1 transform for SHA2-512 may be computed on RV32 +using the following instruction sequence: + + sha512sig1l t0, a0, a1 + sha512sig1h t1, a1, a0 + +==== + +Operation:: +[source,sail] +-- +function clause execute (SHA512SIG1L(rs2, rs1, rd)) = { + X(rd) = EXTS((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^ + (X(rs2) >> 29) ^ (X(rs2) << 26) ^ (X(rs2) << 13) ); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sum0r, reftext="SHA2-512 Sum0 (RV32)"] +==== sha512sum0r + +Synopsis:: +Implements the Sum0 transformation, as +used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sum0r rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction is implemented on RV32 only. +Used to compute the Sum0 transform of the SHA2-512 hash function. +The transform is a 64-bit to 64-bit function, so the input and output +is represented by two 32-bit registers. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +[TIP] +.Note to software developers +==== +The entire Sum0 transform for SHA2-512 may be computed on RV32 +using the following instruction sequence: + + sha512sum0r t0, a0, a1 + sha512sum0r t1, a1, a0 + +Note the reversed source register ordering. +==== + +Operation:: +[source,sail] +-- +function clause execute (SHA512SUM0R(rs2, rs1, rd)) = { + X(rd) = EXTS((X(rs1) << 25) ^ (X(rs1) << 30) ^ (X(rs1) >> 28) ^ + (X(rs2) >> 7) ^ (X(rs2) >> 2) ^ (X(rs2) << 4) ); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sum1r, reftext="SHA2-512 Sum1 (RV32)"] +==== sha512sum1r + +Synopsis:: +Implements the Sum1 transformation, as +used in the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sum1r rd, rs1, rs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x9}, +{bits: 2, name: 0x1}, +]} +.... + +Description:: +This instruction is implemented on RV32 only. +Used to compute the Sum1 transform of the SHA2-512 hash function. +The transform is a 64-bit to 64-bit function, so the input and output +is represented by two 32-bit registers. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +[TIP] +.Note to software developers +==== +The entire Sum1 transform for SHA2-512 may be computed on RV32 +using the following instruction sequence: + + sha512sum1r t0, a0, a1 + sha512sum1r t1, a1, a0 + +Note the reversed source register ordering. +==== + +Operation:: +[source,sail] +-- +function clause execute (SHA512SUM1R(rs2, rs1, rd)) = { + X(rd) = EXTS((X(rs1) << 23) ^ (X(rs1) >> 14) ^ (X(rs1) >> 18) ^ + (X(rs2) >> 9) ^ (X(rs2) << 18) ^ (X(rs2) << 14) ); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV32) +| v1.0.0 +| Frozen +| <<zkn>> (RV32) +| v1.0.0 +| Frozen +| <<zk>> (RV32) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sig0, reftext="SHA2-512 Sigma0 instruction (RV64)"] +==== sha512sig0 + +Synopsis:: +Implements the Sigma0 transformation function as used in +the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sig0 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x6}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for the RV64 base architecture. +It implements the Sigma0 transform of the SHA2-512 hash function. +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA512SIG0(rs1, rd)) = { + X(rd) = ror64(X(rs1), 1) ^ ror64(X(rs1), 8) ^ (X(rs1) >> 7); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sig1, reftext="SHA2-512 Sigma1 instruction (RV64)"] +==== sha512sig1 + +Synopsis:: +Implements the Sigma1 transformation function as used in +the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sig1 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x7}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for the RV64 base architecture. +It implements the Sigma1 transform of the SHA2-512 hash function. +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA512SIG1(rs1, rd)) = { + X(rd) = ror64(X(rs1), 19) ^ ror64(X(rs1), 61) ^ (X(rs1) >> 6); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sum0, reftext="SHA2-512 Sum0 instruction (RV64)"] +==== sha512sum0 + +Synopsis:: +Implements the Sum0 transformation function as used in +the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sum0 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x4}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for the RV64 base architecture. +It implements the Sum0 transform of the SHA2-512 hash function. +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA512SUM0(rs1, rd)) = { + X(rd) = ror64(X(rs1), 28) ^ ror64(X(rs1), 34) ^ ror64(X(rs1) ,39); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sha512sum1, reftext="SHA2-512 Sum1 instruction (RV64)"] +==== sha512sum1 + +Synopsis:: +Implements the Sum1 transformation function as used in +the SHA2-512 hash function cite:[nist:fips:180:4] (Section 4.1.3). + +Mnemonic:: +sha512sum1 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x5}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for the RV64 base architecture. +It implements the Sum1 transform of the SHA2-512 hash function. +cite:[nist:fips:180:4]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SHA512SUM1(rs1, rd)) = { + X(rd) = ror64(X(rs1), 14) ^ ror64(X(rs1), 18) ^ ror64(X(rs1) ,41); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zknh>> (RV64) +| v1.0.0 +| Frozen +| <<zkn>> (RV64) +| v1.0.0 +| Frozen +| <<zk>> (RV64) +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sm3p0, reftext="SM3 P0 transform"] +==== sm3p0 + +Synopsis:: +Implements the _P0_ transformation function as used in +the SM3 hash function cite:[gbt:sm3,iso:sm3]. + +Mnemonic:: +sm3p0 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x8}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for the RV32 and RV64 base architectures. +It implements the _P0_ transform of the SM3 hash function cite:[gbt:sm3,iso:sm3]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +.Supporting Material +[NOTE] +==== +This instruction is based on work done in cite:[MJS:LWSHA:20]. +==== + +Operation:: +[source,sail] +-- +function clause execute (SM3P0(rs1, rd)) = { + let r1 : bits(32) = X(rs1)[31..0]; + let result : bits(32) = r1 ^ rol32(r1, 9) ^ rol32(r1, 17); + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zksh>> +| v1.0.0 +| Frozen +| <<zks>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sm3p1, reftext="SM3 P1 transform"] +==== sm3p1 + +Synopsis:: +Implements the _P1_ transformation function as used in +the SM3 hash function cite:[gbt:sm3,iso:sm3]. + +Mnemonic:: +sm3p1 rd, rs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x13}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x9}, +{bits: 5, name: 0x8}, +{bits: 2, name: 0x0}, +]} +.... + +Description:: +This instruction is supported for the RV32 and RV64 base architectures. +It implements the _P1_ transform of the SM3 hash function cite:[gbt:sm3,iso:sm3]. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +.Supporting Material +[NOTE] +==== +This instruction is based on work done in cite:[MJS:LWSHA:20]. +==== + +Operation:: +[source,sail] +-- +function clause execute (SM3P1(rs1, rd)) = { + let r1 : bits(32) = X(rs1)[31..0]; + let result : bits(32) = r1 ^ rol32(r1, 15) ^ rol32(r1, 23); + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zksh>> +| v1.0.0 +| Frozen +| <<zks>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sm4ed, reftext="SM4 Encrypt/Decrypt Instruction"] +==== sm4ed + +Synopsis:: +Accelerates the block encrypt/decrypt operation of the SM4 block cipher +cite:[gbt:sm4, iso:sm4]. + +Mnemonic:: +sm4ed rd, rs1, rs2, bs + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x18}, +{bits: 2, name: 'bs'}, +]} +.... + +Description:: +Implements a T-tables in hardware style approach to accelerating the +SM4 round function. +A byte is extracted from `rs2` based on `bs`, to which the SBox and +linear layer transforms are applied, before the result is XOR'd with +`rs1` and written back to `rd`. +This instruction exists on RV32 and RV64 base architectures. +On RV64, the 32-bit result is sign extended to XLEN bits. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SM4ED (bs,rs2,rs1,rd)) = { + let shamt : bits(5) = bs @ 0b000; /* shamt = bs*8 */ + let sb_in : bits(8) = (X(rs2)[31..0] >> shamt)[7..0]; + let x : bits(32) = 0x000000 @ sm4_sbox(sb_in); + let y : bits(32) = x ^ (x << 8) ^ ( x << 2) ^ + (x << 18) ^ ((x & 0x0000003F) << 26) ^ + ((x & 0x000000C0) << 10); + let z : bits(32) = rol32(y, unsigned(shamt)); + let result: bits(32) = z ^ X(rs1)[31..0]; + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zksed>> +| v1.0.0 +| Frozen +| <<zks>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-sm4ks, reftext="SM4 Key Schedule Instruction"] +==== sm4ks + +Synopsis:: +Accelerates the Key Schedule operation of the SM4 block cipher +cite:[gbt:sm4, iso:sm4]. + +Mnemonic:: +sm4ks rd, rs1, rs2, bs + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x33}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x0}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'rs2'}, +{bits: 5, name: 0x1a}, +{bits: 2, name: 'bs'}, +]} +.... + +Description:: +Implements a T-tables in hardware style approach to accelerating the +SM4 Key Schedule. +A byte is extracted from `rs2` based on `bs`, to which the SBox and +linear layer transforms are applied, before the result is XOR'd with +`rs1` and written back to `rd`. +This instruction exists on RV32 and RV64 base architectures. +On RV64, the 32-bit result is sign extended to XLEN bits. +This instruction must _always_ be implemented such that its execution +latency does not depend on the data being operated on. + +Operation:: +[source,sail] +-- +function clause execute (SM4KS (bs,rs2,rs1,rd)) = { + let shamt : bits(5) = (bs @ 0b000); /* shamt = bs*8 */ + let sb_in : bits(8) = (X(rs2)[31..0] >> shamt)[7..0]; + let x : bits(32) = 0x000000 @ sm4_sbox(sb_in); + let y : bits(32) = x ^ ((x & 0x00000007) << 29) ^ ((x & 0x000000FE) << 7) ^ + ((x & 0x00000001) << 23) ^ ((x & 0x000000F8) << 13) ; + let z : bits(32) = rol32(y, unsigned(shamt)); + let result: bits(32) = z ^ X(rs1)[31..0]; + X(rd) = EXTS(result); + RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +| <<zksed>> +| v1.0.0 +| Frozen +| <<zks>> +| v1.0.0 +| Frozen +|=== + +<<< + +[#insns-unzip,reftext="Bit deinterleave"] +==== unzip + +Synopsis:: +Implements the inverse of the zip instruction. + +Mnemonic:: +unzip _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 2, name: 0x3}, +{bits: 5, name: 0x4}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x5}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x1f}, +{bits: 7, name: 0x4}, +]} +.... + +Description:: +This instruction gathers bits from the high and low halves of the source +word into odd/even bit positions in the destination word. +It is the inverse of the <<insns-zip,zip>> instruction. +This instruction is available only on RV32. + +Operation:: +[source,sail] +-- +foreach (i from 0 to xlen/2-1) { + X(rd)[i] = X(rs1)[2*i] + X(rd)[i+xlen/2] = X(rs1)[2*i+1] +} +-- + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +This instruction is useful for implementing the SHA3 cryptographic +hash function on a 32-bit architecture, as it implements the +bit-interleaving operation used to speed up the 64-bit rotations +directly. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) (RV32) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-xnor,reftext="Exclusive NOR"] +==== xnor + +Synopsis:: +Exclusive NOR + +Mnemonic:: +xnor _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0x33, attr: ['OP'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['XNOR']}, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x20, attr: ['XNOR'] }, +]} +.... + +Description:: +This instruction performs the bit-wise exclusive-NOR operation on _rs1_ and _rs2_. + +Operation:: +[source,sail] +-- +X(rd) = ~(X(rs1) ^ X(rs2)); +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbb (<<#zbb>>) +|v1.0.0 +|Frozen + +|Zbkb (<<#zbkb>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< +[#insns-xperm8,reftext="Crossbar permutation (bytes)"] +==== xperm8 + +Synopsis:: +Byte-wise lookup of indicies into a vector. + +Mnemonic:: +xprem8 _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 2, name: 0x3 }, + { bits: 5, name: 0xC }, + { bits: 5, name: 'rd'}, + { bits: 3, name: 0x4 }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x14 }, +]} +.... + +Description:: +The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit elements. The +rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in rs2 replaced by the +indexed element in rs1, or zero if the index into rs2 is out of bounds. + +Operation:: +[source,sail] +-- +val xperm8_lookup : (bits(8), xlenbits) -> bits(8) +function xperm8_lookup (idx, lut) = { +(lut >> (idx @ 0b000))[7..0] +} +function clause execute ( XPERM_8 (rs2,rs1,rd)) = { +result : xlenbits = EXTZ(0b0); +foreach(i from 0 to xlen by 8) { +result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1)); +}; +X(rd) = result; +RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkx (<<#zbkx>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-xperm4,reftext="Crossbar permutation (nibbles)"] +==== xperm4 + +Synopsis:: +Nibble-wise lookup of indicies into a vector. + +Mnemonic:: +xperm4 _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 2, name: 0x3 }, + { bits: 5, name: 0xC }, + { bits: 5, name: 'rd'}, + { bits: 3, name: 0x2 }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 7, name: 0x14 }, +]} +.... + +Description:: +The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit elements. +The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in rs2 replaced by the +indexed element in rs1, or zero if the index into rs2 is out of bounds. + +Operation:: +[source,sail] +-- +val xperm4_lookup : (bits(4), xlenbits) -> bits(4) +function xperm4_lookup (idx, lut) = { +(lut >> (idx @ 0b00))[3..0] +} +function clause execute ( XPERM_4 (rs2,rs1,rd)) = { +result : xlenbits = EXTZ(0b0); +foreach(i from 0 to xlen by 4) { +result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1)); +}; +X(rd) = result; +RETIRE_SUCCESS +} +-- + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkx (<<#zbkx>>) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[#insns-zip,reftext="Bit interleave"] +==== zip + +Synopsis:: +Gather odd and even bits of the source word into upper/lower halves of the +destination. + +Mnemonic:: +zip _rd_, _rs_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 2, name: 0x3}, +{bits: 5, name: 0x4}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 0x1e}, +{bits: 7, name: 0x4}, +]} +.... + +Description:: +This instruction scatters all of the odd and even bits of a source word into +the high and low halves of a destination word. +It is the inverse of the <<insns-unzip,unzip>> instruction. +This instruction is available only on RV32. + +Operation:: +[source,sail] +-- +foreach (i from 0 to xlen/2-1) { + X(rd)[2*i] = X(rs1)[i] + X(rd)[2*i+1] = X(rs1)[i+xlen/2] +} +-- + +.Software Hint +[NOTE, caption="SH" ] +=============================================================== +This instruction is useful for implementing the SHA3 cryptographic +hash function on a 32-bit architecture, as it implements the +bit-interleaving operation used to speed up the 64-bit rotations +directly. +=============================================================== + +Included in:: +[%header,cols="4,2,2"] +|=== +|Extension +|Minimum version +|Lifecycle state + +|Zbkb (<<#zbkb>>) (RV32) +|v1.0.0-rc4 +|Frozen +|=== + +<<< + +[[crypto_scalar_es]] +=== Entropy Source + +The `seed` CSR provides an interface to a NIST SP 800-90B cite:[TuBaKe:18] +or BSI AIS-31 cite:[KiSc11] compliant physical Entropy Source (ES). + +An entropy source, by itself, is not a cryptographically secure Random +Bit Generator (RBG), but can be used to build standard (and nonstandard) +RBGs of many types with the help of symmetric cryptography. Expected usage +is to condition (typically with SHA-2/3) the output from an entropy source and +use it to seed a cryptographically secure Deterministic Random Bit Generator +(DRBG) such as AES-based `CTR_DRBG` cite:[BaKe15]. +The combination of an Entropy Source, Conditioning, and a DRBG can be used +to create random bits securely cite:[BaKeRo:21]. +See <<crypto_scalar_appx_es>> for a non-normative description of a +certification and self-certification procedures, design rationale, and more +detailed suggestions on how the entropy source output can be used. + +[[crypto_scalar_seed_csr]] +==== The `seed` CSR + +`seed` is an unprivileged CSR located at address `0x015`. +The 32-bit contents of `seed` are as follows: + +[%autowidth.stretch,cols="^,^,<",options="header",] +|======================================================================= +|Bits |Name |Description + +|`31:30` |`OPST` |Status: `BIST` (00), `WAIT` (01), `ES16` (10), `DEAD` +(11). + +|`29:24` |_reserved_ |For future use by the RISC-V specification. + +|`23:16` |_custom_ |Designated for custom and experimental use. + +|`15: 0` |`entropy` |16 bits of randomness, only when `OPST=ES16`. +|======================================================================= + +The `seed` CSR must be accessed with a read-write instruction. A read-only +instruction such as `CSRRS/CSRRC` with `rs1=x0` or `CSRRSI/CSRRCI` with +`uimm=0` will raise an illegal instruction exception. +The write value (in `rs1` or `uimm`) must be ignored by implementations. +The purpose of the write is to signal polling and flushing. + +The instruction `csrrw rd, seed, x0` can be used for fetching seed status +and entropy values. It is available on both RV32 and RV64 base architectures +and will zero-extend the 32-bit word to XLEN bits. + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 0x73, attr: "SYSTEM"}, +{bits: 5, name: 'rd'}, +{bits: 3, name: 0x1, attr: "CSRRW"}, +{bits: 5, name: 0x0, attr: "x0"}, +{bits: 12, name: 0x15, attr: "seed = 0x015"}, +]} +.... + +The `seed` CSR is also access controlled by execution mode, and attempted +read or write access will raise an illegal instruction exception outside M mode +unless access is explicitly granted. See <<crypto_scalar_es_access>> for +more details. + +The status bits `seed[31:30]` = `OPST` may be `ES16` (10), +indicating successful polling, or one of three entropy polling failure +statuses `BIST` (00), `WAIT` (01), or `DEAD` (11), discussed below. + +Each returned `seed[15:0]` = `entropy` value represents unique randomness +when `OPST`=`ES16` (`seed[31:30]` = `10`), even if its numerical value is +the same as that of a previously polled `entropy` value. The implementation +requirements of `entropy` bits are defined in <<crypto_scalar_es_req>>. +When `OPST` is not `ES16`, `entropy` must be set to 0. +An implementation may safely set reserved and custom bits to zeros. + +For security reasons, the interface guarantees that secret `entropy` +words are not made available multiple times. Hence polling (reading) must +also have the side effect of clearing (wipe-on-read) the `entropy` contents and +changing the state to `WAIT` (unless there is `entropy` +immediately available for `ES16`). Other states (`BIST`, `WAIT`, and `DEAD`) +may be unaffected by polling. + +The Status Bits returned in `seed[31:30]`=`OPST`: + +* `00` - `BIST` +indicates that Built-In Self-Test "on-demand" (BIST) testing is being +performed. If `OPST` returns temporarily to `BIST` from any other +state, this signals a non-fatal self-test alarm, +which is non-actionable, apart from being logged. +Such a `BIST` alarm must be latched until polled at least once to enable +software to record its occurrence. + +* `01` - `WAIT` +means that a sufficient amount of entropy is not yet available. This +is not an error condition and may (in fact) be more frequent than ES16 +since physical entropy sources often have low bandwidth. + +* `10` - `ES16` +indicates success; the low bits `seed[15:0]` will have 16 bits of +randomness (`entropy`), which is guaranteed to meet certain minimum entropy +requirements, regardless of implementation. + +* `11` - `DEAD` +is an unrecoverable self-test error. This may indicate a hardware +fault, a security issue, or (extremely rarely) a type-1 statistical +false positive in the continuous testing procedures. In case of a fatal +failure, an immediate lockdown may also be an appropriate response in +dedicated security devices. + +**Example.** `0x8000ABCD` is a valid `ES16` status output, with `0xABCD` +being the `entropy` value. `0xFFFFFFFF` is an invalid output (`DEAD`) with +no `entropy` value. + +[[crypto_scalar_es_state,reftext="Entropy Source State Transition Diagram"]] +==== +image::es_state.svg[title="Entropy Source state transition diagram.", align="center",scaledwidth=40%] +Normally the operational state alternates between WAIT +(no data) and ES16, which means that 16 bits of randomness (`entropy`) +have been polled. BIST (Built-in Self-Test) only occurs after reset +or to signal a non-fatal self-test alarm (if reached after WAIT or +ES16). DEAD is an unrecoverable error state. +==== + +[[crypto_scalar_es_req]] +==== Entropy Source Requirements + +The output `entropy` (`seed[15:0]` in ES16 state) is not necessarily +fully conditioned randomness due to hardware and energy limitations +of smaller, low-powered implementations. However, minimum requirements are +defined. The main requirement is that 2-to-1 cryptographic post-processing +in 256-bit input blocks will yield 128-bit "full entropy" output blocks. +Entropy source users may make this conservative assumption but are not +prohibited from using more than twice the number of seed bits relative +to the desired resulting entropy. + +An implementation of the entropy source should meet at least one of the +following requirements sets in order to be considered a secure and +safe design: + +* <<crypto_scalar_es_req_90b>>: A physical entropy source meeting + NIST SP 800-90B cite:[TuBaKe:18] criteria with evaluated min-entropy + of 192 bits for each 256 output bits (min-entropy rate 0.75). + +* <<crypto_scalar_es_req_ptg2>>: A physical entropy source meeting the + AIS-31 PTG.2 cite:[KiSc11] criteria, implying average Shannon entropy + rate 0.997. The source must also meet the NIST 800-90B + min-entropy rate 192/256 = 0.75. + +* <<crypto_scalar_es_req_virt>>: A virtual entropy source is a DRBG + seeded from a physical entropy source. It must have at least a + 256-bit (Post-Quantum Category 5) internal security level. + +All implementations must signal initialization, test mode, and health +alarms as required by respective standards. This may require the implementer +to add non-standard (custom) test interfaces in a secure and safe manner, +an example of which is described in <<crypto_scalar_es_getnoise>> + + +[[crypto_scalar_es_req_90b]] +===== NIST SP 800-90B / FIPS 140-3 Requirements + +All NIST SP 800-90B cite:[TuBaKe:18] required components and health test +mechanisms must be implemented. + +The entropy requirement is satisfied if 128 bits of _full entropy_ can be +obtained from each 256-bit (16*16 -bit) successful, but possibly +non-consecutive `entropy` (ES16) output sequence using a vetted conditioning +algorithm such as a cryptographic hash (See Section 3.1.5.1.1, SP 800-90B +cite:[TuBaKe:18]). In practice, a min-entropy rate of 0.75 or larger is +required for this. + +Note that 128 bits of estimated input min-entropy does not yield 128 bits of +conditioned, full entropy in SP 800-90B/C evaluation. Instead, the +implication is that every 256-bit sequence should have min-entropy of at +least 128+64 = 192 bits, as discussed in SP 800-90C cite:[BaKeRo:21]; +the likelihood of successfully "guessing" an individual 256-bit output +sequence should not be higher than 2^-192^ even with (almost) +unconstrained amount of entropy source data and computational power. + +Rather than attempting to define all the mathematical and architectural +properties that the entropy source must satisfy, we define that the physical +entropy source be strong and robust enough to pass the equivalent of +NIST SP 800-90 evaluation and certification for full entropy when +conditioned cryptographically in ratio 2:1 with 128-bit output blocks. + +Even though the requirement is defined in terms of 128-bit full entropy +blocks, we recommend 256-bit security. This can be accomplished by using +at least 512 `entropy` bits to initialize a DRBG that has 256-bit security. + +[[crypto_scalar_es_req_ptg2]] +===== BSI AIS-31 PTG.2 / Common Criteria Requirements + +For alternative Common Criteria certification (or self-certification), +AIS 31 PTG.2 class cite:[KiSc11] (Sect. 4.3.) required hardware components +and mechanisms must be implemented. +In addition to AIS-31 PTG.2 randomness requirements (Shannon entropy rate of +0.997 as evaluated in that standard), the overall min-entropy requirement of +remains, as discussed in <<crypto_scalar_es_req_90b>>. Note that 800-90B +min-entropy can be significantly lower than AIS-31 Shannon entropy. These +two metrics should not be equated or confused with each other. + + +[[crypto_scalar_es_req_virt]] +===== Virtual Sources: Security Requirement + +NOTE: A virtual source is not an ISA compliance requirement. It is defined +for the benefit of the RISC-V security ecosystem so that virtual systems +may have a consistent level of security. + +A virtual source is not a physical entropy source but provides +additional protection against covert channels, depletion attacks, and host +identification in operating environments that can not be entirely trusted +with direct access to a hardware resource. Despite limited trust, +implementors should try to guarantee that even such environments have +sufficient entropy available for secure cryptographic operations. + +A virtual source traps access to the `seed` CSR, emulates it, or +otherwise implements it, possibly without direct access to a physical entropy +source. The output can be cryptographically secure pseudorandomness +instead of real entropy, but must have at least 256-bit security, as defined +below. A virtual source is intended especially for guest operating +systems, sandboxes, emulators, and similar use cases. + +As a technical definition, a random-distinguishing attack against +the output should require computational resources comparable or greater +than those required for exhaustive key search on a secure block cipher +with a 256-bit key (e.g., AES 256). This applies to both classical +and quantum computing models, but only classical information flows. +The virtual source security requirement maps to Post-Quantum Security +Category 5 cite:[NI16]. + +Any implementation of the `seed` CSR that limits the security +strength shall not reduce it to less than 256 bits. If the security +level is under 256 bits, then the interface must not be available. + +A virtual entropy source does not need to implement `WAIT` or `BIST` states. +It should fail (`DEAD`) if the host DRBG or entropy source fails and +there is insufficient seeding material for the host DRBG. + + +[[crypto_scalar_es_access]] +==== Access Control to `seed` + +The `seed` CSR is by default only available in M mode, but can be made +available to other modes via the `mseccfg.sseed` and `mseccfg.useed` +access control bits. `sseed` is bit `9` of and `useed` is +bit `8` of the `mseccfg` CSR. +Without the corresponding access control bit set to 1, any attempted +access to `seed` from U, S, or HS modes will raise an illegal instruction +exception. + +VS and VU modes are present in systems with Hypervisor (H) extension +implemented. If desired, a hypervisor can emulate accesses to the seed CSR +from a virtual machine. Attempted access to `seed` from virtual modes +VS and VU always raises an exception; a read-only instruction causes an +illegal instruction exception, while a read-write instruction (that can +potentially be emulated) causes a virtual instruction exception only if +`mseccfg.sseed=1`. Note that `mseccfg.useed` has no effect on the exception +type for either VS or VU modes. + +.Entropy Source Access Control. + +[cols="1,1,1,7",options="header",] +|======================================================================= +|Mode | `sseed` | `useed` | Description + +| M +| `*` +| `*` +| The `seed` CSR is always available in machine mode as normal (with a +CSR read-write instruction.) Attempted read without a write raises an +illegal instruction exception regardless of mode and access control bits. + +| U +| `*` +| `0` +| Any `seed` CSR access raises an illegal instruction exception. + +| U +| `*` +| `1` +| The `seed` CSR is accessible as normal. No exception is raised for read-write. + +| S/HS +| `0` +| `*` +| Any `seed` CSR access raises an illegal instruction exception. + + +| S/HS +| `1` +| `*` +| The `seed` CSR is accessible as normal. No exception is raised for read-write. + +| VS/VU +| `0` +| `*` +| Any `seed` CSR access raises an illegal instruction exception. + +| VS/VU +| `1` +| `*` +| A read-write `seed` access raises a virtual instruction exception, +while other access conditions raise an illegal instruction exception. + +|======================================================================= + + +Systems should implement carefully considered access control policies from +lower privilege modes to physical entropy sources. The system can trap +attempted access to `seed` and feed a less privileged client +_virtual entropy source_ data (<<crypto_scalar_es_req_virt>>) instead of +invoking an SP 800-90B (<<crypto_scalar_es_req_90b>>) or PTG.2 +(<<crypto_scalar_es_req_ptg2>>) _physical entropy source_. Emulated `seed` +data generation is made with an appropriately seeded, secure software DRBG. +See <<crypto_scalar_appx_es_access>> for security considerations related +to direct access to entropy sources. + +Implementations may implement `mseccfg` such that `[s,u]seed` is a read-only +constant value `0`. Software may discover if access to the `seed` CSR can be +enabled in U and S mode by writing a `1` to `[s,u]seed` and reading back +the result. + +If S or U mode is not implemented, then the corresponding `[s,u]seed` +bits of `mseccfg` must be hardwired to zero. +The `[s,u]seed` bits must have a defined reset value. The system +must not allow them to be in an undefined state after a reset. +`mseccfg` exists if `Zkr` is implemented, or if it is required by other +processor features. If `Zkr` is _not_ implemented, the `[s,u]seed` bits must +be hardwired to zero. + +[[crypto_scalar_zkt]] + +=== Data Independent Execution Latency Subset: Zkt + +The Zkt extension attests that the machine has data-independent execution +time for a safe subset of instructions. This property is commonly called +_"constant-time"_ although should not be taken with that literal meaning. + +All currently proposed cryptographic instructions (scalar K extension) are on +this list, together with a set of relevant supporting instructions from +I, M, C, and B extensions. + + +.Note to software developers +[NOTE,caption="SH"] +==== +Failure to prevent leakage of sensitive parameters via the direct +timing channel is considered a serious security vulnerability and will +typically result in a CERT CVE security advisory. +==== + +==== Scope and Goal + +An "ISA contract" is made between a programmer and the RISC-V implementation +that Zkt instructions do not leak information about processed secret data +(plaintext, keying information, or other "sensitive security parameters" -- +FIPS 140-3 term) through differences in execution latency. Zkt does _not_ +define a set of instructions available in the core; it just restricts the +behaviour of certain instructions if those are implemented. + +Currently, the scope of this document is within scalar RV32/RV64 processors. +Vector cryptography instructions (and appropriate vector support instructions) +will be added later, as will other security-related functions that wish +to assert leakage-free execution latency properties. + +Loads, stores, conditional branches are excluded, along with a set of +instructions that are rarely necessary to process secret data. Also excluded +are instructions for which workarounds exist in standard cryptographic +middleware due to the limitations of other ISA processors. + +The stated goal is that OpenSSL, BoringSSL (Android), the Linux Kernel, +and similar trusted software will not have directly observable +timing side channels when compiled and running on a Zkt-enabled RISC-V target. +The Zkt extension explicitly states many of the common latency assumptions +made by cryptography developers. + +Vendors do not have to implement all of the list's instructions to be Zkt +compliant; however, if they claim to have Zkt and implement any of the listed instructions, it must have data-independent latency. + +For example, many simple RV32I and RV64I cores (without Multiply, Compressed, +Bitmanip, or Cryptographic extensions) are technically compliant with Zkt. +A constant-time AES can be implemented on them using "bit-slice" techniques, +but it will be excruciatingly slow when compared to implementation with AES +instructions. There are no guarantees that even a bit-sliced cipher +implementation (largely based on boolean logic instructions) is secure on a +core without Zkt attestation. + +Out-of-order implementations adhering to Zkt are still free to fuse, crack, +change or even ignore sequences of instructions, so long as the optimisations +are applied deterministically, and not based on operand data. +The guiding principle should be that no information about the data being +operated on should be leaked based on the execution latency. + +[NOTE] +==== +It is left to future extensions or other techniques to tackle the problem +of data-independent execution in implementations which advanced out-of-order +capabilities which use value prediction, or which are otherwise data-dependent. +==== + +.Note to software developers +[WARNING,caption="SH"] +==== +Programming techniques can only mitigate leakage directly caused by +arithmetic, caches, and branches. Other ISAs have had micro-architectural +issues such as Spectre, Meltdown, Speculative Store Bypass, Rogue System +Register Read, Lazy FP State Restore, Bounds Check Bypass Store, TLBleed, +and L1TF/Foreshadow, etc. See e.g. +link:https://github.com/nsacyber/Hardware-and-Firmware-Security-Guidance[NSA Hardware and Firmware Security Guidance] + +It is not within the remit of this proposal to mitigate these +_micro-architectural_ leakages. +==== + +==== Background + +* Timing attacks are much more powerful than was realised before the 2010s, +which has led to a significant mitigation effort in current cryptographic +code-bases. +* Cryptography developers use static and dynamic security testing tools +to trace the handling of secret information and detect occasions where it +influences a branch or is used for a table lookup. +* Architectural testing for Zkt can be pragmatic and semi-formal; +_security by design_ against basic timing attacks can usually be achieved via +conscious implementation (of relevant iterative multi-cycle instructions or +instructions composed of micro-ops) in way that avoids data-dependent latency. +* Laboratory testing may utilize statistical timing attack leakage analysis +techniques such as those described in ISO/IEC 17825 cite:[IS16]. +* Binary executables should not contain secrets in the instruction encodings +(Kerckhoffs's principle), so instruction timing may leak information about +immediates, ordering of input registers, etc. There may be an exception to this +in systems where a binary loader modifies the executable for purposes of +relocation -- and it is desirable to keep the execution location (PC) secret. +This is why instructions such as LUI, AUIPC, and ADDI are on the list. +* The rules used by audit tools are relatively simple to understand. +Very briefly; we call the plaintext, secret keys, expanded keys, nonces, +and other such variables "secrets". A secret variable (arithmetically) +modifying any other variable/register turns that into a secret too. +If a secret ends up in address calculation affecting a load or store, that +is a violation. If a secret affects a branch's condition, that is also a +violation. A secret variable location or register becomes a non-secret via +specific zeroization/sanitisation or by being declared ciphertext +(or otherwise no-longer-secret information). In essence, secrets can only +"touch" instructions on the Zkt list while they are secrets. + +==== Specific Instruction Rationale + +* HINT instruction forms (typically encodings with `rd=x0`) are excluded from +the data-independent time requirement. +* Floating point (F, D, Q, L extensions) are currently excluded from the +constant-time requirement as they have very few applications in standardised +cryptography. We may consider adding floating point add, sub, multiply as a +constant time requirement for some floating point extension in case a specific +algorithm (such as the PQC Signature algorithm Falcon) becomes critical. +* Cryptographers typically assume division to be variable-time (while +multiplication is constant time) and implement their Montgomery reduction +routines with that assumption. +* Zicsr, Zifencei are excluded. +* Some instructions are on the list simply because we see no harm in +including them in testing scope. + + +==== Programming Information + +For background information on secure programming "models", see: + +* Thomas Pornin: _"Why Constant-Time Crypto?"_ (A great introduction to timing assumptions.) https://www.bearssl.org/constanttime.html +* Jean-Philippe Aumasson: _"Guidelines for low-level cryptography software."_ +(A list of recommendations.) https://github.com/veorq/cryptocoding +* Peter Schwabe: _"Timing Attacks and Countermeasures."_ +(Lecture slides -- nice references.) +https://summerschool-croatia.cs.ru.nl/2016/slides/PeterSchwabe.pdf +* Adam Langley: _"ctgrind."_ (This is from 2010 but is still relevant.) +https://www.imperialviolet.org/2010/04/01/ctgrind.html +* Kris Kwiatkowski: _"Constant-time code verification with Memory Sanitizer."_ +https://www.amongbytes.com/post/20210709-testing-constant-time/ +* For early examples of timing attack vulnerabilities, see +https://www.kb.cert.org/vuls/id/997481 and related academic papers. + + +==== Zkt listings + +The following instructions are included in the `Zkt` subset +They are listed here grouped by their original parent extension. + +.Note to implementers +[NOTE, caption="SH"] +==== +You do not need to implement all of these instructions to implement `Zkt`. +Rather, every one of these instructions that the core does implement must +adhere to the requirements of `Zkt`. +==== + +===== RVI (Base Instruction Set) + +Only basic arithmetic and `slt*` (for carry computations) are included. +The data-independent timing requirement does not apply to HINT instruction +encoding forms of these instructions. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | lui _rd_, _imm_ | <<insns-lui>> +| ✓ | ✓ | auipc _rd_, _imm_ | <<insns-auipc>> +| ✓ | ✓ | addi _rd_, _rs1_, _imm_ | <<insns-addi>> +| ✓ | ✓ | slti _rd_, _rs1_, _imm_ | <<insns-slti>> +| ✓ | ✓ | sltiu _rd_, _rs1_, _imm_ | <<insns-sltiu>> +| ✓ | ✓ | xori _rd_, _rs1_, _imm_ | <<insns-xori>> +| ✓ | ✓ | ori _rd_, _rs1_, _imm_ | <<insns-ori>> +| ✓ | ✓ | andi _rd_, _rs1_, _imm_ | <<insns-andi>> +| ✓ | ✓ | slli _rd_, _rs1_, _imm_ | <<insns-slli>> +| ✓ | ✓ | srli _rd_, _rs1_, _imm_ | <<insns-srli>> +| ✓ | ✓ | srai _rd_, _rs1_, _imm_ | <<insns-srai>> +| ✓ | ✓ | add _rd_, _rs1_, _rs2_ | <<insns-add>> +| ✓ | ✓ | sub _rd_, _rs1_, _rs2_ | <<insns-sub>> +| ✓ | ✓ | sll _rd_, _rs1_, _rs2_ | <<insns-sll>> +| ✓ | ✓ | slt _rd_, _rs1_, _rs2_ | <<insns-slt>> +| ✓ | ✓ | sltu _rd_, _rs1_, _rs2_ | <<insns-sltu>> +| ✓ | ✓ | xor _rd_, _rs1_, _rs2_ | <<insns-xor>> +| ✓ | ✓ | srl _rd_, _rs1_, _rs2_ | <<insns-srl>> +| ✓ | ✓ | sra _rd_, _rs1_, _rs2_ | <<insns-sra>> +| ✓ | ✓ | or _rd_, _rs1_, _rs2_ | <<insns-or>> +| ✓ | ✓ | and _rd_, _rs1_, _rs2_ | <<insns-and>> +| | ✓ | addiw _rd_, _rs1_, _imm_ | <<insns-addiw>> +| | ✓ | slliw _rd_, _rs1_, _imm_ | <<insns-slliw>> +| | ✓ | srliw _rd_, _rs1_, _imm_ | <<insns-srliw>> +| | ✓ | sraiw _rd_, _rs1_, _imm_ | <<insns-sraiw>> +| | ✓ | addw _rd_, _rs1_, _rs2_ | <<insns-addw>> +| | ✓ | subw _rd_, _rs1_, _rs2_ | <<insns-subw>> +| | ✓ | sllw _rd_, _rs1_, _rs2_ | <<insns-sllw>> +| | ✓ | srlw _rd_, _rs1_, _rs2_ | <<insns-srlw>> +| | ✓ | sraw _rd_, _rs1_, _rs2_ | <<insns-sraw>> +|=== + +===== RVM (Multiply) + +Multiplication is included; division and remaindering excluded. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | mul _rd_, _rs1_, _rs2_ | <<insns-mul>> +| ✓ | ✓ | mulh _rd_, _rs1_, _rs2_ | <<insns-mulh>> +| ✓ | ✓ | mulhsu _rd_, _rs1_, _rs2_ | <<insns-mulhsu>> +| ✓ | ✓ | mulhu _rd_, _rs1_, _rs2_ | <<insns-mulhu>> +| | ✓ | mulw _rd_, _rs1_, _rs2_ | <<insns-mulw>> +|=== + +===== RVC (Compressed) + +Same criteria as in RVI. Organised by quadrants. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | c.nop | <<insns-c_nop>> +| ✓ | ✓ | c.addi | <<insns-c_addi>> +| | ✓ | c.addiw | <<insns-c_addiw>> +| ✓ | ✓ | c.lui | <<insns-c_lui>> +| ✓ | ✓ | c.srli | <<insns-c_srli>> +| ✓ | ✓ | c.srai | <<insns-c_srai>> +| ✓ | ✓ | c.andi | <<insns-c_andi>> +| ✓ | ✓ | c.sub | <<insns-c_sub>> +| ✓ | ✓ | c.xor | <<insns-c_xor>> +| ✓ | ✓ | c.or | <<insns-c_or>> +| ✓ | ✓ | c.and | <<insns-c_and>> +| | ✓ | c.subw | <<insns-c_subw>> +| | ✓ | c.addw | <<insns-c_addw>> +| ✓ | ✓ | c.slli | <<insns-c_slli>> +| ✓ | ✓ | c.mv | <<insns-c_mv>> +| ✓ | ✓ | c.add | <<insns-c_add>> +|=== + +===== RVK (Scalar Cryptography) + +All K-specific instructions are included. +Additionally, `seed` CSR latency should be independent of `ES16` state output +`entropy` bits, as that is a sensitive security parameter. +See <<crypto_scalar_appx_es_access>>. + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | | aes32dsi | <<insns-aes32dsi>> +| ✓ | | aes32dsmi | <<insns-aes32dsmi>> +| ✓ | | aes32esi | <<insns-aes32esi>> +| ✓ | | aes32esmi | <<insns-aes32esmi>> +| | ✓ | aes64ds | <<insns-aes64ds>> +| | ✓ | aes64dsm | <<insns-aes64dsm>> +| | ✓ | aes64es | <<insns-aes64es>> +| | ✓ | aes64esm | <<insns-aes64esm>> +| | ✓ | aes64im | <<insns-aes64im>> +| | ✓ | aes64ks1i | <<insns-aes64ks1i>> +| | ✓ | aes64ks2 | <<insns-aes64ks2>> +| ✓ | ✓ | sha256sig0 | <<insns-sha256sig0>> +| ✓ | ✓ | sha256sig1 | <<insns-sha256sig1>> +| ✓ | ✓ | sha256sum0 | <<insns-sha256sum0>> +| ✓ | ✓ | sha256sum1 | <<insns-sha256sum1>> +| ✓ | | sha512sig0h | <<insns-sha512sig0h>> +| ✓ | | sha512sig0l | <<insns-sha512sig0l>> +| ✓ | | sha512sig1h | <<insns-sha512sig1h>> +| ✓ | | sha512sig1l | <<insns-sha512sig1l>> +| ✓ | | sha512sum0r | <<insns-sha512sum0r>> +| ✓ | | sha512sum1r | <<insns-sha512sum1r>> +| | ✓ | sha512sig0 | <<insns-sha512sig0>> +| | ✓ | sha512sig1 | <<insns-sha512sig1>> +| | ✓ | sha512sum0 | <<insns-sha512sum0>> +| | ✓ | sha512sum1 | <<insns-sha512sum1>> +| ✓ | ✓ | sm3p0 | <<insns-sm3p0>> +| ✓ | ✓ | sm3p1 | <<insns-sm3p1>> +| ✓ | ✓ | sm4ed | <<insns-sm4ed>> +| ✓ | ✓ | sm4ks | <<insns-sm4ks>> +|=== + + +===== RVB (Bitmanip) + +The <<zbkb>>, <<zbkx>> and <<zbkx>> extensions are included in their entirety. + +.Note to implementers +[NOTE,caption="SH"] +==== +Recall that `rev`, `zip` and `unzip` are pseudo-instructions representing +specific instances of `grevi`, `shfli` and `unshfli` respectively. +==== + +[%header,cols="^1,^1,4,8"] +|=== +|RV32 +|RV64 +|Mnemonic +|Instruction + +| ✓ | ✓ | clmul | <<insns-clmul>> +| ✓ | ✓ | clmulh | <<insns-clmulh>> +| ✓ | ✓ | xperm4 | <<insns-xperm4>> +| ✓ | ✓ | xperm8 | <<insns-xperm8>> +| ✓ | ✓ | ror | <<insns-ror>> +| ✓ | ✓ | rol | <<insns-rol>> +| ✓ | ✓ | rori | <<insns-rori>> +| | ✓ | rorw | <<insns-rorw>> +| | ✓ | rolw | <<insns-rolw>> +| | ✓ | roriw | <<insns-roriw>> +| ✓ | ✓ | andn | <<insns-andn>> +| ✓ | ✓ | orn | <<insns-orn>> +| ✓ | ✓ | xnor | <<insns-xnor>> +| ✓ | ✓ | pack | <<insns-pack>> +| ✓ | ✓ | packh | <<insns-packh>> +| | ✓ | packw | <<insns-packw>> +| ✓ | ✓ | brev8 | <<insns-brev8>> +| ✓ | ✓ | rev8 | <<insns-rev8>> +| ✓ | | zip | <<insns-zip>> +| ✓ | | unzip | <<insns-unzip>> +|=== + +[[crypto_scalar_appx_rationale]] +=== Instruction Rationale + +This section contains various rationale, design notes and usage +recommendations for the instructions in the scalar cryptography +extension. It also tries to record how the designs of instructions were +derived, or where they were contributed from. + +==== AES Instructions + +The 32-bit instructions were derived from work in cite:[MJS:LWAES:20] and +contributed to the RISC-V cryptography extension. +The 64-bit instructions were developed collaboratively by task group +members on our mailing list. + +Supporting material, including rationale and a design space exploration +for all of the AES instructions in the specification can be found in the paper +_"link:https://doi.org/10.46586/tches.v2021.i1.109-136[The design of scalar AES Instruction Set Extensions for RISC-V]"_ cite:[MNPSW:20]. + + +==== SHA2 Instructions + +These instructions were developed based on academic +work at the University of Bristol as part of the XCrypto project +cite:[MPP:19], and contributed to the RISC-V cryptography extension. + +The RV32 SHA2-512 instructions were based on this work, and developed +in cite:[MJS:LWSHA:20], before being contributed in the same way. + +==== SM3 and SM4 Instructions + +The SM4 instructions were derived from work in cite:[MJS:LWAES:20], and +are hence very similar to the RV32 AES instructions. + +The SM3 instructions were inspired by the SHA2 instructions, and +based on development work done in cite:[MJS:LWSHA:20], before being +contributed to the RISC-V cryptography extension. + +[[crypto_scalar_zkb]] +==== Bitmanip Instructions for Cryptography + +Many of the primitive operations used in symmetric key cryptography +and cryptographic hash functions are well supported by the +RISC-V Bitmanip cite:[riscv:bitmanip:repo] extensions. + +NOTE: This section repeats much of the information in +<<zbkb>>, +<<zbkc>> +and +<<zbkx>>, +but includes more rationale. + +We proposed that the scalar cryptographic extension _reuse_ a +subset of the instructions from the Bitmanip extensions `Zb[abc]` directly. +Specifically, this would mean that +a core implementing +_either_ +the scalar cryptographic extensions, +_or_ +the `Zb[abc]`, +_or_ +both, +would be required to implement these instructions. + +===== Rotations + +---- +RV32, RV64: RV64 only: + ror rd, rs1, rs2 rorw rd, rs1, rs2 + rol rd, rs1, rs2 rolw rd, rs1, rs2 + rori rd, rs1, imm roriw rd, rs1, imm +---- + +See cite:[riscv:bitmanip:draft] (Section 3.1.1) for details of +these instructions. + +.Notes to software developers +[NOTE,caption="SH"] +==== +Standard bitwise rotation is a primitive operation in many block ciphers +and hash functions; it features particularly in the ARX (Add, Rotate, Xor) +class of block ciphers and stream ciphers. + +* Algorithms making use of 32-bit rotations: + SHA256, AES (Shift Rows), ChaCha20, SM3. +* Algorithms making use of 64-bit rotations: + SHA512, SHA3. +==== + +===== Bit & Byte Permutations + +---- +RV32: + brev8 rd, rs1 // grevi rd, rs1, 7 - Reverse bits in bytes + rev8 rd, rs1 // grevi rd, rs1, 24 - Reverse bytes in 32-bit word + +RV64: + brev8 rd, rs1 // grevi rd, rs1, 7 - Reverse bits in bytes + rev8 rd, rs1 // grevi rd, rs1, 56 - Reverse bytes in 64-bit word +---- + +The scalar cryptography extension provides the following instructions for +manipulating the bit and byte endianness of data. +They are all parameterisations of the Generalised Reverse with Immediate +(`grevi` instruction. +The scalar cryptography extension requires _only_ the above instances +of `grevi` be implemented, which can be invoked via their pseudo-ops. + +The full specification of the `grevi` instruction is available in +cite:[riscv:bitmanip:draft] (Section 2.2.2). + +.Notes to software developers +[NOTE,caption="SH"] +==== +Reversing bytes in words is very common in cryptography when setting a +standard endianness for input and output data. +Bit reversal within bytes is used for implementing the GHASH component +of Galois/Counter Mode (GCM) cite:[nist:gcm]. +==== + +---- +RV32: + zip rd, rs1 // shfli rd, rs1, 15 - Bit interleave + unzip rd, rs1 // unshfli rd, rs1, 15 - Bit de-interleave +---- + +The `zip` and `unzip` pseudo-ops are specific instances of +the more general `shfli` and `unshfli` instructions. +The scalar cryptography extension requires _only_ the above instances +of `[un]shfli` be implemented, which can be invoked via their +pseudo-ops. +Only RV32 implementations require these instructions. + +The full specification of the `shfli` instruction is available in +cite:[riscv:bitmanip:draft] (Section 2.2.3). + +.Notes to software developers +[NOTE,caption="SH"] +==== +These instructions perform a bit-interleave (or de-interleave) operation, and +are useful for implementing the 64-bit rotations in the +SHA3 cite:[nist:fips:202] algorithm on +a 32-bit architecture. +On RV64, the relevant operations in SHA3 can be done natively using +rotation instructions, so `zip` and `unzip` are not required. +==== + +===== Carry-less Multiply + +---- +RV32, RV64: + clmul rd, rs1, rs2 + clmulh rd, rs1, rs2 +---- + +See cite:[riscv:bitmanip:draft] (Section 2.6) for details of +this instruction. +See <<crypto_scalar_zkt>> for additional implementation +requirements for these instructions, related to data independent +execution latency. + +.Notes to software developers +[NOTE,caption="SH"] +==== +As is mentioned there, obvious cryptographic use-cases for carry-less +multiply are for Galois Counter Mode (GCM) block cipher operations. +GCM is recommended by NIST as a block cipher mode of operation +cite:[nist:gcm], and is the only _required_ mode for the TLS 1.3 +protocol. +==== + +===== Logic With Negate + +---- +RV32, RV64: + andn rd, rs1, rs2 + orn rd, rs1, rs2 + xnor rd, rs1, rs2 +---- + +See cite:[riscv:bitmanip:draft] (Section 2.1.3) for details of +these instructions. +These instructions are useful inside hash functions, block ciphers and +for implementing software based side-channel countermeasures like masking. +The `andn` instruction is also useful for constant time word-select +in systems without the ternary Bitmanip `cmov` instruction. + +.Notes to software developers +[NOTE,caption="SH"] +==== +In the context of Cryptography, these instructions are useful for: +SHA3/Keccak Chi step, +Bit-sliced function implementations, +Software based power/EM side-channel countermeasures based on masking. +==== + +===== Packing + +---- +RV32, RV64: RV64: + pack rd, rs1, rs2 packw rd, rs1, rs2 + packh rd, rs1, rs2 +---- + +See cite:[riscv:bitmanip:draft] (Section 2.1.4) for details of +these instructions. + +.Notes to software developers +[NOTE,caption="SH"] +==== +The `pack*` instructions are +useful for re-arranging halfwords within words, and +generally getting data into the right shape prior to applying transforms. +This is particularly useful for cryptographic algorithms which pass inputs +around as (potentially un-aligned) byte strings, but can operate on words +made out of those byte strings. +This occurs (for example) in AES when loading blocks and keys (which may not +be word aligned) into registers to perform the round functions. +==== + +===== Crossbar Permutation Instructions + +---- +RV32, RV64: + xperm4 rd, rs1, rs2 + xperm8 rd, rs1, rs2 +---- + +See cite:[riscv:bitmanip:draft] (Section 2.2.4) for a complete +description of this instruction. + +The `xperm4` instruction operates on nibbles. +`GPR[rs1]` contains a vector of `XLEN/4` 4-bit elements. +`GPR[rs2]` contains a vector of `XLEN/4` 4-bit indexes. +The result is each element in `GPR[rs2]` replaced by the indexed element +in `GPR[rs1]`, or zero if the index into `GPR[rs2]` is out of bounds. + +The `xperm8` instruction operates on bytes. +`GPR[rs1]` contains a vector of `XLEN/8` 8-bit elements. +`GPR[rs2]` contains a vector of `XLEN/8` 8-bit indexes. +The result is each element in `GPR[rs2]` replaced by the indexed element +in `GPR[rs1]`, or zero if the index into `GPR[rs2]` is out of bounds. + +.Notes to software developers +[NOTE,caption="SH"] +==== +The instruction can be used to implement arbitrary bit +permutations. +For cryptography, they can accelerate bit-sliced implementations, +permutation layers of block ciphers, masking based countermeasures +and SBox operations. + +Lightweight block ciphers using 4-bit SBoxes include: +PRESENT cite:[block:present], +Rectangle cite:[block:rectangle], +GIFT cite:[block:gift], +Twine cite:[block:twine], +Skinny, MANTIS cite:[block:skinny], +Midori cite:[block:midori]. + +National ciphers using 8-bit SBoxes include: +Camellia cite:[block:camellia] (Japan), +Aria cite:[block:aria] (Korea), +AES cite:[nist:fips:197] (USA, Belgium), +SM4 cite:[gbt:sm4] (China) +Kuznyechik (Russia). + +All of these SBoxes can be implemented efficiently, in constant +time, using the `xperm8` instruction +footnote:l[link:http://svn.clairexen.net/handicraft/2020/lut4perm/demo02.cc[]]. +Note that this technique is also suitable for masking based +side-channel countermeasures. +==== + +[[crypto_scalar_appx_es]] + +=== Entropy Source Rationale and Recommendations + +This *non-normative* appendix focuses on the rationale, security, +self-certification, and implementation aspects of entropy sources. Hence we +also discuss non-ISA system features that may be needed for cryptographic +standards compliance and security testing. + +==== Checklists for Design and Self-Certification + +The security of cryptographic systems is based on secret bits and keys. +These bits need to be random and originate from cryptographically secure +Random Bit Generators (RBGs). An Entropy Source (ES) is required to +construct secure RBGs. + +While entropy source implementations do not have to be certified +designs, RISC-V expects that they behave in a compatible manner and do not +create unnecessary security risks to users. Self-evaluation and testing +following appropriate security standards is usually needed to achieve this. + +* *ISA Architectural Tests.* Verify, to the extent possible, that RISC-V ISA + requirements in this specification are correctly implemented. This includes + the state transitions (<<crypto_scalar_es>> and + <<crypto_scalar_es_getnoise>>), access control + (<<crypto_scalar_es_access>>), and that `seed` ES16 `entropy` words + can only be read destructively. + The scope of RISC-V ISA architectural tests are those behaviors that + are independent of the physical entropy source details. A smoke test ES + module may be helpful in design phase. +* *Technical justification for entropy.* This may take the form of a + stochastic model or a heuristic argument that explains why the noise + source output is from a random, rather than pseudorandom (deterministic) + process, and is not easily predictable or externally observable. + A complete physical model is not necessary; research literature can be + cited. For example, one can show that a good ring oscillator noise derives + an amount of physical entropy from local, spontaneously occurring + Johnson-Nyquist thermal noise cite:[Sa21], and is therefore not merely + "random-looking". +* *Entropy Source Design Review.* An entropy source is more than a noise + source, and must have features such as health tests + (<<crypto_scalar_es_security_controls>>), + a conditioner (<<crypto_scalar_appx_es_intro-cond>>), and a security + boundary with clearly defined interfaces. One may tabulate the SHALL + statements of SP 800-90B cite:[TuBaKe:18], FIPS 140-3 Implementation + Guidance cite:[NICC21], AIS-31 cite:[KiSc11] or other standards being + used. Official and non-official checklist tables are available: + https://github.com/usnistgov/90B-Shall-Statements +* *Experimental Tests.* The raw noise source is subjected to entropy + estimation as defined in NIST 800-90B, Section 3 cite:[TuBaKe:18]. + The interface described in <<crypto_scalar_es_getnoise>> can used be to + record datasets for this purpose. One also needs to show experimentally + that the conditioner and health test components work appropriately to + meet the ES16 output entropy requirements of <<crypto_scalar_es_req>>. + For SP 800-90B, NIST has made a min-entropy estimation + package freely available: + https://github.com/usnistgov/SP800-90B_EntropyAssessment +* **Resilience.** Above physical engineering steps should consider the + operational environment of the device, which may be unexpected or + hostile (actively attempting to exploit vulnerabilities in the design). + +See <<crypto_scalar_appx_es_implementation>> for a discussion of various +implementation options. + +NOTE: It is one of the goals of the RISC-V Entropy Source specification +that a standard 90B Entropy Source Module or AIS-31 RNG IP may be licensed +from a third party and integrated with a RISC-V processor design. Compared +to older (FIPS 140-2) RNG and DRBG modules, an entropy source module may +have a relatively small area (just a few thousand NAND2 gate equivalent). +CMVP is introducing an "Entropy Source Validation Scope" which potentially +allows 90B validations to be re-used for different (FIPS 140-3) modules. + +==== Standards and Terminology + +As a fundamental security function, the generation of random numbers is +governed by numerous standards and technical evaluation methods, the main +ones being FIPS 140-3 cite:[NI19,NICC21] required for U.S. Federal use, +and Common Criteria Methodology cite:[Cr17] used in high-security evaluations +internationally. + +Note that FIPS 140-3 is a significantly updated standard compared +to its predecessor FIPS 140-2 and is only coming into use in the 2020s. + +These standards set many of the technical requirements for the RISC-V +entropy source design, and we use their terminology if possible. + + +[[crypto_scalar_es_fig_rng,reftext="TRNG Components"]] +==== +image::es_dataflow.svg[align="center",scaledwidth=50%] +The `seed` CSR provides an Entropy Source (ES) interface, not a stateful +random number generator. As a result, it can support arbitrary +security levels. Cryptographic (AES, SHA-2/3) ISA Extensions +can be used to construct high-speed DRBGs that are seeded from the +entropy source. +==== + +[[crypto_scalar_appx_es_intro-es]] +===== Entropy Source (ES) + +Entropy sources are built by sampling and processing data from a noise +source (<<crypto_scalar_appx_es_noise_sources>>). +We will only consider physical sources of true randomness in this work. +Since these are directly based on natural phenomena and are subject to +environmental conditions (which may be adversarial), they require features +that monitor the "health" and quality of those sources. + +The requirements for physical entropy sources are specified in +NIST SP 800-90B cite:[TuBaKe:18] (<<crypto_scalar_es_req_90b>>) +for U.S. Federal FIPS 140-3 cite:[NI19] evaluations and +in BSI AIS-31 cite:[KiSc01,KiSc11] (<<crypto_scalar_es_req_ptg2>>) +for high-security Common Criteria evaluations. +There is some divergence in the types of health tests and entropy metrics +mandated in these standards, and RISC-V enables support for both alternatives. + +[[crypto_scalar_appx_es_intro-cond]] +===== Conditioning: Cryptographic and Non-Cryptographic + +Raw physical randomness (noise) sources are rarely statistically +perfect, and some generate very large amounts of bits, which need to be +"debiased" and reduced to a smaller number of bits. This process is +called conditioning. A secure hash function is an example of a +cryptographic conditioner. It is important to note that even though +hashing may make any data look random, it does not increase its +entropy content. + +Non-cryptographic conditioners and extractors such as von Neumann's +"debiased coin tossing" cite:[Ne51] are easier to implement +efficiently but may reduce entropy content (in individual bits removed) +more than cryptographic hashes, which mix the input entropy very +efficiently. However, they do not require cryptanalytic or computational +hardness assumptions and are therefore inherently more future-proof. +See <<crypto_scalar_appx_es_noncrypto>> for a more detailed +discussion. + +[[crypto_scalar_appx_es_intro-prng]] +===== Pseudorandom Number Generator (PRNG) + +Pseudorandom Number Generators (PRNGs) use deterministic mathematical +formulas to create abundant random numbers from a smaller amount of +"seed" randomness. PRNGs are also divided into cryptographic and +non-cryptographic ones. + +Non-cryptographic PRNGs, such as LFSRs and the linear-congruential +generators found in many programming libraries, may generate statistically +satisfactory random numbers but must never be used for cryptographic +keying. This is because they are not designed to resist +_cryptanalysis_; it is usually possible to take some output and +mathematically derive the "seed" or the internal state of the PRNG +from it. This is a security problem since knowledge of the state +allows the attacker to compute future or past outputs. + +[[crypto_scalar_appx_es_intro-drbg]] +===== Deterministic Random Bit Generator (DRBG) + +Cryptographic PRNGs are also known as Deterministic Random Bit +Generators (DRBGs), a term used by SP 800-90A cite:[BaKe15]. A strong +cryptographic algorithm such as AES cite:[nist:fips:197] or SHA-2/3 +cite:[nist:fips:202,nist:fips:180:4] +is used to produce random bits from a seed. The secret +seed material is like a cryptographic key; determining the seed +from the DRBG output is as hard as breaking AES or a strong hash function. +This also illustrates that the seed/key needs to be long enough and +come from a trusted Entropy Source. The DRBG should still be frequently +refreshed (reseeded) for forward and backward security. + +==== Specific Rationale and Considerations + +===== (<<crypto_scalar_seed_csr>>) The `seed` CSR + +The interface was designed to be simple so that a vendor- and +device-independent driver component (e.g., in Linux kernel, +embedded firmware, or a cryptographic library) may use `seed` to +generate truly random bits. + +An entropy source does not require a high-bandwidth interface; +a single DRBG source initialization only requires 512 bits +(256 bits of entropy), and DRBG output can be shared by any number of +callers. Once initiated, a DRBG requires new entropy only to mitigate +the risk of state compromise. + +From a security perspective, it is essential that the side effect of +flushing the secret entropy bits occurs upon reading. Hence we mandate +a write operation on this particular CSR. + +A blocking instruction may have been easier to use, but most users should +be querying a (D)RBG instead of an entropy source. +Without a polling-style mechanism, the entropy source could hang for +thousands of cycles under some circumstances. A `wfi` ot `pause` +mechanism (at least potentially) allows energy-saving sleep on MCUs +and context switching on higher-end CPUs. + +The reason for the particular `OPST = seed[31:0]` two-bit mechanism is to +provide redundancy. The "fault" bit combinations `11` (`DEAD`) and `00` +(`BIST`) are more likely for electrical reasons if feature discovery fails +and the entropy source is actually not available. + +The 16-bit bandwidth was a compromise motivated by the desire to +provide redundancy in the return value, some protection against +potential Power/EM leakage (further alleviated by the 2:1 cryptographic +conditioning discussed in <<crypto_scalar_appx_es_crypto-cond>>), +and the desire to have all of the bits "in the same place" on +both RV32 and RV64 architectures for programming convenience. + +===== (<<crypto_scalar_es_req_90b>>) NIST SP 800-90B + +SP 800-90C cite:[BaKeRo:21] states that each conditioned block of n bits +is required to have n+64 bits of input entropy to attain full entropy. +Hence NIST SP 800-90B cite:[TuBaKe:18] min-entropy assessment must +guarantee at least 128 + 64 = 192 bits input entropy per 256-bit block +( cite:[BaKeRo:21], Sections 4.1. and 4.3.2 ). +Only then a hashing of 16 * 16 = 256 bits from the entropy source +will produce the desired 128 bits of full entropy. This follows from +the specific requirements, threat model, and distinguishability proof +contained in SP 800-90C cite:[BaKeRo:21], Appendix A. +The implied min-entropy rate is 192/256=12/16=0.75. The expected +Shannon entropy is much larger. + +In FIPS 140-3 / SP 800-90 classification, an RBG2(P) construction is a +cryptographically secure RBG with continuous access to a physical entropy +source (`seed`) and output generated by a fully seeded, secure DRBG. +The entropy source can also be used to build RBG3 +full entropy sources cite:[BaKeRo:21]. The concatenation of output words +corresponds to the `Get_ES_Bitstring` function. + +The 128-bit output block size was selected because that is the output +size of the CBC-MAC conditioner specified in Appendix F of cite:[TuBaKe:18] +and also the smallest key size we expect to see in applications. + +If NIST SP 800-90B certification is chosen, the entropy source +should implement at least the health tests defined in +Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive +proportion test, or show that the same flaws will be detected +by vendor-defined tests. + +===== (<<crypto_scalar_es_req_ptg2>>) BSI AIS-31 + +PTG.2 is one of the security and functionality classes defined in +BSI AIS 20/31 cite:[KiSc11]. The PTG.2 source requirements work as a +building block for other types of BSI generators (e.g., DRBGs, or +PTG.3 TRNG with appropriate software post-processing). + +For validation purposes, the PTG.2 requirements may be mapped to +security controls T1-3 (<<crypto_scalar_es_security_controls>>) and the +interface as follows: + +* P1 *[PTG.2.1]* Start-up tests map to T1 and reset-triggered (on-demand) +`BIST` tests. +* P2 *[PTG.2.2]* Continuous testing total failure maps to T2 and the +`DEAD` state. +* P3 *[PTG.2.3]* Online tests are continuous tests of T2 – entropy output +is prevented in the `BIST` state. +* P4 *[PTG.2.4]* Is related to the design of effective entropy source +health tests, which we encourage. +* P5 *[PTG.2.5]* Raw random sequence may be checked via the GetNoise +interface (<<crypto_scalar_es_getnoise>>). +* P6 *[PTG.2.6]* Test Procedure A cite:[KiSc11] (Sect 2.4.4.1) is a +part of the evaluation process, and we suggest self-evaluation using these +tests even if AIS-31 certification is not sought. +* P7 *[PTG.2.7]* Average Shannon entropy of "internal random bits" +exceeds 0.997. + +Note how P7 concerns Shannon entropy, not min-entropy as with NIST +sources. Hence the min-entropy requirement needs to be also stated. +PTG.2 modules built and certified to the AIS-31 standard can also meet the +"full entropy" condition after 2:1 cryptographic conditioning, but not +necessarily so. The technical validation process is somewhat different. + +===== (<<crypto_scalar_es_req_virt>>) Virtual Sources + +All sources that are not direct physical sources (meeting the SP 800-90B +or the AIS-31 PTG.2 requirements) need to meet the security requirements +of virtual entropy sources. It is assumed that a virtual entropy source +is not a limiting, shared bandwidth resource (but a software DRBG). + +DRBGs can be used to feed other (virtual) DRBGs, but that does not +increase the absolute amount of entropy in the system. +The entropy source must be able to support current and future security +standards and applications. The 256-bit requirement maps to +"Category 5" of NIST Post-Quantum Cryptography (4.A.5 +"Security Strength Categories" in cite:[NI16]) and TOP SECRET schemes +in Suite B and the newer U.S. Government CNSA Suite cite:[NS15]. + +[[crypto_scalar_appx_es_access]] +===== (<<crypto_scalar_es_access>>) Security Considerations for Direct Hardware Access + +The ISA implementation and system design must try to ensure that the +hardware-software interface minimizes avenues for adversarial +information flow even if not explicitly forbidden in the specification. + +For security, virtualization requires both conditioning and DRBG processing +of physical entropy output. It is recommended if a single physical entropy +source is shared between multiple different virtual machnies or if the +guest OS is untrusted. A virtual entropy source is significantly more +resistant to depletion attacks and also lessens the risk from covert channels. + +The direct `mseccfg.[s,u]seed` option allows one to draw a security boundary +around a component in relation to Sensitive Security Parameter (SSP) flows, +even if that component is not in M mode. This is +helpful when implementing trusted enclaves. Such modules can enforce the +entire key lifecycle from birth (in the entropy source) to death +(zeroization) to occur without the key being passed across the boundary +to external code. + +*Depletion.* +Active polling may deny the entropy source to another simultaneously +running consumer. This can (for example) delay the instantiation of that +virtual machine if it requires entropy to initialize fully. + +*Covert Channels.* +Direct access to a component such as the entropy source can be used to +establish communication channels across security boundaries. Active +polling from one consumer makes the resource unavailable WAIT instead of +ES16 to another (which is polling infrequently). Such interactions can +be used to establish low-bandwidth channels. + +*Hardware Fingerprinting.* +An entropy source (and its noise source circuits) may have a uniquely +identifiable hardware "signature." This can be harmless or even useful +in some applications (as random sources may exhibit Physically Un-clonable +Function (PUF) -like features) +but highly undesirable in others (anonymized virtualized environments +and enclaves). A DRBG masks such statistical features. + +*Side Channels.* +Some of the most devastating practical attacks against real-life +cryptosystems have used inconsequential-looking additional +information, such as padding error messages cite:[BaFoKa:12] +or timing information cite:[MoSuEi:20]. + +We urge implementers against creating unnecessary information flows +via status or custom bits or to allow any other mechanism to disable or +affect the entropy source output. All information flows and interaction +mechanisms must be considered from an adversarial viewpoint: +the fewer the better. + +As an example of side-channel analysis, we note that the entropy +polling interface is typically not "constant time." One needs to +analyze what kind of information is revealed via the timing oracle; +one way of doing it is to model `seed` as a rejection +sampler. Such a timing oracle can reveal information about the noise +source type and entropy source usage, but not about the random output +`entropy` bits themselves. If it does, additional countermeasures are +necessary. + +[[crypto_scalar_es_security_controls]] +==== Security Controls and Health Tests + +The primary purpose of a cryptographic entropy source is to produce +secret keying material. In almost all cases, a hardware entropy source +must implement appropriate _security controls_ to guarantee +unpredictability, prevent leakage, detect attacks, and deny adversarial +control over the entropy output or ts generation mechanism. Explicit +security controls are required for security testing and certification. + +Many of the security controls built into the device are called "health +checks." Health checks can take the form of integrity checks, start-up +tests, and on-demand tests. These tests can be implemented in hardware +or firmware, typically both. Several are mandated by standards such as +NIST SP 800-90B cite:[NI19]. +The choice of appropriate health tests depends on the +certification target, system architecture, threat model, entropy +source type, and other factors. + +Health checks are not intended for hardware diagnostics but for detecting +security issues. Hence the default action in case of a failure should be +aimed at damage control: Limiting further output and preventing weak +crypto keys from being generated. + +We discuss three specific testing requirements T1-T3. The testing requirement +follows from the definition of an Entropy Source; without it, the module is +simply a noise source and can't be trusted to safely generate keying material. + +===== T1: On-demand testing + +A sequence of simple tests is invoked via resetting, rebooting, or +powering up the hardware (not an ISA signal). The implementation will +simply return `BIST` during the initial start-up self-test period; +in any case, the driver must wait for them to finish before starting +cryptographic operations. Upon failure, the entropy source will enter +a no-output `DEAD` state. + +*Rationale.* +Interaction with hardware self-test mechanisms +from the software side should be minimal; the term "on-demand" does not +mean that the end-user or application program should be able to invoke +them in the field (the term is a throwback to an age of discrete, +non-autonomous crypto devices with human operators). + +===== T2: Continuous checks + +If an error is detected in continuous tests or +environmental sensors, the entropy source will enter a no-output state. +We define that a non-critical alarm is signaled if the entropy source +returns to `BIST` state from live (`WAIT` or `ES16`) states. Critical +failures will result in `DEAD` state immediately. A hardware-based +continuous testing mechanism must not make statistical information +externally available, and it must be zeroized periodically or upon +demand via reset, power-up, or similar signal. + +*Rationale.* +Physical attacks can occur while the device is running. The design +should avoid guiding such active attacks by revealing detailed +status information. Upon detection of an attack, the default action +should be aimed at damage control -- to prevent weak crypto keys from +being generated. + +The statistical nature of some tests makes "type-1" false +positives a possibility. There may also be requirements for signaling +of non-fatal alarms; AIS 31 specifies "noise alarms" that can go off +with non-negligible probability even if the device is functioning +correctly; these can be signaled with `BIST`. +There rarely is anything that can or should be done about a non-fatal +alarm condition in an operator-free, autonomous system. + +The state of statistical runtime health checks (such as counters) +is potentially correlated with some secret keying material, hence +the zeroization requirement. + +===== T3: Fatal error states + +Since the security of most cryptographic operations depends on the +entropy source, a system-wide "default deny" security policy approach +is appropriate for most entropy source failures. A hardware test failure +should at least result in the `DEAD` state and possibly reset/halt. +It’s a show stopper: The entropy source (or its cryptographic client +application) _must not_ be allowed to run if its secure operation +can’t be guaranteed. + +*Rationale.* +These tests can complement other integrity and tamper resistance +mechanisms (See Chapter 18 of cite:[An20] for examples). + +Some hardware random generators are, by their physical construction, +exposed to relatively non-adversarial environmental and manufacturing +issues. However, even such "innocent" failure modes may indicate +a _fault attack_ cite:[KaScVe13] and therefore should be addressed +as a system integrity failure rather than as a diagnostic issue. + +Security architects will understand to use +permanent or hard-to-recover "security-fuse" lockdowns only if the +threshold of a test is such that the probability of false-positive is +negligible over the entire device lifetime. + +===== Information Flows + +Some of the most devastating practical attacks +against real-life cryptosystems have used inconsequential-looking +additional information, such as padding error messages cite:[BaFoKa:12] +or timing information cite:[MoSuEi:20]. In cryptography, such +out-of-band information sources are called "oracles." + +To guarantee that no sensitive data is read twice and that different +callers don’t get correlated output, it is required that hardware +implements _wipe-on-read_ on the randomness pathway during each read +(successful poll). For the same reasons, only complete and fully +processed random words shall be made available via `entropy` (ES16 status +of `seed`). + +This also applies to the raw noise source. The raw source interface has +been delegated to an optional vendor-specific test interface. +Importantly the test interface and the main interface should not be +operational at the same time. + +[quote, NIST SP 800-90B, Noise Source Requirements] +The noise source state shall be protected from adversarial +knowledge or influence to the greatest extent possible. The methods +used for this shall be documented, including a description of the +(conceptual) security boundarys role in protecting the noise source +from adversarial observation or influence. + +An entropy source is a singular resource, subject to depletion +and also covert channels cite:[EvPo16]. Observation of the entropy +can be the same as the observation of the noise source output, as +cryptographic conditioning is mandatory only as a post-processing step. +SP 800-90B and other security standards mandate protection of +noise bits from observation and also influence. + +[[crypto_scalar_appx_es_implementation]] +==== Implementation Strategies + +As a general rule, RISC-V specifies the ISA only. We provide some +additional suggestions so that portable, vendor-independent middleware +and kernel components can be created. The actual hardware implementation +and certification are left to vendors and circuit designers; +the discussion in this Section is purely informational. + +When considering implementation options and trade-offs, one must look +at the entire information flow. + +. *A Noise Source* generates private, unpredictable signals + from stable and well-understood physical random events. +. *Sampling* digitizes the noise signal into a raw stream of + bits. This raw data also needs to be protected by the design. +. *Continuous health tests* ensure that the noise source + and its environment meet their operational parameters. +. *Non-cryptographic conditioners* remove much of the bias + and correlation in input noise. +. *Cryptographic conditioners* produce full entropy + output, completely indistinguishable from ideal random. +. *DRBG* takes in `>=256` bits of seed entropy as keying + material and uses a "one way" cryptographic process to rapidly + generate bits on demand (without revealing the seed/state). + +Steps 1-4 (possibly 5) are considered to be part of the Entropy +Source (ES) and provided by the `seed` CSR. +Adding the software-side cryptographic steps 5-6 and control logic +complements it into a True Random Number Generator (TRNG). + +[[crypto_scalar_appx_es_noise_sources]] +===== Ring Oscillators + +We will give some examples of common noise sources that can be +implemented in the processor itself (using standard cells). + +The most common entropy source type in production use today is +based on "free running" ring oscillators and their timing jitter. +Here, an odd number of inverters is connected into a loop from which +noise source bits are sampled in relation to a reference clock +cite:[BaLuMi:11]. The sampled bit sequence may be expected to be +relatively uncorrelated (close to IID) if the sample rate is suitably low +cite:[KiSc11]. However, further processing is usually required. + +AMD cite:[AM17], ARM cite:[AR17], and IBM cite:[LiBaBo:13] are +examples of ring oscillator TRNGs intended for high-security +applications. + +There are related metastability-based generator designs such as +Transition Effect Ring Oscillator (TERO) cite:[VaDr10]. +The differential/feedback Intel construction cite:[HaKoMa12] is slightly +different but also falls into the same general metastable +oscillator-based category. + +The main benefits of ring oscillators are: (1) They can be implemented +with standard cell libraries without external components -- +and even on FPGAs cite:[VaFiAu:10], (2) there is an established theory +for their behavior cite:[HaLe98,HaLiLe99,BaLuMi:11], and (3) ample +precedent exists for testing and certifying them at the highest security +levels. + +Ring oscillators also have well-known implementation pitfalls. +Their output is sometimes highly dependent on temperature, +which must be taken into account in testing and modeling. +If the ring oscillator construction is parallelized, it is important +that the number of stages and/or inverters in each chain is suitable to +avoid entropy reduction due to harmonic "Huyghens synchronization" +cite:[Ba86]. +Such harmonics can also be inserted maliciously in a frequency +injection attack, which can have devastating results cite:[MaMo09]. +Countermeasures are related to circuit design; environmental sensors, +electrical filters, and usage of a differential oscillator may help. + +===== Shot Noise + +A category of random sources consisting of discrete events +and modeled as a Poisson process is called "shot noise." +There's a long-established precedent of certifying them; the +AIS 31 document cite:[KiSc11] itself offers reference designs based on +noisy diodes. Shot noise sources are often more resistant to +temperature changes than ring oscillators. +Some of these generators can also be fully implemented with standard +cells (The Rambus / Inside Secure generic TRNG IP cite:[Ra20] is +described as a Shot Noise generator). + +===== Other types of noise + +It may be possible to certify more exotic noise sources and designs, +although their stochastic model needs to be equally well understood, +and their CPU interfaces must be secure. +See <<crypto_scalar_appx_es_quantum>> for a discussion of Quantum +entropy sources. + +[[crypto_scalar_appx_es_cont-tests]] +===== Continuous Health Tests + +Health monitoring requires some state information related +to the noise source to be maintained. The tests should be designed +in a way that a specific number of samples guarantees a state +flush (no hung states). We suggest flush size `W =< 1024` to +match with the NIST SP 800-90B required tests (See Section 4.4 in +cite:[TuBaKe:18]). The state is also fully zeroized in a system reset. + +The two mandatory tests can be built with minimal circuitry. +Full histograms are not required, only simple counter registers: +repetition count, window count, and sample count. +Repetition count is reset every time the output sample value +changes; if the count reaches a certain cutoff limit, a noise alarm +(`BIST`) or failure (`DEAD`) is signaled. The window counter is +used to save every W'th output (typically `W` in { 512, 1024 }). +The frequency of this reference sample in the following window is +counted; cutoff values are defined in the standard. We see that the +structure of the mandatory tests is such that, if well implemented, +no information is carried beyond a limit of `W` samples. + +Section 4.5 of cite:[TuBaKe:18] explicitly permits additional +developer-defined tests, and several more were defined in early +versions of FIPS 140-1 before being "crossed out." The choice +of additional tests depends on the nature and implementation of the +physical source. + +Especially if a non-cryptographic conditioner is used in hardware, +it is possible that the AIS 31 cite:[KiSc11] online tests are +implemented by driver software. They can also be implemented in hardware. +For some security profiles, AIS 31 mandates that their tolerances are +set in a way that the probability of an alarm is at least 10^-6^ +yearly under "normal usage." Such requirements are problematic +in modern applications since their probability is too high for +critical systems. + +There rarely is anything that can or should be done about a non-fatal +alarm condition in an operator-free, autonomous system. However, +AIS 31 allows the DRBG component to keep running despite a failure in +its Entropy Source, so we suggest re-entering a temporary `BIST` +state (<<crypto_scalar_es_security_controls>>) to signal a non-fatal +statistical error if such (non-actionable) signaling is necessary. +Drivers and applications can react to this appropriately (or simply +log it), but it will not directly affect the availability of the TRNG. +A permanent error condition should result in `DEAD` state. + +[[crypto_scalar_appx_es_noncrypto]] +===== Non-cryptographic Conditioners + +As noted in <<crypto_scalar_appx_es_intro-cond>>, physical randomness +sources generally require a post-processing step called _conditioning_ to +meet the desired quality requirements, which are outlined in +<<crypto_scalar_es_req>>. + +The approach taken in this interface is to allow a combination of +non-cryptographic and cryptographic filtering to take place. The +first stage (hardware) merely needs to be able to distill the entropy +comfortably above the necessary level. + +* One may take a set of bits from a noise source and XOR them + together to produce a less biased (and more independent) bit. + However, such an XOR may introduce "pseudorandomness" and + make the output difficult to analyze. +* The von Neumann extractor cite:[Ne51] looks at consecutive + pairs of bits, rejects 00 and 11, and outputs 0 or 1 for + 01 and 10, respectively. It will reduce the number of bits to + less than 25% of the original, but the output is provably unbiased + (assuming independence). +* Blum's extractor cite:[Bl86] can be used on sources + whose behavior resembles N-state Markov chains. If its + assumptions hold, it also removes dependencies, creating an + independent and identically distributed (IID) source. +* Other linear and non-linear correctors such as those + discussed by Dichtl and Lacharme cite:[La08]. + +Note that the hardware may also implement a full cryptographic conditioner +in the entropy source, even though the software driver still needs +a cryptographic conditioner, too (<<crypto_scalar_es_req>>). + +*Rationale:* +The main advantage of non-cryptographic extractors is in their +energy efficiency, relative simplicity, and amenability to mathematical +analysis. If well designed, they can be evaluated in +conjunction with a stochastic model of the noise source itself. +They do not require computational hardness assumptions. + +[[crypto_scalar_appx_es_crypto-cond]] +===== Cryptographic Conditioners + +For secure use, cryptographic conditioners are always required on the +software side of the ISA boundary. They may also be implemented on the +hardware side if necessary. In any case, the `entropy` ES16 output must +always be compressed 2:1 (or more) before being used as keying material +or considered "full entropy." + +Examples of cryptographic conditioners include the random pool of the +Linux operating system, secure hash functions (SHA-2/3, SHAKE +cite:[nist:fips:202,nist:fips:180:4]), and the AES / CBC-MAC +construction in Appendix F, SP 800-90B cite:[TuBaKe:18]. + +In some constructions, such as the Linux RNG and SHA-3/SHAKE +cite:[nist:fips:202] based generators, the cryptographic conditioning +and output (DRBG) generation are provided by the same component. + +*Rationale:* +For many low-power targets constructions the type of hardware AES CBC-MAC +conditioner used by Intel cite:[Me18] and AMD cite:[AM17] would be too +complex and energy-hungry to implement solely to serve the `seed` CSR. +On the other hand, simpler non-cryptographic conditioners may be too +wasteful on input entropy if high-quality random output is required -- +(ARM TrustZone TRBG cite:[AR17] outputs only 10Kbit/sec at 200 MHz.) +Hence a resource-saving compromise is made between hardware and software +generation. + +[[crypto_scalar_appx_es_drbgs]] +===== The Final Random: DRBGs + +All random bits reaching end users and applications must come from a +cryptographic DRBG. These are generally implemented by the driver +component in software. The RISC-V AES and SHA instruction set extensions +should be used if available since they offer additional +security features such as timing attack resistance. + +Currently recommended DRBGs are defined in NIST SP 800-90A (Rev 1) +cite:[BaKe15]: `CTR_DRBG`, `Hash_DRBG`, and `HMAC_DRBG`. +Certification often requires known answer tests (KATs) for the symmetric +components and the DRBG as a whole. These are significantly easier to +implement in software than in hardware. In addition to the directly +certifiable SP 800-90A DRBGs, a Linux-style random pool construction +based on ChaCha20 cite:[Mu20] can be used, or an appropriate construction +based on SHAKE256 cite:[nist:fips:202]. + +These are just recommendations; programmers can adjust the usage of the +CPU Entropy Source to meet future requirements. + +[[crypto_scalar_appx_es_quantum]] +===== Quantum vs. Classical Random + +[quote,U.K. NCSC QRNG Guidance, March 2020] +The NCSC believes that classical RNGs will continue to +meet our needs for government and military applications for the +foreseeable future. + +A Quantum Random Number Generator (QRNG) is a TRNG whose source of +randomness can be unambiguously identified to be a specific +quantum phenomenon such as quantum state superposition, quantum state +entanglement, Heisenberg uncertainty, quantum tunneling, spontaneous +emission, or radioactive decay cite:[IT19]. + +Direct quantum entropy is theoretically the best possible kind of +entropy. A typical TRNG based on electronic noise is also largely +based on quantum phenomena and is equally unpredictable - the difference +is that the relative amount of quantum and classical physics involved is +difficult to quantify for a classical TRNG. + +QRNGs are designed in a way that allows the amount of quantum-origin +entropy to be modeled and estimated. This distinction is important in +the security model used by QKD (Quantum Key Distribution) security +mechanisms which can be used to protect the physical layer (such as +fiber optic cables) against interception by using quantum mechanical +effects directly. + +This security model means that many of the available QRNG devices do +not use cryptographic conditioning and may fail cryptographic statistical +requirements cite:[HuHe20]. Many implementers may consider them to be +entropy sources instead. + +Relatively little research has gone into QRNG implementation security, +but many QRNG designs are arguably more susceptible to leakage than +classical generators (such as ring oscillators) as they tend to employ +external components and mixed materials. As an example, amplification of +a photon detector signal may be observable in power analysis, +which classical noise-based sources are designed to resist. + +===== Post-Quantum Cryptography + +PQC public-key cryptography standards cite:[NI16] do not require +quantum-origin randomness, just sufficiently secure keying material. +Recall that cryptography aims to protect the confidentiality and +integrity of data itself and does not place any requirements on +the physical communication channel (like QKD). + +Classical good-quality TRNGs are perfectly suitable +for generating the secret keys for PQC protocols that are hard for +quantum computers to break but implementable on classical computers. +What matters in cryptography is that the secret keys have enough true +randomness (entropy) and that they are generated and stored securely. + +Of course, one must avoid DRBGs that are based on problems that are +easily solvable with quantum computers, such as factoring cite:[Sh94] +in the case of the Blum-Blum-Shub generator cite:[BlBlSh86]. +Most symmetric algorithms are not affected as the best quantum +attacks are still exponential to key size cite:[Gr96]. + +As an example, the original Intel RNG cite:[Me18], whose output generation +is based on AES-128, can be attacked using Grover's algorithm +with approximately square-root effort cite:[JaNaRo:20]. +While even "64-bit" quantum security is extremely difficult to +break, many applications specify a higher security requirement. +NIST cite:[NI16] defines AES-128 to be "Category 1" equivalent +post-quantum security, while AES-256 is "Category 5" (highest). +We avoid this possible future issue by exposing direct access +to the entropy source which can derive its security from +information-theoretic assumptions only. + +[[crypto_scalar_es_getnoise]] +==== Suggested GetNoise Test Interface + +Compliance testing, characterization, and configuration of entropy sources +require access to raw, unconditioned noise samples. This conceptual test +interface is named GetNoise in Section 2.3.2 of NIST SP 800-90B +cite:[TuBaKe:18]. + +Since this type of interface is both necessary for security testing +and also constitutes a potential backdoor to the cryptographic key generation +process, we define a safety behavior that compliant implementations can +have for temporarily disabling the entropy source `seed` CSR interface during +test. + +In order for shared RISC-V self-certification scripts (and drivers) to +accommodate the test interface in a secure fashion, we suggest that it is +implemented as a custom, M-mode only CSR, denoted here as `mnoise`. + +This non-normative interface is not intended to be used as a source of +randomness or for other production use. +We define the semantics for single bit for this interface, `mnoise[31]`, +which is named `NOISE_TEST`, which will affect the behavior of `seed` +if implemented. + +When `NOISE_TEST = 1` in `mnoise`, the `seed` CSR must not return +anything via `ES16`; it should be in `BIST` state unless the source +is `DEAD`. When `NOISE_TEST` is again disabled, the entropy source +shall return from `BIST` via an appropriate zeroization and self-test +mechanism. + +The behavior of other input and output bits is largely left to the vendor +(as they depend on the technical details of the physical entropy source), +as is the address of the custom `mnoise` CSR. Other contents and behavior of the +CSR only can be interpreted in the context of `mvendorid`, `marchid`, and +`mimpid` CSR identifiers. + +When not implemented (e.g., in virtual machines), `mnoise` can permanently +read zero (`0x00000000`) and ignore writes. +When available, but `NOISE_TEST = 0`, `mnoise` can return a +nonzero constant (e.g. `0x00000001`) but no noise samples. + +[[crypto_scalar_es_noistest,reftext="Custom Entropy Test Mode Diagram"]] +==== +image::es_noisetest.svg[title="Entropy source can't be read in test mode.", align="center",scaledwidth=66%] +In `NOISE_TEST` mode, the WAIT and ES16 states are unreachable, +and no entropy is output. Implementation of test interfaces that directly +affect ES16 entropy output from the `seed` CSR interface is discouraged. +Such vendor test interfaces have been exploited in attacks. For example, +an ECDSA cite:[nist:fips:186:4] signature process without sufficient +entropy will not only create an insecure signature but can also reveal +the secret signing key, that can be used for authentication forgeries by +attackers. Hence even a temporary lapse in `entropy` security may have serious +security implications. +==== + +[[crypto_scalar_appx_materials]] +=== Supplementary Materials + +While this document contains the specifications for the RISC-V cryptography +extensions, numerous supplementary materials and example codes have +also been developed. +All of the materials related to the RISC-V Cryptography +extension live in a Github Repository, located at +https://github.com/riscv/riscv-crypto + +* `doc/` + Contains the source code for this document. + +* `doc/supp/` + Contains supplementary information and recommendations for implementers of + software and hardware. + +* `benchmarks/` + Example software implementations. + +* `rtl/` + Example Verilog implementations of each instruction. + +* `sail/` + Formal model implementations in Sail. + +[[crypto_scalar_appx_sail]] +=== Supporting Sail Code + +This section contains the supporting Sail code referenced by the +instruction descriptions throughout the specification. +The +link:https://github.com/rems-project/sail/blob/sail2/manual.pdf[Sail Manual] +is recommended reading in order to best understand the supporting code. + +[source,sail] +---- +/* Auxiliary function for performing GF multiplicaiton */ +val xt2 : bits(8) -> bits(8) +function xt2(x) = { + (x << 1) ^ (if bit_to_bool(x[7]) then 0x1b else 0x00) +} + +val xt3 : bits(8) -> bits(8) +function xt3(x) = x ^ xt2(x) + +/* Multiply 8-bit field element by 4-bit value for AES MixCols step */ +val gfmul : (bits(8), bits(4)) -> bits(8) +function gfmul( x, y) = { + (if bit_to_bool(y[0]) then x else 0x00) ^ + (if bit_to_bool(y[1]) then xt2( x) else 0x00) ^ + (if bit_to_bool(y[2]) then xt2(xt2( x)) else 0x00) ^ + (if bit_to_bool(y[3]) then xt2(xt2(xt2(x))) else 0x00) +} + +/* 8-bit to 32-bit partial AES Mix Colum - forwards */ +val aes_mixcolumn_byte_fwd : bits(8) -> bits(32) +function aes_mixcolumn_byte_fwd(so) = { + gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2) +} + +/* 8-bit to 32-bit partial AES Mix Colum - inverse*/ +val aes_mixcolumn_byte_inv : bits(8) -> bits(32) +function aes_mixcolumn_byte_inv(so) = { + gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe) +} + +/* 32-bit to 32-bit AES forward MixColumn */ +val aes_mixcolumn_fwd : bits(32) -> bits(32) +function aes_mixcolumn_fwd(x) = { + let s0 : bits (8) = x[ 7.. 0]; + let s1 : bits (8) = x[15.. 8]; + let s2 : bits (8) = x[23..16]; + let s3 : bits (8) = x[31..24]; + let b0 : bits (8) = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3); + let b1 : bits (8) = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3); + let b2 : bits (8) = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3); + let b3 : bits (8) = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3); + b3 @ b2 @ b1 @ b0 /* Return value */ +} + +/* 32-bit to 32-bit AES inverse MixColumn */ +val aes_mixcolumn_inv : bits(32) -> bits(32) +function aes_mixcolumn_inv(x) = { + let s0 : bits (8) = x[ 7.. 0]; + let s1 : bits (8) = x[15.. 8]; + let s2 : bits (8) = x[23..16]; + let s3 : bits (8) = x[31..24]; + let b0 : bits (8) = gfmul(s0, 0xE) ^ gfmul(s1, 0xB) ^ gfmul(s2, 0xD) ^ gfmul(s3, 0x9); + let b1 : bits (8) = gfmul(s0, 0x9) ^ gfmul(s1, 0xE) ^ gfmul(s2, 0xB) ^ gfmul(s3, 0xD); + let b2 : bits (8) = gfmul(s0, 0xD) ^ gfmul(s1, 0x9) ^ gfmul(s2, 0xE) ^ gfmul(s3, 0xB); + let b3 : bits (8) = gfmul(s0, 0xB) ^ gfmul(s1, 0xD) ^ gfmul(s2, 0x9) ^ gfmul(s3, 0xE); + b3 @ b2 @ b1 @ b0 /* Return value */ +} + +/* Turn a round number into a round constant for AES. Note that the + AES64KS1I instruction is defined such that the r argument is always + in the range 0x0..0xA. Values of rnum outside the range 0x0..0xA + do not decode to the AES64KS1I instruction. The 0xA case is used + specifically for the AES-256 KeySchedule, and this function is never + called in that case. */ +val aes_decode_rcon : bits(4) -> bits(32) +function aes_decode_rcon(r) = { + assert(r <_u 0xA); + match r { + 0x0 => 0x00000001, + 0x1 => 0x00000002, + 0x2 => 0x00000004, + 0x3 => 0x00000008, + 0x4 => 0x00000010, + 0x5 => 0x00000020, + 0x6 => 0x00000040, + 0x7 => 0x00000080, + 0x8 => 0x0000001b, + 0x9 => 0x00000036, + _ => internal_error(__FILE__, __LINE__, "Unexpected AES r") /* unreachable -- required to silence Sail warning */ + } +} + +/* SM4 SBox - only one sbox for forwards and inverse */ +let sm4_sbox_table : vector(256, bits(8)) = [ +0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, +0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, +0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, +0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, 0xE4, 0xB3, 0x1C, 0xA9, +0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, 0x47, +0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, +0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, +0x4B, 0x70, 0x56, 0x9D, 0x35, 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, +0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, +0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, +0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, +0xA1, 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, +0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, +0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, +0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, 0x8D, 0x1B, 0xAF, +0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, +0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, +0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, +0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, +0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48 +] + +let aes_sbox_fwd_table : vector(256, bits(8)) = [ +0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, +0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, +0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, +0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, +0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, +0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, +0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, +0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, +0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, +0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, +0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, +0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, +0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, +0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, +0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, +0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, +0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, +0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, +0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, +0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 +] + +let aes_sbox_inv_table : vector(256, bits(8)) = [ +0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, +0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, +0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, +0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, +0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, +0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, +0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, +0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, +0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, +0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, +0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, +0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, +0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, +0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, +0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, +0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, +0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, +0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, +0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, +0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d +] + +/* Lookup function - takes an index and a table, and retrieves the + * x'th element of that table. Note that the Sail vector literals + * start at index 255, and go down to 0. + */ +val sbox_lookup : (bits(8), vector(256, bits(8))) -> bits(8) +function sbox_lookup(x, table) = { + table[255 - unsigned(x)] +} + +/* Easy function to perform a forward AES SBox operation on 1 byte. */ +val aes_sbox_fwd : bits(8) -> bits(8) +function aes_sbox_fwd(x) = sbox_lookup(x, aes_sbox_fwd_table) + +/* Easy function to perform an inverse AES SBox operation on 1 byte. */ +val aes_sbox_inv : bits(8) -> bits(8) +function aes_sbox_inv(x) = sbox_lookup(x, aes_sbox_inv_table) + +/* AES SubWord function used in the key expansion + * - Applies the forward sbox to each byte in the input word. + */ +val aes_subword_fwd : bits(32) -> bits(32) +function aes_subword_fwd(x) = { + aes_sbox_fwd(x[31..24]) @ + aes_sbox_fwd(x[23..16]) @ + aes_sbox_fwd(x[15.. 8]) @ + aes_sbox_fwd(x[ 7.. 0]) +} + +/* AES Inverse SubWord function. + * - Applies the inverse sbox to each byte in the input word. + */ +val aes_subword_inv : bits(32) -> bits(32) +function aes_subword_inv(x) = { + aes_sbox_inv(x[31..24]) @ + aes_sbox_inv(x[23..16]) @ + aes_sbox_inv(x[15.. 8]) @ + aes_sbox_inv(x[ 7.. 0]) +} + +/* Easy function to perform an SM4 SBox operation on 1 byte. */ +val sm4_sbox : bits(8) -> bits(8) +function sm4_sbox(x) = sbox_lookup(x, sm4_sbox_table) + +val aes_get_column : (bits(128), nat) -> bits(32) +function aes_get_column(state,c) = (state >> (to_bits(7, 32 * c)))[31..0] + +/* 64-bit to 64-bit function which applies the AES forward sbox to each byte + * in a 64-bit word. + */ +val aes_apply_fwd_sbox_to_each_byte : bits(64) -> bits(64) +function aes_apply_fwd_sbox_to_each_byte(x) = { + aes_sbox_fwd(x[63..56]) @ + aes_sbox_fwd(x[55..48]) @ + aes_sbox_fwd(x[47..40]) @ + aes_sbox_fwd(x[39..32]) @ + aes_sbox_fwd(x[31..24]) @ + aes_sbox_fwd(x[23..16]) @ + aes_sbox_fwd(x[15.. 8]) @ + aes_sbox_fwd(x[ 7.. 0]) +} + +/* 64-bit to 64-bit function which applies the AES inverse sbox to each byte + * in a 64-bit word. + */ +val aes_apply_inv_sbox_to_each_byte : bits(64) -> bits(64) +function aes_apply_inv_sbox_to_each_byte(x) = { + aes_sbox_inv(x[63..56]) @ + aes_sbox_inv(x[55..48]) @ + aes_sbox_inv(x[47..40]) @ + aes_sbox_inv(x[39..32]) @ + aes_sbox_inv(x[31..24]) @ + aes_sbox_inv(x[23..16]) @ + aes_sbox_inv(x[15.. 8]) @ + aes_sbox_inv(x[ 7.. 0]) +} + +/* + * AES full-round transformation functions. + */ + +val getbyte : (bits(64), int) -> bits(8) +function getbyte(x, i) = (x >> to_bits(6, i * 8))[7..0] + +val aes_rv64_shiftrows_fwd : (bits(64), bits(64)) -> bits(64) +function aes_rv64_shiftrows_fwd(rs2, rs1) = { + getbyte(rs1, 3) @ + getbyte(rs2, 6) @ + getbyte(rs2, 1) @ + getbyte(rs1, 4) @ + getbyte(rs2, 7) @ + getbyte(rs2, 2) @ + getbyte(rs1, 5) @ + getbyte(rs1, 0) +} + +val aes_rv64_shiftrows_inv : (bits(64), bits(64)) -> bits(64) +function aes_rv64_shiftrows_inv(rs2, rs1) = { + getbyte(rs2, 3) @ + getbyte(rs2, 6) @ + getbyte(rs1, 1) @ + getbyte(rs1, 4) @ + getbyte(rs1, 7) @ + getbyte(rs2, 2) @ + getbyte(rs2, 5) @ + getbyte(rs1, 0) +} + +/* 128-bit to 128-bit implementation of the forward AES ShiftRows transform. + * Byte 0 of state is input column 0, bits 7..0. + * Byte 5 of state is input column 1, bits 15..8. + */ +val aes_shift_rows_fwd : bits(128) -> bits(128) +function aes_shift_rows_fwd(x) = { + let ic3 : bits(32) = aes_get_column(x, 3); + let ic2 : bits(32) = aes_get_column(x, 2); + let ic1 : bits(32) = aes_get_column(x, 1); + let ic0 : bits(32) = aes_get_column(x, 0); + let oc0 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic2[15.. 8] @ ic3[ 7.. 0]; + let oc1 : bits(32) = ic1[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0]; + let oc2 : bits(32) = ic2[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic1[ 7.. 0]; + let oc3 : bits(32) = ic3[31..24] @ ic0[23..16] @ ic1[15.. 8] @ ic2[ 7.. 0]; + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* 128-bit to 128-bit implementation of the inverse AES ShiftRows transform. + * Byte 0 of state is input column 0, bits 7..0. + * Byte 5 of state is input column 1, bits 15..8. + */ +val aes_shift_rows_inv : bits(128) -> bits(128) +function aes_shift_rows_inv(x) = { + let ic3 : bits(32) = aes_get_column(x, 3); /* In column 3 */ + let ic2 : bits(32) = aes_get_column(x, 2); + let ic1 : bits(32) = aes_get_column(x, 1); + let ic0 : bits(32) = aes_get_column(x, 0); + let oc0 : bits(32) = ic0[31..24] @ ic3[23..16] @ ic2[15.. 8] @ ic1[ 7.. 0]; + let oc1 : bits(32) = ic1[31..24] @ ic0[23..16] @ ic3[15.. 8] @ ic2[ 7.. 0]; + let oc2 : bits(32) = ic2[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic3[ 7.. 0]; + let oc3 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic1[15.. 8] @ ic0[ 7.. 0]; + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the forward sub-bytes step of AES to a 128-bit vector + * representation of its state. + */ +val aes_subbytes_fwd : bits(128) -> bits(128) +function aes_subbytes_fwd(x) = { + let oc0 : bits(32) = aes_subword_fwd(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_subword_fwd(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_subword_fwd(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_subword_fwd(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the inverse sub-bytes step of AES to a 128-bit vector + * representation of its state. + */ +val aes_subbytes_inv : bits(128) -> bits(128) +function aes_subbytes_inv(x) = { + let oc0 : bits(32) = aes_subword_inv(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_subword_inv(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_subword_inv(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_subword_inv(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the forward MixColumns step of AES to a 128-bit vector + * representation of its state. + */ +val aes_mixcolumns_fwd : bits(128) -> bits(128) +function aes_mixcolumns_fwd(x) = { + let oc0 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the inverse MixColumns step of AES to a 128-bit vector + * representation of its state. + */ +val aes_mixcolumns_inv : bits(128) -> bits(128) +function aes_mixcolumns_inv(x) = { + let oc0 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} +---- diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc new file mode 100644 index 0000000..339ced2 --- /dev/null +++ b/src/smcntrpmf.adoc @@ -0,0 +1,73 @@ +[[smcntrpmf]] +== "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0.0 + +[[intro]] +=== Introduction + +The cycle and instret counters serve to support user mode self-profiling usages, wherein a user can read the counter(s) twice and compute the delta(s) to evaluate user software performance and behavior. Currently, these counters are not filtered by privilege mode, and thus they continue to increment while traps (e.g., page faults or interrupts) to more privileged code are handled. This causes two problems: + +* It introduces unpredictable noise to the counter values observed by the user. +* It leaks information about privileged software execution to user mode. + +This proposal remedies these issues by introducing privilege mode filtering for the cycle and instret counters. + +[[csrs]] +=== CSRs + +==== Machine Counter Configuration Registers (mcyclecfg, minstretcfg) + +mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode filtering for the cycle and instret counters, respectively. + +[cols="^1,^1,^1,^1,^1,^1,^5",stripes=even,options="header"] +|==== +|63 |62 |61 |60 |59 |58 |57:0 +|0 |MINH |SINH |UINH |VSINH |VUINH |_WPRI_ +|==== + +[cols="15%,85%",options="header"] +|==== +| Field | Description +| MINH | If set, then counting of events in M-mode is inhibited +| SINH | If set, then counting of events in S/HS-mode is inhibited +| UINH | If set, then counting of events in U-mode is inhibited +| VSINH | If set, then counting of events in VS-mode is inhibited +| VUINH | If set, then counting of events in VU-mode is inhibited +|==== + +When all __x__INH bits are zero, event counting is enabled in all modes. + +For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. Bits 57:56 are reserved for possible future modes. + +For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR. + +The CSR numbers are 0x321 for mcyclecfg, 0x322 for minstretcfg, 0x721 for mcyclecfgh, and 0x722 for minstretcfgh. + +The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extensions are implemented. + +[NOTE] +==== +The more natural CSR number for mcyclecfg would be 0x320, but that was allocated to mcountinhibit. + +This register format matches that specified for programmable counters by Sscofpmf. The bit position for the OF bit (bit 63) is read-only 0, since these counters do not generate local counter overflow interrupts on overflow. +==== + +[[behavior]] +=== Counter Behavior + +The fundamental behavior of cycle and instret is modified in that counting does not occur while executing in an inhibited privilege mode. Further, the following defines how transitions between a non-inhibited privilege mode and an inhibited privilege mode are counted. + +The cycle counter will simply count CPU cycles while the CPU is in a non-inhibited privilege mode. Mode transition operations (traps and trap returns) may take multiple clock cycles, and the change of privilege mode may be reported as occurring in any one of those cycles (possibly different for each occurrence of a trap or trap return). + +[NOTE] +==== +The RISC-V ISA has no requirement that the number of cycles for a trap or trap return be the same for all occurrences. Implementations are free to determine the extent to which this number may be consistent and predictable (or not), and the same is true for the specific cycle in which privilege mode changes. +==== + +For the instret counter, most instructions do not affect mode transitions, so for those the behavior is clear: instructions that retire in a non-inhibited mode increment instret, and instructions that retire in an inhibited mode do not. There are two types of instructions that can affect a privilege mode change: instructions that cause synchronous exceptions to a more privileged mode, and xRET instructions that return to a less privileged mode. The former are not considered to retire, and hence do not increment instret. The latter do retire, and should increment instret only if the originating privilege mode is not inhibited. + +[NOTE] +==== +The instret definition above is intended to ensure that the counter increments in a predictable fashion. For example, consider a scenario where minstretcfg is configured such that all modes other than U-mode are inhibited. A user mode load should increment only once, even if it takes a page fault or other exception. With this definition, the faulting execution of the load will not increment (it does not retire), the handler instructions will not increment (they execute in an inhibited mode), including the xRET (it arguably retires in a non-inhibited mode, but it originates in an inhibited mode). Only once the load is re-executed and retires will it increment instret. + +In cases where an instruction is emulated by software running in a privilege mode that is inhibited in minstretcfg, the emulation routine must emulate the instret increment. +====
\ No newline at end of file diff --git a/src/svadu.adoc b/src/svadu.adoc new file mode 100644 index 0000000..f8c4267 --- /dev/null +++ b/src/svadu.adoc @@ -0,0 +1,92 @@ +[[svadu]] +== "Svadu" Hardware Updating of PTE A/D Bits, Version 1.0.0 + +[[chapter2]] +=== Hardware Updating of PTE A/D Bits + +The Svadu extension adds support and CSR controls for hardware updating of PTE +A/D bits. The A and D bits are managed by these extensions as follows: + +* When a virtual page is accessed and the A bit is clear, the PTE is updated to + set the A bit. When the virtual page is written and the D bit is clear, the + PTE is updated to set the D bit. When G-stage address translation is in use + and is not Bare, the G-stage virtual pages may be accessed or written by + implicit accesses to VS-level memory management data structures, such as page + tables. + +* When two-stage address translation is in use, an explicit access may cause + both VS-stage and G-stage PTEs to be updated. The following rules apply to all + PTE updates caused by an explicit or an implicit memory accesses. + + + + The PTE update must be atomic with respect to other accesses to the PTE, and + must atomically perform all tablewalk checks for that leaf PTE as part of, and + before, conditionally updating the PTE value. Updates of the A bit may be + performed as a result of speculation, even if the associated memory access + ultimately is not performed architecturally. However, updates to the D bit, + resulting from an explicit store, must be exact (i.e., non-speculative), and + observed in program order by the local hart. When two-stage address + translation is active, updates of the D bit in G-stage PTEs may be performed + as a result of speculative updates of the A bit in VS-stage PTEs. + + + + The PTE update must appear in the global memory order before the memory access + that caused the PTE update and before any subsequent explicit memory access to + that virtual page by the local hart. The ordering on loads and stores provided + by FENCE instructions and the acquire/release bits on atomic instructions also + orders the PTE updates associated with those loads and stores as observed by + remote harts. + + + + The PTE update is not required to be atomic with respect to the memory access + that caused the update and a trap may occur between the PTE update and the + memory access that caused the PTE update. If a trap occurs then the A and/or D + bit may be updated but the memory access that caused the PTE update might not + occur. The hart must not perform the memory access that caused the PTE update + before the PTE update is globally visible. + +[NOTE] +==== +The PTE updates due to memory accesses ordered-after a FENCE are not themselves +ordered by the FENCE. + +Simpler implementations that cannot precisely order the PTE update before +subsequent explicit memory accesses to the associated virtual page by the local +hart may simply order the PTE update before all subsequent explicit memory +accesses to any virtual page by the local hart. +==== + +Svadu extension requires the page tables to be located in memory with hardware +page-table write access and _RsrvEventual_ PMA. + +<<< + +The translation of virtual addresses (or guest physical addresses) to physical +(or guest physical) addresses is accomplished with the same algorithm as +specified in the Supervisor-Level ISA extension (section "Virtual Address +Translation Process") and as modified by the hypervisor extension (section +"Two-stage Address Translation"), except that step 7 of the translation process, +instead of causing a page-fault exception due to A and/or D bits being 0 when +required to be 1, continues as follows: + +[start=7] +. If `pte.a = 0`, or if the original memory access is a store and `pte.d = 0`: +.. If a store to `pte` would violate a PMA or PMP check, raise an access-fault + exception corresponding to the original access type. +.. Perform the following steps atomically: +... Compare `pte` to the value of the PTE at address `a + va.vpn[i] × PTESIZE`. +... If the values match, set `pte.a` to 1 and, if the original memory access is + a store, also set `pte.d` to 1. +... If the comparison fails, return to step 2 + +The Svadu extension adds the `ADUE` bit (bit 61) to `menvcfg`. When +`menvcfg.ADUE` is 1, hardware updating of PTE A/D bits is enabled during +single-stage address translation. When the hypervisor extension is implemented, +if `menvcfg.ADUE` is 1, hardware updating of PTE A/D bits is enabled during +G-stage address translation. When `menvcfg.ADUE` is zero, the implementation +behaves as though Svadu were not implemented. If Svadu is not implemented, +`menvcfg.ADUE` is read-only zero. Furthermore, for implementations with the +hypervisor extension, `henvcfg.ADUE` is read-only zero if `menvcfg.ADUE` is zero. + +When the hypervisor extension is implemented, the Svadu extension adds the +`ADUE` bit (bit 61) to `henvcfg`. When `henvcfg.ADUE` is 1, hardware updating of +PTE A/D bits is enabled during VS-stage address translation. When `henvcfg.ADUE` +is zero, the implementation behaves as though Svadu were not implemented for +VS-stage address translation.
\ No newline at end of file diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index 88dcf8d..194e448 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -1,9 +1,6 @@ [[vector]] == "V" Standard Extension for Vector Operations, Version 1.0 -The specification is currently hosted at -https://github.com/riscv/riscv-v-spec. - [NOTE] ==== _The base vector extension is intended to provide general support for @@ -12,3 +9,5185 @@ with later vector extensions supporting richer functionality for certain domains._ ==== +=== Introduction + +This document is version 1.1-draft of the RISC-V vector extension. + +NOTE: This version holds updates gathered after the start of the +public review. The spec will have a final update to version 2.0 at +time of ratification. + +This spec includes the complete set of currently frozen vector +instructions. Other instructions that have been considered during +development but are not present in this document are not included in +the review and ratification process, and may be completely revised or +abandoned. Section <<sec-vector-extensions>> lists the standard +vector extensions and which instructions and element widths are +supported by each extension. + +=== Implementation-defined Constant Parameters + +Each hart supporting a vector extension defines two parameters: + +. The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which +must be a power of 2. +. The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^. + +Standard vector extensions (Section <<sec-vector-extensions>>) and +architecture profiles may set further constraints on _ELEN_ and _VLEN_. + +NOTE: Future extensions may allow ELEN {gt} VLEN by holding one +element using bits from multiple vector registers, but this current +proposal does not include this option. + +NOTE: The upper limit on VLEN allows software to know that indices +will fit into 16 bits (largest VLMAX of 65,536 occurs for LMUL=8 and +SEW=8 with VLEN=65,536). Any future extension beyond 64Kib per vector +register will require new configuration instructions such that +software using the old configuration instructions does not see greater +vector lengths. + +The vector extension supports writing binary code that under certain +constraints will execute portably on harts with different values for +the VLEN parameter, provided the harts support the required element +types and instructions. + +NOTE: Code can be written that will expose differences in +implementation parameters. + +NOTE: In general, thread contexts with active vector state cannot be +migrated during execution between harts that have any difference in +VLEN or ELEN parameters. + +=== Vector Extension Programmer's Model + +The vector extension adds 32 vector registers, and seven unprivileged +CSRs (`vstart`, `vxsat`, `vxrm`, `vcsr`, `vtype`, `vl`, `vlenb`) to a +base scalar RISC-V ISA. + +.New vector CSRs +[cols="2,2,2,10"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Address | Privilege | Name | Description + +| 0x008 | URW | vstart | Vector start position +| 0x009 | URW | vxsat | Fixed-Point Saturate Flag +| 0x00A | URW | vxrm | Fixed-Point Rounding Mode +| 0x00F | URW | vcsr | Vector control and status register +| 0xC20 | URO | vl | Vector length +| 0xC21 | URO | vtype | Vector data type register +| 0xC22 | URO | vlenb | VLEN/8 (vector register length in bytes) +|=== + +NOTE: The four CSR numbers `0x00B`-`0x00E` are tentatively reserved +for future vector CSRs, some of which may be mirrored into `vcsr`. + +==== Vector Registers + +The vector extension adds 32 architectural vector registers, +`v0`-`v31` to the base scalar RISC-V ISA. + +Each vector register has a fixed VLEN bits of state. + +==== Vector Context Status in `mstatus` + +A vector context status field, `VS`, is added to `mstatus[10:9]` and shadowed +in `sstatus[10:9]`. It is defined analogously to the floating-point context +status field, `FS`. + +Attempts to execute any vector instruction, or to access the vector +CSRs, raise an illegal-instruction exception when `mstatus.VS` is +set to Off. + +When `mstatus.VS` is set to Initial or Clean, executing any +instruction that changes vector state, including the vector CSRs, will +change `mstatus.VS` to Dirty. +Implementations may also change `mstatus.VS` from Initial or Clean to Dirty +at any time, even when there is no change in vector state. + +NOTE: Accurate setting of `mstatus.VS` is an optimization. Software +will typically use VS to reduce context-swap overhead. + +If `mstatus.VS` is Dirty, `mstatus.SD` is 1; +otherwise, `mstatus.SD` is set in accordance with existing specifications. + +Implementations may have a writable `misa.V` field. Analogous to the +way in which the floating-point unit is handled, the `mstatus.VS` +field may exist even if `misa.V` is clear. + +NOTE: Allowing `mstatus.VS` to exist when `misa.V` is clear, enables +vector emulation and simplifies handling of `mstatus.VS` in systems +with writable `misa.V`. + +==== Vector Context Status in `vsstatus` + +When the hypervisor extension is present, a vector context status field, `VS`, +is added to `vsstatus[10:9]`. +It is defined analogously to the floating-point context status field, `FS`. + +When V=1, both `vsstatus.VS` and `mstatus.VS` are in effect: attempts to +execute any vector instruction, or to access the vector CSRs, raise an +illegal-instruction exception when either field is set to Off. + +When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing +any instruction that changes vector state, including the vector CSRs, will +change both `mstatus.VS` and `vsstatus.VS` to Dirty. +Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or +Clean to Dirty at any time, even when there is no change in vector state. + +If `vsstatus.VS` is Dirty, `vsstatus.SD` is 1; +otherwise, `vsstatus.SD` is set in accordance with existing specifications. + +If `mstatus.VS` is Dirty, `mstatus.SD` is 1; +otherwise, `mstatus.SD` is set in accordance with existing specifications. + +For implementations with a writable `misa.V` field, +the `vsstatus.VS` field may exist even if `misa.V` is clear. + +==== Vector type register, `vtype` + +The read-only XLEN-wide _vector_ _type_ CSR, `vtype` provides the +default type used to interpret the contents of the vector register +file, and can only be updated by `vset{i}vl{i}` instructions. The +vector type determines the organization of elements in each +vector register, and how multiple vector registers are grouped. The +`vtype` register also indicates how masked-off elements and elements +past the current vector length in a vector result are handled. + +NOTE: Allowing updates only via the `vset{i}vl{i}` instructions +simplifies maintenance of the `vtype` register state. + +The `vtype` register has five fields, `vill`, `vma`, `vta`, +`vsew[2:0]`, and `vlmul[2:0]`. Bits `vtype[XLEN-2:8]` should be +written with zero, and non-zero values in this field are reserved. + +include::images/wavedrom/vtype-format.adoc[] + +NOTE: A small implementation supporting ELEN=32 requires only seven +bits of state in `vtype`: two bits for `ma` and `ta`, two bits for +`vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value +represented by `vill` can be internally encoded using the illegal 64-bit +combination in `vsew[1:0]` without requiring an additional storage +bit to hold `vill`. + +NOTE: Further standard and custom vector extensions may extend these +fields to support a greater variety of data types. + +NOTE: The primary motivation for the `vtype` CSR is to allow the +vector instruction set to fit into a 32-bit instruction encoding +space. A separate `vset{i}vl{i}` instruction can be used to set `vl` +and/or `vtype` fields before execution of a vector instruction, and +implementations may choose to fuse these two instructions into a single +internal vector microop. In many cases, the `vl` and `vtype` values +can be reused across multiple instructions, reducing the static and +dynamic instruction overhead from the `vset{i}vl{i}` instructions. It +is anticipated that a future extended 64-bit instruction encoding +would allow these fields to be specified statically in the instruction +encoding. + +===== Vector selected element width `vsew[2:0]` + +The value in `vsew` sets the dynamic _selected_ _element_ _width_ +(SEW). By default, a vector register is viewed as being divided into +VLEN/SEW elements. + +.vsew[2:0] (selected element width) encoding +[cols="1,1,1,1"] +[%autowidth,float="center",align="center",options="header"] +|=== +3+| vsew[2:0] | SEW + +| 0 | 0 | 0 | 8 +| 0 | 0 | 1 | 16 +| 0 | 1 | 0 | 32 +| 0 | 1 | 1 | 64 +| 1 | X | X | Reserved +|=== + +NOTE: While it is anticipated the larger `vsew[2:0]` encodings +(`100`-`111`) will be used to encode larger SEW, the encodings are +formally _reserved_ at this point. + +.Example VLEN = 128 bits +[cols=">,>"] +[%autowidth,float="center",align="center",options="header"] +|=== +| SEW | Elements per vector register + +| 64 | 2 +| 32 | 4 +| 16 | 8 +| 8 | 16 +|=== + +The supported element width may vary with LMUL. + +NOTE: The current set of standard vector extensions do not vary +supported element width with LMUL. Some future extensions may support +larger SEWs only when bits from multiple vector registers are combined +using LMUL. In this case, software that relies on large SEW should +attempt to use the largest LMUL, and hence the fewest vector register +groups, to increase the number of implementations on which the code +will run. The `vill` bit in `vtype` should be checked after setting +`vtype` to see if the configuration is supported, and an alternate +code path should be provided if it is not. Alternatively, a profile +can mandate the minimum SEW at each LMUL setting. + +===== Vector Register Grouping (`vlmul[2:0]`) + +Multiple vector registers can be grouped together, so that a single +vector instruction can operate on multiple vector registers. The term +_vector_ _register_ _group_ is used herein to refer to one or more +vector registers used as a single operand to a vector instruction. +Vector register groups can be used to provide greater execution +efficiency for longer application vectors, but the main reason for +their inclusion is to allow double-width or larger elements to be +operated on with the same vector length as single-width elements. The +vector length multiplier, _LMUL_, when greater than 1, represents the +default number of vector registers that are combined to form a vector +register group. Implementations must support LMUL integer values of +1, 2, 4, and 8. + + +NOTE: The vector architecture includes instructions that take multiple +source and destination vector operands with different element widths, +but the same number of elements. The effective LMUL (EMUL) of each +vector operand is determined by the number of registers required to +hold the elements. For example, for a widening add operation, such as +add 32-bit values to produce 64-bit results, a double-width result +requires twice the LMUL of the single-width inputs. + +LMUL can also be a fractional value, reducing the number of bits used +in a single vector register. Fractional LMUL is used to increase the +number of effective usable vector register groups when operating on +mixed-width values. + +NOTE: With only integer LMUL values, a loop operating on a range of +sizes would have to allocate at least one whole vector register +(LMUL=1) for the narrowest data type and then would consume multiple +vector registers (LMUL>1) to form a vector register group for each +wider vector operand. This can limit the number of vector register groups +available. With fractional LMUL, the widest values need occupy only a +single vector register while narrower values can occupy a fraction of +a single vector register, allowing all 32 architectural vector +register names to be used for different values in a vector loop even +when handling mixed-width values. Fractional LMUL implies portions of +vector registers are unused, but in some cases, having more shorter +register-resident vectors improves efficiency relative to fewer longer +register-resident vectors. + +Implementations must provide fractional LMUL settings that allow the +narrowest supported type to occupy a fraction of a vector register +corresponding to the ratio of the narrowest supported type's width to +that of the largest supported type's width. In general, the +requirement is to support LMUL {ge} SEW~MIN~/ELEN, where SEW~MIN~ is +the narrowest supported SEW value and ELEN is the widest supported SEW +value. In the standard extensions, SEW~MIN~=8. For +standard vector extensions with ELEN=32, fractional LMULs of 1/2 and +1/4 must be supported. For standard vector extensions with ELEN=64, +fractional LMULs of 1/2, 1/4, and 1/8 must be supported. + +NOTE: When LMUL < SEW~MIN~/ELEN, there is no guarantee +an implementation would have enough bits in the fractional vector +register to store at least one element, as VLEN=ELEN is a +valid implementation choice. For example, with VLEN=ELEN=32, +and SEW~MIN~=8, an LMUL of 1/8 would only provide four bits of +storage in a vector register. + +For a given supported fractional LMUL setting, implementations must support +SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive. + +The use of `vtype` encodings with LMUL < SEW~MIN~/ELEN is +__reserved__, but implementations can set `vill` if they do not +support these configurations. + +NOTE: Requiring all implementations to set `vill` in this case would +prohibit future use of this case in an extension, so to allow for a +future definition of LMUL<SEW~MIN~/ELEN behavior, we +consider the use of this case to be __reserved__. + +NOTE: It is recommended that assemblers provide a warning (not an +error) if a `vsetvli` instruction attempts to write an LMUL < SEW~MIN~/ELEN. + +LMUL is set by the signed `vlmul` field in `vtype` (i.e., LMUL = +2^`vlmul[2:0]`^). + +The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number +of elements that can be operated on with a single vector instruction +given the current SEW and LMUL settings as shown in the table below. + +[cols="1,1,1,2,2,5,5"] +[%autowidth,float="center",align="center",options="header"] +|=== + 3+| vlmul[2:0] | LMUL | #groups | VLMAX | Registers grouped with register __n__ + +| 1 | 0 | 0 | - | - | - | reserved +| 1 | 0 | 1 | 1/8| 32 | VLEN/SEW/8 | `v` __n__ (single register in group) +| 1 | 1 | 0 | 1/4| 32 | VLEN/SEW/4 | `v` __n__ (single register in group) +| 1 | 1 | 1 | 1/2| 32 | VLEN/SEW/2 | `v` __n__ (single register in group) +| 0 | 0 | 0 | 1 | 32 | VLEN/SEW | `v` __n__ (single register in group) +| 0 | 0 | 1 | 2 | 16 | 2*VLEN/SEW | `v` __n__, `v` __n__+1 +| 0 | 1 | 0 | 4 | 8 | 4*VLEN/SEW | `v` __n__, ..., `v` __n__+3 +| 0 | 1 | 1 | 8 | 4 | 8*VLEN/SEW | `v` __n__, ..., `v` __n__+7 +|=== + +When LMUL=2, the vector register group contains vector register `v` +__n__ and vector register `v` __n__+1, providing twice the vector +length in bits. Instructions specifying an LMUL=2 vector register group +with an odd-numbered vector register are reserved. + +When LMUL=4, the vector register group contains four vector registers, +and instructions specifying an LMUL=4 vector register group using vector +register numbers that are not multiples of four are reserved. + +When LMUL=8, the vector register group contains eight vector +registers, and instructions specifying an LMUL=8 vector register group +using register numbers that are not multiples of eight are reserved. + +Mask registers are always contained in a single vector register, +regardless of LMUL. + +[[sec-agnostic]] +===== Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma` + +These two bits modify the behavior of destination tail elements and +destination inactive masked-off elements respectively during the +execution of vector instructions. The tail and inactive sets contain +element positions that are not receiving new results during a vector +operation, as defined in Section <<sec-inactive-defs>>. + +All systems must support all four options: + +[cols="1,1,3,3"] +[%autowidth,float="center",align="center",options="header"] +|=== +| `vta` | `vma` | Tail Elements | Inactive Elements + +| 0 | 0 | undisturbed | undisturbed +| 0 | 1 | undisturbed | agnostic +| 1 | 0 | agnostic | undisturbed +| 1 | 1 | agnostic | agnostic +|=== + +Mask destination tail elements are always treated as tail-agnostic, +regardless of the setting of `vta`. + +When a set is marked undisturbed, the corresponding set of destination +elements in a vector register group retain the value they previously +held. + +When a set is marked agnostic, the corresponding set of destination +elements in any vector destination operand can either retain the value +they previously held, or are overwritten with 1s. Within a single vector +instruction, each destination element can be either left undisturbed +or overwritten with 1s, in any combination, and the pattern of +undisturbed or overwritten with 1s is not required to be deterministic +when the instruction is executed with the same inputs. + +NOTE: The agnostic policy was added to accommodate machines with +vector register renaming. With an undisturbed policy, all elements +would have to be read from the old physical destination vector +register to be copied into the new physical destination vector +register. This causes an inefficiency when these inactive or tail +values are not required for subsequent calculations. + +NOTE: The value of all 1s instead of all 0s was chosen for the +overwrite value to discourage software developers from depending on +the value written. + +NOTE: A simple in-order implementation can ignore the settings and +simply execute all vector instructions using the undisturbed +policy. The `vta` and `vma` state bits must still be provided in +`vtype` for compatibility and to support thread migration. + +NOTE: An out-of-order implementation can choose to implement +tail-agnostic + mask-agnostic using tail-agnostic + mask-undisturbed +to reduce implementation complexity. + +NOTE: The definition of agnostic result policy is left loose to +accommodate migrating application threads between harts on a small +in-order core (which probably leaves agnostic regions undisturbed) and +harts on a larger out-of-order core with register renaming (which +probably overwrites agnostic elements with 1s). As it might be +necessary to restart in the middle, we allow arbitrary mixing of +agnostic policies within a single vector instruction. This allowed +mixing of policies also enables implementations that might change +policies for different granules of a vector register, for example, +using undisturbed within a granule that is actively operated on but +renaming to all 1s for granules in the tail. + +In addition, except for mask load instructions, any element in the +tail of a mask result can also be written with the value the +mask-producing operation would have calculated with `vl`=VLMAX. +Furthermore, for mask-logical instructions and `vmsbf.m`, `vmsif.m`, +`vmsof.m` mask-manipulation instructions, any element in the tail of +the result can be written with the value the mask-producing operation +would have calculated with `vl`=VLEN, SEW=8, and LMUL=8 (i.e., all +bits of the mask register can be overwritten). + +NOTE: Mask tails are always treated as agnostic to reduce complexity +of managing mask data, which can be written at bit granularity. There +appears to be little software need to support tail-undisturbed for +mask register values. Allowing mask-generating instructions to write +back the result of the instruction avoids the need for logic to mask +out the tail, except mask loads cannot write memory values to +destination mask tails as this would imply accessing memory past +software intent. + +The assembly syntax adds two mandatory flags to the `vsetvli` instruction: + +---- + ta # Tail agnostic + tu # Tail undisturbed + ma # Mask agnostic + mu # Mask undisturbed + + vsetvli t0, a0, e32, m4, ta, ma # Tail agnostic, mask agnostic + vsetvli t0, a0, e32, m4, tu, ma # Tail undisturbed, mask agnostic + vsetvli t0, a0, e32, m4, ta, mu # Tail agnostic, mask undisturbed + vsetvli t0, a0, e32, m4, tu, mu # Tail undisturbed, mask undisturbed +---- + +NOTE: Prior to v0.9, when these flags were not specified on a +`vsetvli`, they defaulted to mask-undisturbed/tail-undisturbed. The +use of `vsetvli` without these flags is deprecated, however, and +specifying a flag setting is now mandatory. The default should +perhaps be tail-agnostic/mask-agnostic, so software has to specify +when it cares about the non-participating elements, but given the +historical meaning of the instruction prior to introduction of these +flags, it was decided to always require them in future assembly code. + +===== Vector Type Illegal `vill` + +The `vill` bit is used to encode that a previous `vset{i}vl{i}` +instruction attempted to write an unsupported value to `vtype`. + +NOTE: The `vill` bit is held in bit XLEN-1 of the CSR to support +checking for illegal values with a branch on the sign bit. + +If the `vill` bit is set, then any attempt to execute a vector instruction +that depends upon `vtype` will raise an illegal-instruction exception. + +NOTE: `vset{i}vl{i}` and whole register loads and stores do not depend +upon `vtype`. + +When the `vill` bit is set, the other XLEN-1 bits in `vtype` shall be +zero. + +==== Vector Length Register `vl` + +The _XLEN_-bit-wide read-only `vl` CSR can only be updated by the +`vset{i}vl{i}` instructions, and the _fault-only-first_ vector load +instruction variants. + +The `vl` register holds an unsigned integer specifying the number of +elements to be updated with results from a vector instruction, as +further detailed in Section <<sec-inactive-defs>>. + +NOTE: The number of bits implemented in `vl` depends on the +implementation's maximum vector length of the smallest supported +type. The smallest vector implementation with VLEN=32 and supporting +SEW=8 would need at least six bits in `vl` to hold the values 0-32 +(VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32). + +==== Vector Byte Length `vlenb` + +The _XLEN_-bit-wide read-only CSR `vlenb` holds the value VLEN/8, +i.e., the vector register length in bytes. + +NOTE: The value in `vlenb` is a design-time constant in any +implementation. + +NOTE: Without this CSR, several instructions are needed to calculate +VLEN in bytes, and the code has to disturb current `vl` and `vtype` +settings which require them to be saved and restored. + +==== Vector Start Index CSR `vstart` + +The _XLEN_-bit-wide read-write `vstart` CSR specifies the index of the +first element to be executed by a vector instruction, as described in +Section <<sec-inactive-defs>>. + +Normally, `vstart` is only written by hardware on a trap on a vector +instruction, with the `vstart` value representing the element on which +the trap was taken (either a synchronous exception or an asynchronous +interrupt), and at which execution should resume after a resumable +trap is handled. + +All vector instructions are defined to begin execution with the +element number given in the `vstart` CSR, leaving earlier elements in +the destination vector undisturbed, and to reset the `vstart` CSR to +zero at the end of execution. + +NOTE: All vector instructions, including `vset{i}vl{i}`, reset the `vstart` +CSR to zero. + +`vstart` is not modified by vector instructions that raise illegal-instruction +exceptions. + +The `vstart` CSR is defined to have only enough writable bits to hold +the largest element index (one less than the maximum VLMAX). + +NOTE: The maximum vector length is obtained with the largest LMUL +setting (8) and the smallest SEW setting (8), so VLMAX_max = 8*VLEN/8 = VLEN. For example, for VLEN=256, `vstart` would have 8 bits to +represent indices from 0 through 255. + +The use of `vstart` values greater than the largest element index for +the current `vtype` setting is reserved. + +NOTE: It is recommended that implementations trap if `vstart` is out +of bounds. It is not required to trap, as a possible future use of +upper `vstart` bits is to store imprecise trap information. + +The `vstart` CSR is writable by unprivileged code, but non-zero +`vstart` values may cause vector instructions to run substantially +slower on some implementations, so `vstart` should not be used by +application programmers. A few vector instructions cannot be +executed with a non-zero `vstart` value and will raise an illegal +instruction exception as defined below. + +NOTE: Making `vstart` visible to unprivileged code supports user-level +threading libraries. + +Implementations are permitted to raise illegal instruction exceptions when +attempting to execute a vector instruction with a value of `vstart` that the +implementation can never produce when executing that same instruction with +the same `vtype` setting. + +NOTE: For example, some implementations will never take interrupts during +execution of a vector arithmetic instruction, instead waiting until the +instruction completes to take the interrupt. Such implementations are +permitted to raise an illegal instruction exception when attempting to execute +a vector arithmetic instruction when `vstart` is nonzero. + +NOTE: When migrating a software thread between two harts with +different microarchitectures, the `vstart` value might not be +supported by the new hart microarchitecture. The runtime on the +receiving hart might then have to emulate instruction execution up to the +next supported `vstart` element position. Alternatively, migration events +can be constrained to only occur at mutually supported `vstart` +locations. + +==== Vector Fixed-Point Rounding Mode Register `vxrm` + +The vector fixed-point rounding-mode register holds a two-bit +read-write rounding-mode field in the least-significant bits +(`vxrm[1:0]`). The upper bits, `vxrm[XLEN-1:2]`, should be written as +zeros. + +The vector fixed-point rounding-mode is given a separate CSR address +to allow independent access, but is also reflected as a field in +`vcsr`. + +NOTE: A new rounding mode can be set while saving the original +rounding mode using a single `csrwi` instruction. + +The fixed-point rounding algorithm is specified as follows. +Suppose the pre-rounding result is `v`, and `d` bits of that result are to be +rounded off. +Then the rounded result is `(v >> d) + r`, where `r` depends on the rounding +mode as specified in the following table. + +.vxrm encoding +//[cols="1,1,4,10,5"] +[%autowidth,float="center",align="center",cols="<,<,<,<,<",options="header"] +|=== +2+| `vxrm[1:0]` | Abbreviation | Rounding Mode | Rounding increment, `r` + +| 0 | 0 | rnu | round-to-nearest-up (add +0.5 LSB) | `v[d-1]` +| 0 | 1 | rne | round-to-nearest-even | `v[d-1] & (v[d-2:0]{ne}0 \| v[d])` +| 1 | 0 | rdn | round-down (truncate) | `0` +| 1 | 1 | rod | round-to-odd (OR bits into LSB, aka "jam") | `!v[d] & v[d-1:0]{ne}0` +|=== + +The rounding functions: +---- +roundoff_unsigned(v, d) = (unsigned(v) >> d) + r +roundoff_signed(v, d) = (signed(v) >> d) + r +---- +are used to represent this operation in the instruction descriptions below. + +==== Vector Fixed-Point Saturation Flag `vxsat` + +The `vxsat` CSR has a single read-write least-significant bit +(`vxsat[0]`) that indicates if a fixed-point instruction has had to +saturate an output value to fit into a destination format. +Bits `vxsat[XLEN-1:1]` should be written as zeros. + +The `vxsat` bit is mirrored in `vcsr`. + +==== Vector Control and Status Register `vcsr` + +The `vxrm` and `vxsat` separate CSRs can also be accessed via fields +in the _XLEN_-bit-wide vector control and status CSR, `vcsr`. + +.vcsr layout +[cols=">2,4,10"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Bits | Name | Description + +| XLEN-1:3 | | Reserved +| 2:1 | vxrm[1:0] | Fixed-point rounding mode +| 0 | vxsat | Fixed-point accrued saturation flag +|=== + +==== State of Vector Extension at Reset + +The vector extension must have a consistent state at reset. In +particular, `vtype` and `vl` must have values that can be read and +then restored with a single `vsetvl` instruction. + +NOTE: It is recommended that at reset, `vtype.vill` is set, the +remaining bits in `vtype` are zero, and `vl` is set to zero. + +The `vstart`, `vxrm`, `vxsat` CSRs can have arbitrary values at reset. + +NOTE: Most uses of the vector unit will require an initial `vset{i}vl{i}`, +which will reset `vstart`. The `vxrm` and `vxsat` fields should be +reset explicitly in software before use. + +The vector registers can have arbitrary values at reset. + +=== Mapping of Vector Elements to Vector Register State + +The following diagrams illustrate how different width elements are +packed into the bytes of a vector register depending on the current +SEW and LMUL settings, as well as implementation VLEN. Elements are +packed into each vector register with the least-significant byte in +the lowest-numbered bits. + +The mapping was chosen to provide the simplest and most portable model +for software, but might appear to incur large wiring cost for wider +vector datapaths on certain operations. The vector instruction set +was expressly designed to support implementations that internally +rearrange vector data for different SEW to reduce datapath wiring +costs, while externally preserving the simple software model. + +NOTE: For example, microarchitectures can track the EEW with which a +vector register was written, and then insert additional scrambling +operations to rearrange data if the register is accessed with a +different EEW. + +==== Mapping for LMUL = 1 + +When LMUL=1, elements are simply packed in order from the +least-significant to most-significant bits of the vector register. + +NOTE: To increase readability, vector register layouts are drawn with +bytes ordered from right to left with increasing byte address. Bits +within an element are numbered in a little-endian format with +increasing bit index from right to left corresponding to increasing +magnitude. + +---- +LMUL=1 examples. + +The element index is given in hexadecimal and is shown placed at the +least-significant byte of the stored element. + + + VLEN=32b + + Byte 3 2 1 0 + + SEW=8b 3 2 1 0 + SEW=16b 1 0 + SEW=32b 0 + + VLEN=64b + + Byte 7 6 5 4 3 2 1 0 + + SEW=8b 7 6 5 4 3 2 1 0 + SEW=16b 3 2 1 0 + SEW=32b 1 0 + SEW=64b 0 + + VLEN=128b + + Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 + + SEW=8b F E D C B A 9 8 7 6 5 4 3 2 1 0 + SEW=16b 7 6 5 4 3 2 1 0 + SEW=32b 3 2 1 0 + SEW=64b 1 0 + + VLEN=256b + + Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 + + SEW=8b 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 + SEW=16b F E D C B A 9 8 7 6 5 4 3 2 1 0 + SEW=32b 7 6 5 4 3 2 1 0 + SEW=64b 3 2 1 0 +---- + +==== Mapping for LMUL < 1 + +When LMUL < 1, only the first LMUL*VLEN/SEW elements in the vector +register are used. The remaining space in the vector register is +treated as part of the tail, and hence must obey the vta setting. + +---- + Example, VLEN=128b, LMUL=1/4 + + Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 + + SEW=8b - - - - - - - - - - - - 3 2 1 0 + SEW=16b - - - - - - 1 0 + SEW=32b - - - 0 +---- + +==== Mapping for LMUL > 1 + +When vector registers are grouped, the elements of the vector register +group are packed contiguously in element order beginning with the +lowest-numbered vector register and moving to the +next-highest-numbered vector register in the group once each vector +register is filled. + +---- + LMUL > 1 examples + + VLEN=32b, SEW=8b, LMUL=2 + + Byte 3 2 1 0 + v2*n 3 2 1 0 + v2*n+1 7 6 5 4 + + VLEN=32b, SEW=16b, LMUL=2 + + Byte 3 2 1 0 + v2*n 1 0 + v2*n+1 3 2 + + VLEN=32b, SEW=16b, LMUL=4 + + Byte 3 2 1 0 + v4*n 1 0 + v4*n+1 3 2 + v4*n+2 5 4 + v4*n+3 7 6 + + VLEN=32b, SEW=32b, LMUL=4 + + Byte 3 2 1 0 + v4*n 0 + v4*n+1 1 + v4*n+2 2 + v4*n+3 3 + + VLEN=64b, SEW=32b, LMUL=2 + + Byte 7 6 5 4 3 2 1 0 + v2*n 1 0 + v2*n+1 3 2 + + VLEN=64b, SEW=32b, LMUL=4 + + Byte 7 6 5 4 3 2 1 0 + v4*n 1 0 + v4*n+1 3 2 + v4*n+2 5 4 + v4*n+3 7 6 + + VLEN=128b, SEW=32b, LMUL=2 + + Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 + v2*n 3 2 1 0 + v2*n+1 7 6 5 4 + + VLEN=128b, SEW=32b, LMUL=4 + + Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 + v4*n 3 2 1 0 + v4*n+1 7 6 5 4 + v4*n+2 B A 9 8 + v4*n+3 F E D C +---- + +[[sec-mapping-mixed]] +==== Mapping across Mixed-Width Operations + +The vector ISA is designed to support mixed-width operations without +requiring additional explicit rearrangement instructions. The +recommended software strategy when operating on multiple vectors with +different precision values is to modify `vtype` dynamically to keep +SEW/LMUL constant (and hence VLMAX constant). + +The following example shows four different packed element widths (8b, +16b, 32b, 64b) in a VLEN=128b implementation. The vector register +grouping factor (LMUL) is increased by the relative element size such +that each group can hold the same number of vector elements (VLMAX=8 +in this example) to simplify stripmining code. + +---- +Example VLEN=128b, with SEW/LMUL=16 + +Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 +vn - - - - - - - - 7 6 5 4 3 2 1 0 SEW=8b, LMUL=1/2 + +vn 7 6 5 4 3 2 1 0 SEW=16b, LMUL=1 + +v2*n 3 2 1 0 SEW=32b, LMUL=2 +v2*n+1 7 6 5 4 + +v4*n 1 0 SEW=64b, LMUL=4 +v4*n+1 3 2 +v4*n+2 5 4 +v4*n+3 7 6 +---- + +The following table shows each possible constant SEW/LMUL operating +point for loops with mixed-width operations. Each column represents a +constant SEW/LMUL operating point. Entries in table are the LMUL +values that yield that column's SEW/LMUL value for the datawidth on +that row. In each column, an LMUL setting for a datawidth indicates +that it can be aligned with the other datawidths in the same column +that also have an LMUL setting, such that all have the same VLMAX. + +|=== +| 7+^| SEW/LMUL +| | 1 | 2 | 4 | 8 | 16 | 32 | 64 + +| SEW= 8 | 8 | 4 | 2 | 1 | 1/2 | 1/4 | 1/8 +| SEW= 16 | | 8 | 4 | 2 | 1 | 1/2 | 1/4 +| SEW= 32 | | | 8 | 4 | 2 | 1 | 1/2 +| SEW= 64 | | | | 8 | 4 | 2 | 1 +|=== + +Larger LMUL settings can also used to simply increase vector length to +reduce instruction fetch and dispatch overheads in cases where fewer +vector register groups are needed. + +[[sec-mask-register-layout]] +==== Mask Register Layout + +A vector mask occupies only one vector register regardless of SEW and +LMUL. + +Each element is allocated a single mask bit in a mask vector register. +The mask bit for element _i_ is located in bit _i_ of the mask +register, independent of SEW or LMUL. + +=== Vector Instruction Formats + +The instructions in the vector extension fit under two existing major +opcodes (LOAD-FP and STORE-FP) and one new major opcode (OP-V). + +Vector loads and stores are encoded within the scalar floating-point +load and store major opcodes (LOAD-FP/STORE-FP). The vector load and +store encodings repurpose a portion of the standard scalar +floating-point load/store 12-bit immediate field to provide further +vector instruction encoding, with bit 25 holding the standard vector +mask bit (see <<sec-vector-mask-encoding>>). + +include::images/wavedrom/vmem-format.adoc[] + +include::images/wavedrom/valu-format.adoc[] + +include::images/wavedrom/vcfg-format.adoc[] + +Vector instructions can have scalar or vector source operands and +produce scalar or vector results, and most vector instructions can be +performed either unconditionally or conditionally under a mask. + +Vector loads and stores move bit patterns between vector register +elements and memory. Vector arithmetic instructions operate on values +held in vector register elements. + +==== Scalar Operands + +Scalar operands can be immediates, or taken from the `x` registers, +the `f` registers, or element 0 of a vector register. Scalar results +are written to an `x` or `f` register or to element 0 of a vector +register. Any vector register can be used to hold a scalar regardless +of the current LMUL setting. + +NOTE: Zfinx ("F in X") is a new ISA extension where +floating-point instructions take their arguments from the integer +register file. The vector extension is also compatible with Zfinx, +where the Zfinx vector extension has vector-scalar floating-point +instructions taking their scalar argument from the `x` registers. + +NOTE: We considered but did not pursue overlaying the `f` registers on +`v` registers. The adopted approach reduces vector register pressure, +avoids interactions with the standard calling convention, simplifies +high-performance scalar floating-point design, and provides +compatibility with the Zfinx ISA option. Overlaying `f` with `v` +would provide the advantage of lowering the number of state bits in +some implementations, but complicates high-performance designs and +would prevent compatibility with the Zfinx ISA option. + +[[sec-vec-operands]] +==== Vector Operands + +Each vector operand has an _effective_ _element_ _width_ (EEW) and an +_effective_ LMUL (EMUL) that is used to determine the size and +location of all the elements within a vector register group. By +default, for most operands of most instructions, EEW=SEW and +EMUL=LMUL. + +Some vector instructions have source and destination vector operands +with the same number of elements but different widths, so that EEW and +EMUL differ from SEW and LMUL respectively but EEW/EMUL = SEW/LMUL. +For example, most widening arithmetic instructions have a source group +with EEW=SEW and EMUL=LMUL but have a destination group with EEW=2*SEW and +EMUL=2*LMUL. Narrowing instructions have a source operand that has +EEW=2*SEW and EMUL=2*LMUL but with a destination where EEW=SEW and EMUL=LMUL. + +Vector operands or results may occupy one or more vector registers +depending on EMUL, but are always specified using the lowest-numbered +vector register in the group. Using other than the lowest-numbered +vector register to specify a vector register group is a reserved +encoding. + +A vector register cannot be used to provide source operands with more +than one EEW for a single instruction. A mask register source is +considered to have EEW=1 for this constraint. An encoding that would +result in the same vector register being read with two or more +different EEWs, including when the vector register appears at +different positions within two or more vector register groups, is +reserved. + +NOTE: In practice, there is no software benefit to reading the same +register with different EEW in the same instruction, and this +constraint reduces complexity for implementations that internally +rearrange data dependent on EEW. + +A destination vector register group can overlap a source vector register +group only if one of the following holds: + +- The destination EEW equals the source EEW. +- The destination EEW is smaller than the source EEW and the overlap is in + the lowest-numbered part of the source register group (e.g., when LMUL=1, + `vnsrl.wi v0, v0, 3` is legal, but a destination of `v1` is not). +- The destination EEW is greater than the source EEW, the source EMUL is + at least 1, and the overlap is in the highest-numbered part of the + destination register group (e.g., when LMUL=8, `vzext.vf4 v0, v6` is legal, + but a source of `v0`, `v2`, or `v4` is not). + +For the purpose of determining register group overlap constraints, +mask elements have EEW=1. + +NOTE: The overlap constraints are designed to support resumable +exceptions in machines without register renaming. + +Any instruction encoding that violates the overlap constraints is reserved. + +When source and destination registers overlap and have different EEW, the +instruction is mask- and tail-agnostic, regardless of the setting of the +`vta` and `vma` bits in `vtype`. + +The largest vector register group used by an instruction can not be +greater than 8 vector registers (i.e., EMUL{le}8), and if a vector +instruction would require greater than 8 vector registers in a group, +the instruction encoding is reserved. For example, a widening +operation that produces a widened vector register group result when +LMUL=8 is reserved as this would imply a result EMUL=16. + +Widened scalar values, e.g., input and output to a widening reduction +operation, are held in the first element of a vector register and +have EMUL=1. + +==== Vector Masking + +Masking is supported on many vector instructions. Element operations +that are masked off (inactive) never generate exceptions. The +destination vector register elements corresponding to masked-off +elements are handled with either a mask-undisturbed or mask-agnostic +policy depending on the setting of the `vma` bit in `vtype` (Section +<<sec-agnostic>>). + +The mask value used to control execution of a masked vector +instruction is always supplied by vector register `v0`. + +NOTE: Masks are held in vector registers, rather than in a separate mask +register file, to reduce total architectural state and to simplify the ISA. + +NOTE: Future vector extensions may provide longer instruction +encodings with space for a full mask register specifier. + +The destination vector register group for a masked vector instruction +cannot overlap the source mask register (`v0`), unless the destination +vector register is being written with a mask value (e.g., compares) +or the scalar result of a reduction. These instruction encodings are +reserved. + +NOTE: This constraint supports restart with a non-zero `vstart` value. + +Other vector registers can be used to hold working mask values, and +mask vector logical operations are provided to perform predicate +calculations. [[sec-mask-vector-logical]] + +As specified in Section <<sec-agnostic>>, mask destination values are +always treated as tail-agnostic, regardless of the setting of `vta`. + +[[sec-vector-mask-encoding]] +===== Mask Encoding + +Where available, masking is encoded in a single-bit `vm` field in the + instruction (`inst[25]`). + +[cols="1,15"] +|=== +| vm | Description + +| 0 | vector result, only where v0.mask[i] = 1 +| 1 | unmasked +|=== + +Vector masking is represented in assembler code as another vector +operand, with `.t` indicating that the operation occurs when +`v0.mask[i]` is `1` (`t` for "true"). If no masking operand is +specified, unmasked vector execution (`vm=1`) is assumed. + +---- + vop.v* v1, v2, v3, v0.t # enabled where v0.mask[i]=1, vm=0 + vop.v* v1, v2, v3 # unmasked vector operation, vm=1 +---- + +NOTE: Even though the current vector extensions only support one vector +mask register `v0` and only the true form of predication, the assembly +syntax writes it out in full to be compatible with future extensions +that might add a mask register specifier and support both true and +complement mask values. The `.t` suffix on the masking operand also helps +to visually encode the use of a mask. + +NOTE: The `.mask` suffix is not part of the assembly syntax. +We only append it in contexts where a mask vector is subscripted, +e.g., `v0.mask[i]`. + +[[sec-inactive-defs]] +==== Prestart, Active, Inactive, Body, and Tail Element Definitions + +The destination element indices operated on during a vector +instruction's execution can be divided into three disjoint subsets. + +* The _prestart_ elements are those whose element index is less than the +initial value in the `vstart` register. The prestart elements do not +raise exceptions and do not update the destination vector register. + +* The _body_ elements are those whose element index is greater than or equal +to the initial value in the `vstart` register, and less than the current +vector length setting in `vl`. The body can be split into two disjoint subsets: + +** The _active_ elements during a vector instruction's execution are the +elements within the body and where the current mask is enabled at that element +position. The active elements can raise exceptions and update the destination +vector register group. + +** The _inactive_ elements are the elements within the body +but where the current mask is disabled at that element +position. The inactive elements do not raise exceptions and do not +update any destination vector register group unless masked agnostic is +specified (`vtype.vma`=1), in which case inactive elements may be +overwritten with 1s. + +* The _tail_ elements during a vector instruction's execution are the +elements past the current vector length setting specified in `vl`. +The tail elements do not raise exceptions, and do not update any +destination vector register group unless tail agnostic is specified +(`vtype.vta`=1), in which case tail elements may be overwritten with +1s, or with the result of the instruction in the case of +mask-producing instructions except for mask loads. When LMUL < 1, the +tail includes the elements past VLMAX that are held in the same vector +register. + +---- + for element index x + prestart(x) = (0 <= x < vstart) + body(x) = (vstart <= x < vl) + tail(x) = (vl <= x < max(VLMAX,VLEN/SEW)) + mask(x) = unmasked || v0.mask[x] == 1 + active(x) = body(x) && mask(x) + inactive(x) = body(x) && !mask(x) +---- + +When `vstart` {ge} `vl`, there are no body elements, and no elements +are updated in any destination vector register group, including that +no tail elements are updated with agnostic values. + +NOTE: As a consequence, when `vl`=0, no elements, including agnostic +elements, are updated in the destination vector register group +regardless of `vstart`. + +Instructions that write an `x` register or `f` register +do so even when `vstart` {ge} `vl`, including when `vl`=0. + +NOTE: Some instructions such as `vslidedown` and `vrgather` may read +indices past `vl` or even VLMAX in source vector register groups. The +general policy is to return the value 0 when the index is greater than +VLMAX in the source vector register group. + +[[sec-vector-config]] +=== Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) + +One of the common approaches to handling a large number of elements is +"stripmining" where each iteration of a loop handles some number of elements, +and the iterations continue until all elements have been processed. The RISC-V +vector specification provides direct, portable support for this approach. +The application specifies the total number of elements to be processed (the application vector length or AVL) as a +candidate value for `vl`, and the hardware responds via a general-purpose +register with the (frequently smaller) number of elements that the hardware +will handle per iteration (stored in `vl`), based on the microarchitectural +implementation and the `vtype` setting. A straightforward loop structure, +shown in <<example-stripmine-sew>>, depicts the ease with which the code keeps +track of the remaining number of elements and the amount per iteration handled +by hardware. + +A set of instructions is provided to allow rapid configuration of the +values in `vl` and `vtype` to match application needs. The +`vset{i}vl{i}` instructions set the `vtype` and `vl` CSRs based on +their arguments, and write the new value of `vl` into `rd`. + +---- + vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting + vsetivli rd, uimm, vtypei # rd = new vl, uimm = AVL, vtypei = new vtype setting + vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value +---- + +include::images/wavedrom/vcfg-format.adoc[] + +==== `vtype` encoding + +include::images/wavedrom/vtype-format.adoc[] + +The new `vtype` value is encoded in the immediate fields of `vsetvli` +and `vsetivli`, and in the `rs2` register for `vsetvl`. + +---- + Suggested assembler names used for vset{i}vli vtypei immediate + + e8 # SEW=8b + e16 # SEW=16b + e32 # SEW=32b + e64 # SEW=64b + + mf8 # LMUL=1/8 + mf4 # LMUL=1/4 + mf2 # LMUL=1/2 + m1 # LMUL=1, assumed if m setting absent + m2 # LMUL=2 + m4 # LMUL=4 + m8 # LMUL=8 + +Examples: + vsetvli t0, a0, e8, ta, ma # SEW= 8, LMUL=1 + vsetvli t0, a0, e8, m2, ta, ma # SEW= 8, LMUL=2 + vsetvli t0, a0, e32, mf2, ta, ma # SEW=32, LMUL=1/2 +---- + +The `vsetvl` variant operates similarly to `vsetvli` except that it +takes a `vtype` value from `rs2` and can be used for context restore. + +===== Unsupported `vtype` Values + +If the `vtype` value is not supported by the implementation, then +the `vill` bit is set in `vtype`, the remaining bits in `vtype` are +set to zero, and the `vl` register is also set to zero. + +NOTE: Earlier drafts required a trap when setting `vtype` to an +illegal value. However, this would have added the first +data-dependent trap on a CSR write to the ISA. Implementations could +choose to trap when illegal values are written to `vtype` instead of +setting `vill`, to allow emulation to support new configurations for +forward-compatibility. The current scheme supports light-weight +runtime interrogation of the supported vector unit configurations by +checking if `vill` is clear for a given setting. + +A `vtype` value with `vill` set is treated as an unsupported +configuration. + +Implementations must consider all bits of the `vtype` value to +determine if the configuration is supported. An unsupported value in +any location within the `vtype` value must result in `vill` being set. + +NOTE: In particular, all XLEN bits of the register `vtype` argument to +the `vsetvl` instruction must be checked. Implementations cannot +ignore fields they do not implement. All bits must be checked to +ensure that new code assuming unsupported vector features in `vtype` +traps instead of executing incorrectly on an older implementation. + +==== AVL encoding + +The new vector +length setting is based on AVL, which for `vsetvli` and `vsetvl` is encoded in the `rs1` and `rd` +fields as follows: + +.AVL used in `vsetvli` and `vsetvl` instructions +[cols="2,2,10,10"] +[%autowidth,float="center",align="center",options="header"] +|=== +| `rd` | `rs1` | AVL value | Effect on `vl` +| - | !x0 | Value in `x[rs1]` | Normal stripmining +| !x0 | x0 | ~0 | Set `vl` to VLMAX +| x0 | x0 | Value in `vl` register | Keep existing `vl` (of course, `vtype` may change) +|=== + +When `rs1` is not `x0`, the AVL is an unsigned integer held in the `x` +register specified by `rs1`, and the new `vl` value is also written to +the `x` register specified by `rd`. + +When `rs1=x0` but `rd!=x0`, the maximum unsigned integer value (`~0`) +is used as the AVL, and the resulting VLMAX is written to `vl` and +also to the `x` register specified by `rd`. + +When `rs1=x0` and `rd=x0`, the instruction operates as if the current +vector length in `vl` is used as the AVL, and the resulting value is +written to `vl`, but not to a destination register. This form can +only be used when VLMAX and hence `vl` is not actually changed by the +new SEW/LMUL ratio. Use of the instruction with a new SEW/LMUL ratio +that would result in a change of VLMAX is reserved. +Use of the instruction is also reserved if `vill` was 1 beforehand. +Implementations may set `vill` in either case. + +NOTE: This last form of the instructions allows the `vtype` register to +be changed while maintaining the current `vl`, provided VLMAX is not +reduced. This design was chosen to ensure `vl` would always hold a +legal value for current `vtype` setting. The current `vl` value can +be read from the `vl` CSR. The `vl` value could be reduced by this +instruction if the new SEW/LMUL ratio causes VLMAX to shrink, and so +this case has been reserved as it is not clear this is a generally +useful operation, and implementations can otherwise assume `vl` is not +changed by this instruction to optimize their microarchitecture. + +For the `vsetivli` instruction, the AVL is encoded as a 5-bit +zero-extended immediate (0--31) in the `rs1` field. + +NOTE: The encoding of AVL for `vsetivli` is the same as for regular +CSR immediate values. + +NOTE: The `vsetivli` instruction provides more compact code when the +dimensions of vectors are small and known to fit inside the vector +registers, in which case there is no stripmining overhead. + +==== Constraints on Setting `vl` + +The `vset{i}vl{i}` instructions first set VLMAX according to their `vtype` +argument, then set `vl` obeying the following constraints: + +. `vl = AVL` if `AVL {le} VLMAX` +. `ceil(AVL / 2) {le} vl {le} VLMAX` if `AVL < (2 * VLMAX)` +. `vl = VLMAX` if `AVL {ge} (2 * VLMAX)` +. Deterministic on any given implementation for same input AVL and VLMAX values +. These specific properties follow from the prior rules: +.. `vl = 0` if `AVL = 0` +.. `vl > 0` if `AVL > 0` +.. `vl {le} VLMAX` +.. `vl {le} AVL` +.. a value read from `vl` when used as the AVL argument to `vset{i}vl{i}` results in the same +value in `vl`, provided the resultant VLMAX equals the value of VLMAX at the time that `vl` was read + +[NOTE] +-- +The `vl` setting rules are designed to be sufficiently strict to +preserve `vl` behavior across register spills and context swaps for +`AVL {le} VLMAX`, yet flexible enough to enable implementations to improve +vector lane utilization for `AVL > VLMAX`. + +For example, this permits an implementation to set `vl = ceil(AVL / 2)` +for `VLMAX < AVL < 2*VLMAX` in order to evenly distribute work over the +last two iterations of a stripmine loop. +Requirement 2 ensures that the first stripmine iteration of reduction +loops uses the largest vector length of all iterations, even in the case +of `AVL < 2*VLMAX`. +This allows software to avoid needing to explicitly calculate a running +maximum of vector lengths observed during a stripmined loop. +Requirement 2 also allows an implementation to set vl to VLMAX for `VLMAX < AVL < 2*VLMAX` +-- + +[[example-stripmine-sew]] +==== Example of stripmining and changes to SEW + +The SEW and LMUL settings can be changed dynamically to provide high +throughput on mixed-width operations in a single loop. +---- +# Example: Load 16-bit values, widen multiply to 32b, shift 32b result +# right by 3, store 32b values. +# On entry: +# a0 holds the total number of elements to process +# a1 holds the address of the source array +# a2 holds the address of the destination array + +loop: + vsetvli a3, a0, e16, m4, ta, ma # vtype = 16-bit integer vectors; + # also update a3 with vl (# of elements this iteration) + vle16.v v4, (a1) # Get 16b vector + slli t1, a3, 1 # Multiply # elements this iteration by 2 bytes/source element + add a1, a1, t1 # Bump pointer + vwmul.vx v8, v4, x10 # Widening multiply into 32b in <v8--v15> + + vsetvli x0, x0, e32, m8, ta, ma # Operate on 32b values + vsrl.vi v8, v8, 3 + vse32.v v8, (a2) # Store vector of 32b elements + slli t1, a3, 2 # Multiply # elements this iteration by 4 bytes/destination element + add a2, a2, t1 # Bump pointer + sub a0, a0, a3 # Decrement count by vl + bnez a0, loop # Any more? +---- + +[[sec-vector-memory]] +=== Vector Loads and Stores + +Vector loads and stores move values between vector registers and +memory. +Vector loads and stores can be masked, and they only access memory or raise +exceptions for active elements. +Masked vector loads do not update inactive elements in the destination vector +register group, unless masked agnostic is specified (`vtype.vma`=1). +All vector loads and stores may +generate and accept a non-zero `vstart` value. + +==== Vector Load/Store Instruction Encoding + +Vector loads and stores are encoded within the scalar floating-point +load and store major opcodes (LOAD-FP/STORE-FP). The vector load and +store encodings repurpose a portion of the standard scalar +floating-point load/store 12-bit immediate field to provide further +vector instruction encoding, with bit 25 holding the standard vector +mask bit (see <<sec-vector-mask-encoding>>). + +include::images/wavedrom/vmem-format.adoc[] + +[cols="4,12"] +|=== +| Field | Description + +| rs1[4:0] | specifies x register holding base address +| rs2[4:0] | specifies x register holding stride +| vs2[4:0] | specifies v register holding address offsets +| vs3[4:0] | specifies v register holding store data +| vd[4:0] | specifies v register destination of load +| vm | specifies whether vector masking is enabled (0 = mask enabled, 1 = mask disabled) +| width[2:0] | specifies size of memory elements, and distinguishes from FP scalar +| mew | extended memory element width. See <<sec-vector-loadstore-width-encoding>> +| mop[1:0] | specifies memory addressing mode +| nf[2:0] | specifies the number of fields in each segment, for segment load/stores +| lumop[4:0]/sumop[4:0] | are additional fields encoding variants of unit-stride instructions +|=== + +Vector memory unit-stride and constant-stride operations directly +encode EEW of the data to be transferred statically in the instruction +to reduce the number of `vtype` changes when accessing memory in a +mixed-width routine. Indexed operations use the explicit EEW encoding +in the instruction to set the size of the indices used, and use +SEW/LMUL to specify the data width. + +==== Vector Load/Store Addressing Modes + +The vector extension supports unit-stride, strided, and +indexed (scatter/gather) addressing modes. Vector load/store base +registers and strides are taken from the GPR `x` registers. + +The base effective address for all vector accesses is given by the +contents of the `x` register named in `rs1`. + +Vector unit-stride operations access elements stored contiguously in +memory starting from the base effective address. + +Vector constant-strided operations access the first memory element at the base +effective address, and then access subsequent elements at address +increments given by the byte offset contained in the `x` register +specified by `rs2`. + +Vector indexed operations add the contents of each element of the +vector offset operand specified by `vs2` to the base effective address +to give the effective address of each element. The data vector +register group has EEW=SEW, EMUL=LMUL, while the offset vector +register group has EEW encoded in the instruction and +EMUL=(EEW/SEW)*LMUL. + +The vector offset operand is treated as a vector of byte-address +offsets. + +NOTE: The indexed operations can also be used to access fields within +a vector of objects, where the `vs2` vector holds pointers to the base +of the objects and the scalar `x` register holds the offset of the +member field in each object. Supporting this case is why the indexed +operations were not defined to scale the element indices by the data +EEW. + +If the vector offset elements are narrower than XLEN, they are +zero-extended to XLEN before adding to the base effective address. If +the vector offset elements are wider than XLEN, the least-significant +XLEN bits are used in the address calculation. An implementation must +raise an illegal instruction exception if the EEW is not supported for +offset elements. + +NOTE: A profile may place an upper limit on the maximum supported index +EEW (e.g., only up to XLEN) smaller than ELEN. + +The vector addressing modes are encoded using the 2-bit `mop[1:0]` +field. + +.encoding for loads +[cols="1,1,7,6"] +|=== +2+| mop [1:0] | Description | Opcodes + +| 0 | 0 | unit-stride | VLE<EEW> +| 0 | 1 | indexed-unordered | VLUXEI<EEW> +| 1 | 0 | strided | VLSE<EEW> +| 1 | 1 | indexed-ordered | VLOXEI<EEW> +|=== + +.encoding for stores +[cols="1,1,7,6"] +|=== +2+| mop [1:0] | Description | Opcodes + +| 0 | 0 | unit-stride | VSE<EEW> +| 0 | 1 | indexed-unordered | VSUXEI<EEW> +| 1 | 0 | strided | VSSE<EEW> +| 1 | 1 | indexed-ordered | VSOXEI<EEW> +|=== + +Vector unit-stride and constant-stride memory accesses do not +guarantee ordering between individual element accesses. The vector +indexed load and store memory operations have two forms, ordered and +unordered. The indexed-ordered variants preserve element ordering on +memory accesses. + +For unordered instructions (`mop[1:0]`!=11) there is no guarantee on +element access order. If the accesses are to a strongly ordered IO +region, the element accesses can be initiated in any order. + +NOTE: To provide ordered vector accesses to a strongly ordered IO +region, the ordered indexed instructions should be used. + +For implementations with precise vector traps, exceptions on +indexed-unordered stores must also be precise. + +Additional unit-stride vector addressing modes are encoded using the +5-bit `lumop` and `sumop` fields in the unit-stride load and store +instruction encodings respectively. + +.lumop +[cols="1,1,1,1,1,11"] +|=== +5+| lumop[4:0] | Description + +| 0 | 0 | 0 | 0 | 0 | unit-stride load +| 0 | 1 | 0 | 0 | 0 | unit-stride, whole register load +| 0 | 1 | 0 | 1 | 1 | unit-stride, mask load, EEW=8 +| 1 | 0 | 0 | 0 | 0 | unit-stride fault-only-first +| x | x | x | x | x | other encodings reserved +|=== + +.sumop +[cols="1,1,1,1,1,11"] +|=== +5+| sumop[4:0] | Description + +| 0 | 0 | 0 | 0 | 0 | unit-stride store +| 0 | 1 | 0 | 0 | 0 | unit-stride, whole register store +| 0 | 1 | 0 | 1 | 1 | unit-stride, mask store, EEW=8 +| x | x | x | x | x | other encodings reserved +|=== + +The `nf[2:0]` field encodes the number of fields in each segment. For +regular vector loads and stores, `nf`=0, indicating that a single +value is moved between a vector register group and memory at each +element position. Larger values in the `nf` field are used to access +multiple contiguous fields within a segment as described below in +Section <<sec-aos>>. + +The `nf[2:0]` field also encodes the number of whole vector registers +to transfer for the whole vector register load/store instructions. + +[[sec-vector-loadstore-width-encoding]] +==== Vector Load/Store Width Encoding + +Vector loads and stores have an EEW encoded directly in the +instruction. The corresponding EMUL is calculated as EMUL = +(EEW/SEW)*LMUL. If the EMUL would be out of range (EMUL>8 or +EMUL<1/8), the instruction encoding is reserved. The vector register +groups must have legal register specifiers for the selected EMUL, +otherwise the instruction encoding is reserved. + +Vector unit-stride and constant-stride use the EEW/EMUL encoded in the +instruction for the data values, while vector indexed loads and stores +use the EEW/EMUL encoded in the instruction for the index values and +the SEW/LMUL encoded in `vtype` for the data values. + +Vector loads and stores are encoded using width values that are not +claimed by the standard scalar floating-point loads and stores. + +Implementations must provide vector loads and stores with EEWs +corresponding to all supported SEW settings. Vector load/store +encodings for unsupported EEW widths must raise an illegal +instruction exception. + +.Width encoding for vector loads and stores. +[cols="5,1,1,1,1,>3,>3,>3,3"] +|=== +| | mew 3+| width [2:0] | Mem bits | Data Reg bits | Index bits | Opcodes + +| Standard scalar FP | x | 0 | 0 | 1 | 16| FLEN | - | FLH/FSH +| Standard scalar FP | x | 0 | 1 | 0 | 32| FLEN | - | FLW/FSW +| Standard scalar FP | x | 0 | 1 | 1 | 64| FLEN | - | FLD/FSD +| Standard scalar FP | x | 1 | 0 | 0 | 128| FLEN | - | FLQ/FSQ +| Vector 8b element | 0 | 0 | 0 | 0 | 8| 8 | - | VLxE8/VSxE8 +| Vector 16b element | 0 | 1 | 0 | 1 | 16| 16 | - | VLxE16/VSxE16 +| Vector 32b element | 0 | 1 | 1 | 0 | 32| 32 | - | VLxE32/VSxE32 +| Vector 64b element | 0 | 1 | 1 | 1 | 64| 64 | - | VLxE64/VSxE64 +| Vector 8b index | 0 | 0 | 0 | 0 | SEW | SEW | 8 | VLxEI8/VSxEI8 +| Vector 16b index | 0 | 1 | 0 | 1 | SEW | SEW | 16 | VLxEI16/VSxEI16 +| Vector 32b index | 0 | 1 | 1 | 0 | SEW | SEW | 32 | VLxEI32/VSxEI32 +| Vector 64b index | 0 | 1 | 1 | 1 | SEW | SEW | 64 | VLxEI64/VSxEI64 +| Reserved | 1 | X | X | X | - | - | - | +|=== + +Mem bits is the size of each element accessed in memory. + +Data reg bits is the size of each data element accessed in register. + +Index bits is the size of each index accessed in register. + +The `mew` bit (`inst[28]`) when set is expected to be used to encode +expanded memory sizes of 128 bits and above, but these encodings are +currently reserved. + +==== Vector Unit-Stride Instructions + +---- + # Vector unit-stride loads and stores + + # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) + vle8.v vd, (rs1), vm # 8-bit unit-stride load + vle16.v vd, (rs1), vm # 16-bit unit-stride load + vle32.v vd, (rs1), vm # 32-bit unit-stride load + vle64.v vd, (rs1), vm # 64-bit unit-stride load + + # vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>) + vse8.v vs3, (rs1), vm # 8-bit unit-stride store + vse16.v vs3, (rs1), vm # 16-bit unit-stride store + vse32.v vs3, (rs1), vm # 32-bit unit-stride store + vse64.v vs3, (rs1), vm # 64-bit unit-stride store +---- + +Additional unit-stride mask load and store instructions are +provided to transfer mask values to/from memory. These +operate similarly to unmasked byte loads or stores (EEW=8), except that +the effective vector length is ``evl``=ceil(``vl``/8) (i.e. EMUL=1), +and the destination register is always written with a tail-agnostic +policy. + +---- + # Vector unit-stride mask load + vlm.v vd, (rs1) # Load byte vector of length ceil(vl/8) + + # Vector unit-stride mask store + vsm.v vs3, (rs1) # Store byte vector of length ceil(vl/8) +---- + +`vlm.v` and `vsm.v` are encoded with the same `width[2:0]`=0 encoding as +`vle8.v` and `vse8.v`, but are distinguished by different +`lumop` and `sumop` encodings. Since `vlm.v` and `vsm.v` operate as byte loads and stores, +`vstart` is in units of bytes for these instructions. + +NOTE: `vlm.v` and `vsm.v` respect the `vill` field in `vtype`, as +they depend on `vtype` indirectly through its constraints on `vl`. + +NOTE: The previous assembler mnemonics `vle1.v` and `vse1.v` were +confusing as length was handled differently for these instructions +versus other element load/store instructions. To avoid software +churn, these older assembly mnemonics are being retained as aliases. + +NOTE: The primary motivation to provide mask load and store is to +support machines that internally rearrange data to reduce +cross-datapath wiring. However, these instructions also provide a convenient +mechanism to use packed bit vectors in memory as mask values, +and also reduce the cost of mask spill/fill by reducing need to change +`vl`. + +==== Vector Strided Instructions + +---- + # Vector strided loads and stores + + # vd destination, rs1 base address, rs2 byte stride + vlse8.v vd, (rs1), rs2, vm # 8-bit strided load + vlse16.v vd, (rs1), rs2, vm # 16-bit strided load + vlse32.v vd, (rs1), rs2, vm # 32-bit strided load + vlse64.v vd, (rs1), rs2, vm # 64-bit strided load + + # vs3 store data, rs1 base address, rs2 byte stride + vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store + vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store + vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store + vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store +---- + +Negative and zero strides are supported. + +Element accesses within a strided instruction are unordered with +respect to each other. + +When `rs2`=`x0`, then an implementation is allowed, but not required, +to perform fewer memory operations than the number of active elements, +and may perform different numbers of memory operations across +different dynamic executions of the same static instruction. + +NOTE: Compilers must be aware to not use the `x0` form for rs2 when +the immediate stride is `0` if the intent is to require all memory +accesses are performed. + +When `rs2!=x0` and the value of `x[rs2]=0`, the implementation must +perform one memory access for each active element (but these accesses +will not be ordered). + +NOTE: As with other architectural mandates, implementations must +_appear_ to perform each memory access. Microarchitectures are +free to optimize away accesses that would not be observed by another +agent, for example, in idempotent memory regions obeying RVWMO. For +non-idempotent memory regions, where by definition each access can be +observed by a device, the optimization would not be possible. + +NOTE: When repeating ordered vector accesses to the same memory +address are required, then an ordered indexed operation can be used. + +==== Vector Indexed Instructions + +---- + # Vector indexed loads and stores + + # Vector indexed-unordered load instructions + # vd destination, rs1 base address, vs2 byte offsets + vluxei8.v vd, (rs1), vs2, vm # unordered 8-bit indexed load of SEW data + vluxei16.v vd, (rs1), vs2, vm # unordered 16-bit indexed load of SEW data + vluxei32.v vd, (rs1), vs2, vm # unordered 32-bit indexed load of SEW data + vluxei64.v vd, (rs1), vs2, vm # unordered 64-bit indexed load of SEW data + + # Vector indexed-ordered load instructions + # vd destination, rs1 base address, vs2 byte offsets + vloxei8.v vd, (rs1), vs2, vm # ordered 8-bit indexed load of SEW data + vloxei16.v vd, (rs1), vs2, vm # ordered 16-bit indexed load of SEW data + vloxei32.v vd, (rs1), vs2, vm # ordered 32-bit indexed load of SEW data + vloxei64.v vd, (rs1), vs2, vm # ordered 64-bit indexed load of SEW data + + # Vector indexed-unordered store instructions + # vs3 store data, rs1 base address, vs2 byte offsets + vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data + vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data + vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data + vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data + + # Vector indexed-ordered store instructions + # vs3 store data, rs1 base address, vs2 byte offsets + vsoxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data + vsoxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data + vsoxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data + vsoxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data + +---- + +NOTE: The assembler syntax for indexed loads and stores uses +``ei``__x__ instead of ``e``__x__ to indicate the statically encoded EEW +is of the index not the data. + +NOTE: The indexed operations mnemonics have a "U" or "O" to +distinguish between unordered and ordered, while the other vector +addressing modes have no character. While this is perhaps a little +less consistent, this approach minimizes disruption to existing +software, as VSXEI previously meant "ordered" - and the opcode can be +retained as an alias during transition to help reduce software churn. + +==== Unit-stride Fault-Only-First Loads + +The unit-stride fault-only-first load instructions are used to +vectorize loops with data-dependent exit conditions ("while" loops). +These instructions execute as a regular load except that they will +only take a trap caused by a synchronous exception on element 0. If +element 0 raises an exception, `vl` is not modified, and the trap is +taken. If an element > 0 raises an exception, the corresponding trap +is not taken, and the vector length `vl` is reduced to the index of +the element that would have raised an exception. + +Load instructions may overwrite active destination vector register +group elements past the element index at which the trap is reported. +Similarly, fault-only-first load instructions may update active destination +elements past the element that causes trimming of the vector length +(but not past the original vector length). The values of these +spurious updates do not have to correspond to the values in memory at +the addressed memory locations. Non-idempotent memory locations can +only be accessed when it is known the corresponding element load +operation will not be restarted due to a trap or vector-length +trimming. + +---- + # Vector unit-stride fault-only-first loads + + # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>) + vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load + vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load + vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load + vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load +---- + +---- +strlen example using unit-stride fault-only-first instruction + +include::example/strlen.s[lines=4..-1] +---- + +NOTE: There is a security concern with fault-on-first loads, as they +can be used to probe for valid effective addresses. The unit-stride +versions only allow probing a region immediately contiguous to a known +region, and so reduce the security impact when used in unprivileged +code. However, code running in S-mode can establish arbitrary page +translations that allow probing of random guest physical addresses +provided by a hypervisor. Strided and scatter/gather fault-only-first +instructions are not provided due to lack of encoding space, but they +can also represent a larger security hole, allowing even unprivileged +software to easily check multiple random pages for accessibility +without experiencing a trap. This standard does not address possible +security mitigations for fault-only-first instructions. + +Even when an exception is not raised, implementations are permitted to process +fewer than `vl` elements and reduce `vl` accordingly, but if `vstart`=0 and +`vl`>0, then at least one element must be processed. + +When the fault-only-first instruction takes a trap due to an +interrupt, implementations should not reduce `vl` and should instead +set a `vstart` value. + +NOTE: When the fault-only-first instruction would trigger a debug +data-watchpoint trap on an element after the first, implementations +should not reduce `vl` but instead should trigger the debug trap as +otherwise the event might be lost. + +[[sec-aos]] +==== Vector Load/Store Segment Instructions + +The vector load/store segment instructions move multiple contiguous +fields in memory to and from consecutively numbered vector registers. + +NOTE: The name "segment" reflects that the items moved are subarrays +with homogeneous elements. These operations can be used to transpose +arrays between memory and registers, and can support operations on +"array-of-structures" datatypes by unpacking each field in a structure +into a separate vector register. + +The three-bit `nf` field in the vector instruction encoding is an +unsigned integer that contains one less than the number of fields per +segment, _NFIELDS_. + +[[fig-nf]] +.NFIELDS Encoding +[cols="1,1,1,13"] +|=== +3+| nf[2:0] | NFIELDS + +| 0 | 0 | 0 | 1 +| 0 | 0 | 1 | 2 +| 0 | 1 | 0 | 3 +| 0 | 1 | 1 | 4 +| 1 | 0 | 0 | 5 +| 1 | 0 | 1 | 6 +| 1 | 1 | 0 | 7 +| 1 | 1 | 1 | 8 +|=== + +The EMUL setting must be such that EMUL * NFIELDS {le} 8, otherwise +the instruction encoding is reserved. + +NOTE: The product ceil(EMUL) * NFIELDS represents the number of underlying +vector registers that will be touched by a segmented load or store +instruction. This constraint makes this total no larger than 1/4 of +the architectural register file, and the same as for regular +operations with EMUL=8. + +Each field will be held in successively numbered vector register +groups. When EMUL>1, each field will occupy a vector register group +held in multiple successively numbered vector registers, and the +vector register group for each field must follow the usual vector +register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each +field's vector register group must start at an even vector register, +but does not have to start at a multiple of 8 vector register number). + +If the vector register numbers accessed by the segment load or store +would increment past 31, then the instruction encoding is reserved. + +NOTE: This constraint is to help allow for forward-compatibility with +a possible future longer instruction encoding that has more +addressable vector registers. + +The `vl` register gives the number of segments to move, which is +equal to the number of elements transferred to each vector register +group. Masking is also applied at the level of whole segments. + +For segment loads and stores, the individual memory accesses used to +access fields within each segment are unordered with respect to each +other even for ordered indexed segment loads and stores. + +The `vstart` value is in units of whole segments. If a trap occurs during +access to a segment, it is implementation-defined whether a subset +of the faulting segment's accesses are performed before the trap is taken. + +===== Vector Unit-Stride Segment Loads and Stores + +The vector unit-stride load and store segment instructions move packed +contiguous segments into multiple destination vector register groups. + +NOTE: Where the segments hold structures with heterogeneous-sized +fields, software can later unpack individual structure fields using +additional instructions after the segment load brings data into the +vector registers. + +The assembler prefixes `vlseg`/`vsseg` are used for unit-stride +segment loads and stores respectively. + +---- + # Format + vlseg<nf>e<eew>.v vd, (rs1), vm # Unit-stride segment load template + vsseg<nf>e<eew>.v vs3, (rs1), vm # Unit-stride segment store template + + # Examples + vlseg8e8.v vd, (rs1), vm # Load eight vector registers with eight byte fields. + + vsseg3e32.v vs3, (rs1), vm # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory +---- + +For loads, the `vd` register will hold the first field loaded from the +segment. For stores, the `vs3` register is read to provide the first +field to be stored to each segment. + +---- + # Example 1 + # Memory structure holds packed RGB pixels (24-bit data structure, 8bpp) + vsetvli a1, t0, e8, ta, ma + vlseg3e8.v v8, (a0), vm + # v8 holds the red pixels + # v9 holds the green pixels + # v10 holds the blue pixels + + # Example 2 + # Memory structure holds complex values, 32b for real and 32b for imaginary + vsetvli a1, t0, e32, ta, ma + vlseg2e32.v v8, (a0), vm + # v8 holds real + # v9 holds imaginary +---- + +There are also fault-only-first versions of the unit-stride instructions. + +---- + # Template for vector fault-only-first unit-stride segment loads. + vlseg<nf>e<eew>ff.v vd, (rs1), vm # Unit-stride fault-only-first segment loads +---- + +For fault-only-first segment loads, if an exception is detected partway +through accessing a segment, regardless of whether the element index is zero, +it is implementation-defined whether a subset of the segment is loaded. + +These instructions may overwrite destination vector register group +elements past the point at which a trap is reported or past the point +at which vector length is trimmed. + +===== Vector Strided Segment Loads and Stores + +Vector strided segment loads and stores move contiguous segments where +each segment is separated by the byte-stride offset given in the `rs2` +GPR argument. + +NOTE: Negative and zero strides are supported. + +---- + # Format + vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm # Strided segment loads + vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm # Strided segment stores + + # Examples + vsetvli a1, t0, e8, ta, ma + vlsseg3e8.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i], + # and bytes at addresses x5+i*x6+1 into v5[i], + # and bytes at addresses x5+i*x6+2 into v6[i]. + + # Examples + vsetvli a1, t0, e32, ta, ma + vssseg2e32.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6 + # and words from v3[i] to address x5+i*x6+4 +---- + +Accesses to the fields within each segment can occur in any order, +including the case where the byte stride is such that segments overlap +in memory. + +===== Vector Indexed Segment Loads and Stores + +Vector indexed segment loads and stores move contiguous segments where +each segment is located at an address given by adding the scalar base +address in the `rs1` field to byte offsets in vector register `vs2`. +Both ordered and unordered forms are provided, where the ordered forms +access segments in element order. However, even for the ordered form, +accesses to the fields within an individual segment are not ordered +with respect to each other. + +The data vector register group has EEW=SEW, EMUL=LMUL, while the index +vector register group has EEW encoded in the instruction with +EMUL=(EEW/SEW)*LMUL. +The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group. + +---- + # Format + vluxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-unordered segment loads + vloxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-ordered segment loads + vsuxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-unordered segment stores + vsoxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-ordered segment stores + + # Examples + vsetvli a1, t0, e8, ta, ma + vluxseg3ei8.v v4, (x5), v3 # Load bytes at addresses x5+v3[i] into v4[i], + # and bytes at addresses x5+v3[i]+1 into v5[i], + # and bytes at addresses x5+v3[i]+2 into v6[i]. + + # Examples + vsetvli a1, t0, e32, ta, ma + vsuxseg2ei32.v v2, (x5), v5 # Store words from v2[i] to address x5+v5[i] + # and words from v3[i] to address x5+v5[i]+4 +---- + +For vector indexed segment loads, the destination vector register +groups cannot overlap the source vector register group (specified by +`vs2`), else the instruction encoding is reserved. + +NOTE: This constraint supports restart of indexed segment loads +that raise exceptions partway through loading a structure. + +==== Vector Load/Store Whole Register Instructions + +Format for Vector Load Whole Register Instructions under LOAD-FP major opcode + +//// +31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0 + nf | mew| 00 | 1| 01000 | rs1 | width | vd |0000111| VL<nf>R +//// + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x07, attr: 'VL*R*'}, + {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 3, name: 'width'}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 8, attr: 'lumop'}, + {bits: 1, name: 1, attr: 'vm'}, + {bits: 2, name: 0x10000, attr: 'mop'}, + {bits: 1, name: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... + +Format for Vector Store Whole Register Instructions under STORE-FP major opcode + +//// +31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0 + nf | 0 | 00 | 1| 01000 | rs1 | 000 | vs3 |0100111| VS<nf>R +//// + +[wavedrom,,svg] +.... +{reg: [ + {bits: 7, name: 0x27, attr: 'VS*R*'}, + {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 3, name: 0x1000}, + {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 8, attr: 'sumop'}, + {bits: 1, name: 1, attr: 'vm'}, + {bits: 2, name: 0x100, attr: 'mop'}, + {bits: 1, name: 0x100, attr: 'mew'}, + {bits: 3, name: 'nf'}, +]} +.... + +These instructions load and store whole vector register groups. + +NOTE: These instructions are intended to be used to save and restore +vector registers when the type or length of the current contents of +the vector register is not known, or where modifying `vl` and `vtype` +would be costly. Examples include compiler register spills, vector +function calls where values are passed in vector registers, interrupt +handlers, and OS context switches. Software can determine the number +of bytes transferred by reading the `vlenb` register. + +The load instructions have an EEW encoded in the `mew` and `width` +fields following the pattern of regular unit-stride loads. + +NOTE: Because in-register byte layouts are identical to in-memory byte +layouts, the same data is written to the destination register group +regardless of EEW. +Hence, it would have sufficed to provide only EEW=8 variants. +The full set of EEW variants is provided so that the encoded EEW can be used +as a hint to indicate the destination register group will next be accessed +with this EEW, which aids implementations that rearrange data internally. + +The vector whole register store instructions are encoded similar to +unmasked unit-stride store of elements with EEW=8. + +The `nf` field encodes how many vector registers to load and store using the NFIELDS encoding (Figure <<fig-nf>>). +The encoded number of registers must be a power of 2 and the vector +register numbers must be aligned as with a vector register group, +otherwise the instruction encoding is reserved. NFIELDS +indicates the number of vector registers to transfer, numbered +successively after the base. Only NFIELDS values of 1, 2, 4, 8 are +supported, with other values reserved. When multiple registers are +transferred, the lowest-numbered vector register is held in the +lowest-numbered memory addresses and successive vector register +numbers are placed contiguously in memory. + +The instructions operate with an effective vector length, +`evl`=NFIELDS*VLEN/EEW, regardless of current settings in `vtype` and +`vl`. The usual property that no elements are written if `vstart` +{ge} `vl` does not apply to these instructions. Instead, no elements +are written if `vstart` {ge} `evl`. + +The instructions operate similarly to unmasked unit-stride load and +store instructions, with the base address passed in the scalar `x` +register specified by `rs1`. + +Implementations are allowed to raise a misaligned address exception on +whole register loads and stores if the base address is not naturally +aligned to the larger of the size of the encoded EEW in bytes (EEW/8) +or the implementation's smallest supported SEW size in bytes +(SEW~MIN~/8). + +NOTE: Allowing misaligned exceptions to be raised based on +non-alignment to the encoded EEW simplifies the implementation of these +instructions. Some subset implementations might not support smaller +SEW widths, so are allowed to report misaligned exceptions for the +smallest supported SEW even if larger than encoded EEW. An extreme +non-standard implementation might have SEW~MIN~>XLEN for example. Software +environments can mandate the minimum alignment requirements to support +an ABI. + +---- + # Format of whole register load and store instructions. + vl1r.v v3, (a0) # Pseudoinstruction equal to vl1re8.v + + vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0 + vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0 + vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0 + vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0 + + vl2r.v v2, (a0) # Pseudoinstruction equal to vl2re8.v + + vl2re8.v v2, (a0) # Load v2-v3 with 2*VLEN/8 bytes from address in a0 + vl2re16.v v2, (a0) # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 + vl2re32.v v2, (a0) # Load v2-v3 with 2*VLEN/32 words held at address in a0 + vl2re64.v v2, (a0) # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0 + + vl4r.v v4, (a0) # Pseudoinstruction equal to vl4re8.v + + vl4re8.v v4, (a0) # Load v4-v7 with 4*VLEN/8 bytes from address in a0 + vl4re16.v v4, (a0) + vl4re32.v v4, (a0) + vl4re64.v v4, (a0) + + vl8r.v v8, (a0) # Pseudoinstruction equal to vl8re8.v + + vl8re8.v v8, (a0) # Load v8-v15 with 8*VLEN/8 bytes from address in a0 + vl8re16.v v8, (a0) + vl8re32.v v8, (a0) + vl8re64.v v8, (a0) + + vs1r.v v3, (a1) # Store v3 to address in a1 + vs2r.v v2, (a1) # Store v2-v3 to address in a1 + vs4r.v v4, (a1) # Store v4-v7 to address in a1 + vs8r.v v8, (a1) # Store v8-v15 to address in a1 +---- + +NOTE: Implementations should raise illegal instruction exceptions on +`vl<nf>r` instructions for EEW values that are not supported. + +NOTE: We have considered adding a whole register mask load instruction +(`vl1rm.v`) but have decided to omit from initial extension. The +primary purpose would be to inform the microarchitecture that the data +will be used as a mask. The same effect can be achieved with the +following code sequence, whose cost is at most four instructions. Of +these, the first could likely be removed as `vl` is often already +in a scalar register, and the last might already be present if the +following vector instruction needs a new SEW/LMUL. So, in best case +only two instructions (of which only one performs vector operations) are needed to synthesize the effect of the +dedicated instruction: +---- + csrr t0, vl # Save current vl (potentially not needed) + vsetvli t1, x0, e8, m8, ta, ma # Maximum VLMAX + vlm.v v0, (a0) # Load mask register + vsetvli x0, t0, <new type> # Restore vl (potentially already present) +---- + +=== Vector Memory Alignment Constraints + +If an element accessed by a vector memory instruction is not naturally +aligned to the size of the element, either the element is transferred +successfully or an address misaligned exception is raised on that +element. + +Support for misaligned vector memory accesses is independent of an +implementation's support for misaligned scalar memory accesses. + +NOTE: An implementation may have neither, one, or both scalar and +vector memory accesses support some or all misaligned accesses in +hardware. A separate PMA should be defined to determine if vector +misaligned accesses are supported in the associated address range. + +Vector misaligned memory accesses follow the same rules for atomicity +as scalar misaligned memory accesses. + +=== Vector Memory Consistency Model + +Vector memory instructions appear to execute in program order on the +local hart. + +Vector memory instructions follow RVWMO at the instruction level. +If the Ztso extension is implemented, vector memory instructions additionally +follow RVTSO at the instruction level. + +Except for vector indexed-ordered loads and stores, element operations +are unordered within the instruction. + +Vector indexed-ordered loads and stores read and write elements +from/to memory in element order respectively, +obeying RVWMO at the element level. + +NOTE: Ztso only imposes RVTSO at the instruction level; intra-instruction +ordering follows RVWMO regardless of whether Ztso is implemented. + +NOTE: More formal definitions required. + +Instructions affected by the vector length register `vl` have a control +dependency on `vl`, rather than a data dependency. +Similarly, masked vector instructions have a control dependency on the source +mask register, rather than a data dependency. + +NOTE: Treating the vector length and mask as control rather than data +typically matches the semantics of the corresponding scalar code, where branch +instructions ordinarily would have been used. +Treating the mask as control allows masked vector load instructions to access +memory before the mask value is known, without the need for +a misspeculation-recovery mechanism. + +=== Vector Arithmetic Instruction Formats + +The vector arithmetic instructions use a new major opcode (OP-V = +1010111~2~) which neighbors OP-FP. The three-bit `funct3` field is +used to define sub-categories of vector instructions. + +include::images/wavedrom/valu-format.adoc[] + +[[sec-arithmetic-encoding]] +==== Vector Arithmetic Instruction encoding + +The `funct3` field encodes the operand type and source locations. + +.funct3 +[cols="1,1,1,3,5,5"] +|=== +3+| funct3[2:0] | Category | Operands | Type of scalar operand + +| 0 | 0 | 0 | OPIVV | vector-vector | N/A +| 0 | 0 | 1 | OPFVV | vector-vector | N/A +| 0 | 1 | 0 | OPMVV | vector-vector | N/A +| 0 | 1 | 1 | OPIVI | vector-immediate | `imm[4:0]` +| 1 | 0 | 0 | OPIVX | vector-scalar | GPR `x` register `rs1` +| 1 | 0 | 1 | OPFVF | vector-scalar | FP `f` register `rs1` +| 1 | 1 | 0 | OPMVX | vector-scalar | GPR `x` register `rs1` +| 1 | 1 | 1 | OPCFG | scalars-imms | GPR `x` register `rs1` & `rs2`/`imm` +|=== + +Integer operations are performed using unsigned or two's-complement +signed integer arithmetic depending on the opcode. + +NOTE: In this discussion, fixed-point operations are +considered to be integer operations. + +All standard vector floating-point arithmetic operations follow the +IEEE-754/2008 standard. All vector floating-point operations use the +dynamic rounding mode in the `frm` register. Use of the `frm` field +when it contains an invalid rounding mode by any vector floating-point +instruction--even those that do not depend on the rounding mode, or +when `vl`=0, or when `vstart` {ge} `vl`--is reserved. + +NOTE: All vector floating-point code will rely on a valid value in +`frm`. Implementations can make all vector FP instructions report +exceptions when the rounding mode is invalid to simplify control +logic. + +Vector-vector operations take two vectors of operands from vector +register groups specified by `vs2` and `vs1` respectively. + +Vector-scalar operations can have three possible forms. In all three forms, +the vector register group operand is specified by `vs2`. The second +scalar source operand comes from one of three alternative sources: + +. For integer operations, the scalar can be a 5-bit immediate, `imm[4:0]`, encoded +in the `rs1` field. The value is sign-extended to SEW bits, unless +otherwise specified. + +. For integer operations, the scalar can be taken from the scalar `x` +register specified by `rs1`. If XLEN>SEW, the least-significant SEW +bits of the `x` register are used, unless otherwise specified. If +XLEN<SEW, the value from the `x` register is sign-extended to SEW +bits. + +. For floating-point operations, the scalar can be taken from a scalar +`f` register. If FLEN > SEW, the value in the `f` registers is +checked for a valid NaN-boxed value, in which case the +least-significant SEW bits of the `f` register are used, else the +canonical NaN value is used. Vector instructions where any +floating-point vector operand's EEW is not a supported floating-point +type width (which includes when FLEN < SEW) are reserved. + +NOTE: Some instructions _zero_-extend the 5-bit immediate, and denote this +by naming the immediate `uimm` in the assembly syntax. + +NOTE: When adding a vector extension to the Zfinx/Zdinx/Zhinx +extensions, floating-point scalar arguments are taken from the `x` +registers. NaN-boxing is not supported in these extensions, and so +the vector floating-point scalar value is produced using the same +rules as for an integer scalar operand (i.e., when XLEN > SEW use the +lowest SEW bits, when XLEN < SEW use the sign-extended value). + +Vector arithmetic instructions are masked under control of the `vm` +field. + +---- +# Assembly syntax pattern for vector binary arithmetic instructions + +# Operations returning vector results, masked by vm (v0.t, <nothing>) +vop.vv vd, vs2, vs1, vm # integer vector-vector vd[i] = vs2[i] op vs1[i] +vop.vx vd, vs2, rs1, vm # integer vector-scalar vd[i] = vs2[i] op x[rs1] +vop.vi vd, vs2, imm, vm # integer vector-immediate vd[i] = vs2[i] op imm + +vfop.vv vd, vs2, vs1, vm # FP vector-vector operation vd[i] = vs2[i] fop vs1[i] +vfop.vf vd, vs2, rs1, vm # FP vector-scalar operation vd[i] = vs2[i] fop f[rs1] +---- + +NOTE: In the encoding, `vs2` is the first operand, while `rs1/imm` +is the second operand. This is the opposite to the standard scalar +ordering. This arrangement retains the existing encoding conventions +that instructions that read only one scalar register, read it from +`rs1`, and that 5-bit immediates are sourced from the `rs1` field. + +---- +# Assembly syntax pattern for vector ternary arithmetic instructions (multiply-add) + +# Integer operations overwriting sum input +vop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] +vop.vx vd, rs1, vs2, vm # vd[i] = x[rs1] * vs2[i] + vd[i] + +# Integer operations overwriting product input +vop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vd[i] + vs2[i] +vop.vx vd, rs1, vs2, vm # vd[i] = x[rs1] * vd[i] + vs2[i] + +# Floating-point operations overwriting sum input +vfop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vs2[i] + vd[i] +vfop.vf vd, rs1, vs2, vm # vd[i] = f[rs1] * vs2[i] + vd[i] + +# Floating-point operations overwriting product input +vfop.vv vd, vs1, vs2, vm # vd[i] = vs1[i] * vd[i] + vs2[i] +vfop.vf vd, rs1, vs2, vm # vd[i] = f[rs1] * vd[i] + vs2[i] +---- + +NOTE: For ternary multiply-add operations, the assembler syntax always +places the destination vector register first, followed by either `rs1` +or `vs1`, then `vs2`. This ordering provides a more natural reading +of the assembler for these ternary operations, as the multiply +operands are always next to each other. + +[[sec-widening]] +==== Widening Vector Arithmetic Instructions + +A few vector arithmetic instructions are defined to be __widening__ +operations where the destination vector register group has EEW=2*SEW +and EMUL=2*LMUL. These are generally given a `vw*` prefix on the +opcode, or `vfw*` for vector floating-point instructions. + +The first vector register group operand can be either single or +double-width. + +---- +Assembly syntax pattern for vector widening arithmetic instructions + +# Double-width result, two single-width sources: 2*SEW = SEW op SEW +vwop.vv vd, vs2, vs1, vm # integer vector-vector vd[i] = vs2[i] op vs1[i] +vwop.vx vd, vs2, rs1, vm # integer vector-scalar vd[i] = vs2[i] op x[rs1] + +# Double-width result, first source double-width, second source single-width: 2*SEW = 2*SEW op SEW +vwop.wv vd, vs2, vs1, vm # integer vector-vector vd[i] = vs2[i] op vs1[i] +vwop.wx vd, vs2, rs1, vm # integer vector-scalar vd[i] = vs2[i] op x[rs1] +---- + +NOTE: Originally, a `w` suffix was used on opcode, but this could be +confused with the use of a `w` suffix to mean word-sized operations in +doubleword integers, so the `w` was moved to prefix. + +NOTE: The floating-point widening operations were changed to `vfw*` +from `vwf*` to be more consistent with any scalar widening +floating-point operations that will be written as `fw*`. + +Widening instruction encodings must follow the constraints in Section +<<sec-vec-operands>>. + +[[sec-narrowing]] +==== Narrowing Vector Arithmetic Instructions + +A few instructions are provided to convert double-width source vectors +into single-width destination vectors. These instructions convert a +vector register group specified by `vs2` with EEW/EMUL=2*SEW/2*LMUL to a vector register +group with the current SEW/LMUL setting. Where there is a second +source vector register group (specified by `vs1`), this has the same +(narrower) width as the result (i.e., EEW=SEW). + +NOTE: An alternative design decision would have been to treat SEW/LMUL +as defining the size of the source vector register group. The choice +here is motivated by the belief the chosen approach will require fewer +`vtype` changes. + +NOTE: Compare operations that set a mask register are also +implicitly a narrowing operation. + +A `vn*` prefix on the opcode is used to distinguish these instructions +in the assembler, or a `vfn*` prefix for narrowing floating-point +opcodes. The double-width source vector register group is signified +by a `w` in the source operand suffix (e.g., `vnsra.wv`) + +---- +Assembly syntax pattern for vector narrowing arithmetic instructions + +# Single-width result vd, double-width source vs2, single-width source vs1/rs1 +# SEW = 2*SEW op SEW +vnop.wv vd, vs2, vs1, vm # integer vector-vector vd[i] = vs2[i] op vs1[i] +vnop.wx vd, vs2, rs1, vm # integer vector-scalar vd[i] = vs2[i] op x[rs1] +---- + +Narrowing instruction encodings must follow the constraints in Section +<<sec-vec-operands>>. + +[[sec-vector-integer]] +=== Vector Integer Arithmetic Instructions + +A set of vector integer arithmetic instructions is provided. Unless +otherwise stated, integer operations wrap around on overflow. + +==== Vector Single-Width Integer Add and Subtract + +Vector integer add and subtract are provided. Reverse-subtract +instructions are also provided for the vector-scalar forms. + +---- +# Integer adds. +vadd.vv vd, vs2, vs1, vm # Vector-vector +vadd.vx vd, vs2, rs1, vm # vector-scalar +vadd.vi vd, vs2, imm, vm # vector-immediate + +# Integer subtract +vsub.vv vd, vs2, vs1, vm # Vector-vector +vsub.vx vd, vs2, rs1, vm # vector-scalar + +# Integer reverse subtract +vrsub.vx vd, vs2, rs1, vm # vd[i] = x[rs1] - vs2[i] +vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i] +---- + +NOTE: A vector of integer values can be negated using a +reverse-subtract instruction with a scalar operand of `x0`. An +assembly pseudoinstruction `vneg.v vd,vs` = `vrsub.vx vd,vs,x0` is provided. + +==== Vector Widening Integer Add/Subtract + +The widening add/subtract instructions are provided in both signed and +unsigned variants, depending on whether the narrower source operands +are first sign- or zero-extended before forming the double-width sum. + +---- +# Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW +vwaddu.vv vd, vs2, vs1, vm # vector-vector +vwaddu.vx vd, vs2, rs1, vm # vector-scalar +vwsubu.vv vd, vs2, vs1, vm # vector-vector +vwsubu.vx vd, vs2, rs1, vm # vector-scalar + +# Widening signed integer add/subtract, 2*SEW = SEW +/- SEW +vwadd.vv vd, vs2, vs1, vm # vector-vector +vwadd.vx vd, vs2, rs1, vm # vector-scalar +vwsub.vv vd, vs2, vs1, vm # vector-vector +vwsub.vx vd, vs2, rs1, vm # vector-scalar + +# Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW +vwaddu.wv vd, vs2, vs1, vm # vector-vector +vwaddu.wx vd, vs2, rs1, vm # vector-scalar +vwsubu.wv vd, vs2, vs1, vm # vector-vector +vwsubu.wx vd, vs2, rs1, vm # vector-scalar + +# Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW +vwadd.wv vd, vs2, vs1, vm # vector-vector +vwadd.wx vd, vs2, rs1, vm # vector-scalar +vwsub.wv vd, vs2, vs1, vm # vector-vector +vwsub.wx vd, vs2, rs1, vm # vector-scalar +---- + +NOTE: An integer value can be doubled in width using the widening add +instructions with a scalar operand of `x0`. Assembly +pseudoinstructions `vwcvt.x.x.v vd,vs,vm` = `vwadd.vx vd,vs,x0,vm` and +`vwcvtu.x.x.v vd,vs,vm` = `vwaddu.vx vd,vs,x0,vm` are provided. + +==== Vector Integer Extension + +The vector integer extension instructions zero- or sign-extend a +source vector integer operand with EEW less than SEW to fill SEW-sized +elements in the destination. The EEW of the source is 1/2, 1/4, or +1/8 of SEW, while EMUL of the source is (EEW/SEW)*LMUL. The +destination has EEW equal to SEW and EMUL equal to LMUL. + +---- +vzext.vf2 vd, vs2, vm # Zero-extend SEW/2 source to SEW destination +vsext.vf2 vd, vs2, vm # Sign-extend SEW/2 source to SEW destination +vzext.vf4 vd, vs2, vm # Zero-extend SEW/4 source to SEW destination +vsext.vf4 vd, vs2, vm # Sign-extend SEW/4 source to SEW destination +vzext.vf8 vd, vs2, vm # Zero-extend SEW/8 source to SEW destination +vsext.vf8 vd, vs2, vm # Sign-extend SEW/8 source to SEW destination +---- + +If the source EEW is not a supported width, or source EMUL would be +below the minimum legal LMUL, the instruction encoding is reserved. + +NOTE: Standard vector load instructions access memory values that are +the same size as the destination register elements. Some application +code needs to operate on a range of operand widths in a wider element, +for example, loading a byte from memory and adding to an eight-byte +element. To avoid having to provide the cross-product of the number +of vector load instructions by the number of data types (byte, word, +halfword, and also signed/unsigned variants), we instead add explicit +extension instructions that can be used if an appropriate widening +arithmetic instruction is not available. + +==== Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions + +To support multi-word integer arithmetic, instructions that operate on +a carry bit are provided. For each operation (add or subtract), two +instructions are provided: one to provide the result (SEW width), and +the second to generate the carry output (single bit encoded as a mask +boolean). + +The carry inputs and outputs are represented using the mask register +layout as described in Section <<sec-mask-register-layout>>. Due to +encoding constraints, the carry input must come from the implicit `v0` +register, but carry outputs can be written to any vector register that +respects the source/destination overlap restrictions. + +`vadc` and `vsbc` add or subtract the source operands and the carry-in or +borrow-in, and write the result to vector register `vd`. +These instructions are encoded as masked instructions (`vm=0`), but they operate +on and write back all body elements. +Encodings corresponding to the unmasked versions (`vm=1`) are reserved. + +`vmadc` and `vmsbc` add or subtract the source operands, optionally +add the carry-in or subtract the borrow-in if masked (`vm=0`), and +write the result back to mask register `vd`. If unmasked (`vm=1`), +there is no carry-in or borrow-in. These instructions operate on and +write back all body elements, even if masked. Because these +instructions produce a mask value, they always operate with a +tail-agnostic policy. + +---- + # Produce sum with carry. + + # vd[i] = vs2[i] + vs1[i] + v0.mask[i] + vadc.vvm vd, vs2, vs1, v0 # Vector-vector + + # vd[i] = vs2[i] + x[rs1] + v0.mask[i] + vadc.vxm vd, vs2, rs1, v0 # Vector-scalar + + # vd[i] = vs2[i] + imm + v0.mask[i] + vadc.vim vd, vs2, imm, v0 # Vector-immediate + + # Produce carry out in mask register format + + # vd.mask[i] = carry_out(vs2[i] + vs1[i] + v0.mask[i]) + vmadc.vvm vd, vs2, vs1, v0 # Vector-vector + + # vd.mask[i] = carry_out(vs2[i] + x[rs1] + v0.mask[i]) + vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar + + # vd.mask[i] = carry_out(vs2[i] + imm + v0.mask[i]) + vmadc.vim vd, vs2, imm, v0 # Vector-immediate + + # vd.mask[i] = carry_out(vs2[i] + vs1[i]) + vmadc.vv vd, vs2, vs1 # Vector-vector, no carry-in + + # vd.mask[i] = carry_out(vs2[i] + x[rs1]) + vmadc.vx vd, vs2, rs1 # Vector-scalar, no carry-in + + # vd.mask[i] = carry_out(vs2[i] + imm) + vmadc.vi vd, vs2, imm # Vector-immediate, no carry-in +---- + +Because implementing a carry propagation requires executing two +instructions with unchanged inputs, destructive accumulations will +require an additional move to obtain correct results. + +---- + # Example multi-word arithmetic sequence, accumulating into v4 + vmadc.vvm v1, v4, v8, v0 # Get carry into temp register v1 + vadc.vvm v4, v4, v8, v0 # Calc new sum + vmmv.m v0, v1 # Move temp carry into v0 for next word +---- + +The subtract with borrow instruction `vsbc` performs the equivalent +function to support long word arithmetic for subtraction. There are +no subtract with immediate instructions. + +---- + # Produce difference with borrow. + + # vd[i] = vs2[i] - vs1[i] - v0.mask[i] + vsbc.vvm vd, vs2, vs1, v0 # Vector-vector + + # vd[i] = vs2[i] - x[rs1] - v0.mask[i] + vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar + + # Produce borrow out in mask register format + + # vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i]) + vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector + + # vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i]) + vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar + + # vd.mask[i] = borrow_out(vs2[i] - vs1[i]) + vmsbc.vv vd, vs2, vs1 # Vector-vector, no borrow-in + + # vd.mask[i] = borrow_out(vs2[i] - x[rs1]) + vmsbc.vx vd, vs2, rs1 # Vector-scalar, no borrow-in +---- + +For `vmsbc`, the borrow is defined to be 1 iff the difference, prior to +truncation, is negative. + +For `vadc` and `vsbc`, the instruction encoding is reserved if the +destination vector register is `v0`. + +NOTE: This constraint corresponds to the constraint on masked vector +operations that overwrite the mask register. + +==== Vector Bitwise Logical Instructions + +---- +# Bitwise logical operations. +vand.vv vd, vs2, vs1, vm # Vector-vector +vand.vx vd, vs2, rs1, vm # vector-scalar +vand.vi vd, vs2, imm, vm # vector-immediate + +vor.vv vd, vs2, vs1, vm # Vector-vector +vor.vx vd, vs2, rs1, vm # vector-scalar +vor.vi vd, vs2, imm, vm # vector-immediate + +vxor.vv vd, vs2, vs1, vm # Vector-vector +vxor.vx vd, vs2, rs1, vm # vector-scalar +vxor.vi vd, vs2, imm, vm # vector-immediate +---- + +NOTE: With an immediate of -1, scalar-immediate forms of the `vxor` +instruction provide a bitwise NOT operation. This is provided as +an assembler pseudoinstruction `vnot.v vd,vs,vm` = `vxor.vi vd,vs,-1,vm`. + +==== Vector Single-Width Shift Instructions + +A full set of vector shift instructions are provided, including +logical shift left (`sll`), and logical (zero-extending `srl`) and +arithmetic (sign-extending `sra`) shift right. The data to be shifted +is in the vector register group specified by `vs2` and the shift +amount value can come from a vector register group `vs1`, a scalar +integer register `rs1`, or a zero-extended 5-bit immediate. Only the low +lg2(SEW) bits of the shift-amount value are used to control the shift +amount. + +---- +# Bit shift operations +vsll.vv vd, vs2, vs1, vm # Vector-vector +vsll.vx vd, vs2, rs1, vm # vector-scalar +vsll.vi vd, vs2, uimm, vm # vector-immediate + +vsrl.vv vd, vs2, vs1, vm # Vector-vector +vsrl.vx vd, vs2, rs1, vm # vector-scalar +vsrl.vi vd, vs2, uimm, vm # vector-immediate + +vsra.vv vd, vs2, vs1, vm # Vector-vector +vsra.vx vd, vs2, rs1, vm # vector-scalar +vsra.vi vd, vs2, uimm, vm # vector-immediate +---- + +==== Vector Narrowing Integer Right Shift Instructions + +The narrowing right shifts extract a smaller field from a wider +operand and have both zero-extending (`srl`) and sign-extending +(`sra`) forms. The shift amount can come from a vector register +group, or a scalar `x` register, or a zero-extended 5-bit immediate. +The low lg2(2*SEW) bits of the shift-amount value are +used (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing +operation). + +---- + # Narrowing shift right logical, SEW = (2*SEW) >> SEW + vnsrl.wv vd, vs2, vs1, vm # vector-vector + vnsrl.wx vd, vs2, rs1, vm # vector-scalar + vnsrl.wi vd, vs2, uimm, vm # vector-immediate + + # Narrowing shift right arithmetic, SEW = (2*SEW) >> SEW + vnsra.wv vd, vs2, vs1, vm # vector-vector + vnsra.wx vd, vs2, rs1, vm # vector-scalar + vnsra.wi vd, vs2, uimm, vm # vector-immediate +---- + +NOTE: Future extensions might add support for versions that narrow to +a destination that is 1/4 the width of the source. + +NOTE: An integer value can be halved in width using the narrowing integer +shift instructions with a scalar operand of `x0`. An assembly +pseudoinstruction is provided `vncvt.x.x.w vd,vs,vm` = `vnsrl.wx vd,vs,x0,vm`. + +==== Vector Integer Compare Instructions + +The following integer compare instructions write 1 to the destination +mask register element if the comparison evaluates to true, and 0 +otherwise. The destination mask vector is always held in a single +vector register, with a layout of elements as described in Section +<<sec-mask-register-layout>>. The destination mask vector register +may be the same as the source vector mask register (`v0`). + +---- +# Set if equal +vmseq.vv vd, vs2, vs1, vm # Vector-vector +vmseq.vx vd, vs2, rs1, vm # vector-scalar +vmseq.vi vd, vs2, imm, vm # vector-immediate + +# Set if not equal +vmsne.vv vd, vs2, vs1, vm # Vector-vector +vmsne.vx vd, vs2, rs1, vm # vector-scalar +vmsne.vi vd, vs2, imm, vm # vector-immediate + +# Set if less than, unsigned +vmsltu.vv vd, vs2, vs1, vm # Vector-vector +vmsltu.vx vd, vs2, rs1, vm # Vector-scalar + +# Set if less than, signed +vmslt.vv vd, vs2, vs1, vm # Vector-vector +vmslt.vx vd, vs2, rs1, vm # vector-scalar + +# Set if less than or equal, unsigned +vmsleu.vv vd, vs2, vs1, vm # Vector-vector +vmsleu.vx vd, vs2, rs1, vm # vector-scalar +vmsleu.vi vd, vs2, imm, vm # Vector-immediate + +# Set if less than or equal, signed +vmsle.vv vd, vs2, vs1, vm # Vector-vector +vmsle.vx vd, vs2, rs1, vm # vector-scalar +vmsle.vi vd, vs2, imm, vm # vector-immediate + +# Set if greater than, unsigned +vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar +vmsgtu.vi vd, vs2, imm, vm # Vector-immediate + +# Set if greater than, signed +vmsgt.vx vd, vs2, rs1, vm # Vector-scalar +vmsgt.vi vd, vs2, imm, vm # Vector-immediate + +# Following two instructions are not provided directly +# Set if greater than or equal, unsigned +# vmsgeu.vx vd, vs2, rs1, vm # Vector-scalar +# Set if greater than or equal, signed +# vmsge.vx vd, vs2, rs1, vm # Vector-scalar +---- + +The following table indicates how all comparisons are implemented in +native machine code. + +---- +Comparison Assembler Mapping Assembler Pseudoinstruction + +va < vb vmslt{u}.vv vd, va, vb, vm +va <= vb vmsle{u}.vv vd, va, vb, vm +va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm +va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm + +va < x vmslt{u}.vx vd, va, x, vm +va <= x vmsle{u}.vx vd, va, x, vm +va > x vmsgt{u}.vx vd, va, x, vm +va >= x see below + +va < i vmsle{u}.vi vd, va, i-1, vm vmslt{u}.vi vd, va, i, vm +va <= i vmsle{u}.vi vd, va, i, vm +va > i vmsgt{u}.vi vd, va, i, vm +va >= i vmsgt{u}.vi vd, va, i-1, vm vmsge{u}.vi vd, va, i, vm + +va, vb vector register groups +x scalar integer register +i immediate +---- + +NOTE: The immediate forms of `vmslt{u}.vi` are not provided as the +immediate value can be decreased by 1 and the `vmsle{u}.vi` variants +used instead. The `vmsle.vi` range is -16 to 15, resulting in an +effective `vmslt.vi` range of -15 to 16. The `vmsleu.vi` range is 0 +to 15 giving an effective `vmsltu.vi` range of 1 to 16 (Note, +`vmsltu.vi` with immediate 0 is not useful as it is always +false). + +NOTE: Because the 5-bit vector immediates are always sign-extended, +when the high bit of the `simm5` immediate is set, `vmsleu.vi` also +supports unsigned immediate values in the range `2^SEW^-16` to +`2^SEW^-1`, allowing corresponding `vmsltu.vi` compares against +unsigned immediates in the range `2^SEW^-15` to `2^SEW^`. Note that +`vmsltu.vi` with immediate `2^SEW^` is not useful as it is always +true. + +Similarly, `vmsge{u}.vi` is not provided and the compare is +implemented using `vmsgt{u}.vi` with the immediate decremented by one. +The resulting effective `vmsge.vi` range is -15 to 16, and the +resulting effective `vmsgeu.vi` range is 1 to 16 (Note, `vmsgeu.vi` with +immediate 0 is not useful as it is always true). + +NOTE: The `vmsgt` forms for register scalar and immediates are provided +to allow a single compare instruction to provide the correct +polarity of mask value without using additional mask logical +instructions. + +To reduce encoding space, the `vmsge{u}.vx` form is not directly +provided, and so the `va {ge} x` case requires special treatment. + +NOTE: The `vmsge{u}.vx` could potentially be encoded in a +non-orthogonal way under the unused OPIVI variant of `vmslt{u}`. These +would be the only instructions in OPIVI that use a scalar `x`register +however. Alternatively, a further two funct6 encodings could be used, +but these would have a different operand format (writes to mask +register) than others in the same group of 8 funct6 encodings. The +current PoR is to omit these instructions and to synthesize where +needed as described below. + +The `vmsge{u}.vx` operation can be synthesized by reducing the +value of `x` by 1 and using the `vmsgt{u}.vx` instruction, when it is +known that this will not underflow the representation in `x`. + +---- +Sequences to synthesize `vmsge{u}.vx` instruction + +va >= x, x > minimum + + addi t0, x, -1; vmsgt{u}.vx vd, va, t0, vm +---- + +The above sequence will usually be the most efficient implementation, +but assembler pseudoinstructions can be provided for cases where the +range of `x` is unknown. + +---- +unmasked va >= x + + pseudoinstruction: vmsge{u}.vx vd, va, x + expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd + +masked va >= x, vd != v0 + + pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t + expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 + +masked va >= x, vd == v0 + + pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt + expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt + +masked va >= x, any vd + + pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt + expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd, vd, v0; vmor.mm vd, vt, vd + + The vt argument to the pseudoinstruction must name a temporary vector register that is + not same as vd and which will be clobbered by the pseudoinstruction +---- + +Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is `v0`, e.g., + +---- + # (a < b) && (b < c) in two instructions when mask-undisturbed + vmslt.vv v0, va, vb # All body elements written + vmslt.vv v0, vb, vc, v0.t # Only update at set mask +---- + +Compares write mask registers, and so always operate under a +tail-agnostic policy. + +==== Vector Integer Min/Max Instructions + +Signed and unsigned integer minimum and maximum instructions are +supported. + +---- +# Unsigned minimum +vminu.vv vd, vs2, vs1, vm # Vector-vector +vminu.vx vd, vs2, rs1, vm # vector-scalar + +# Signed minimum +vmin.vv vd, vs2, vs1, vm # Vector-vector +vmin.vx vd, vs2, rs1, vm # vector-scalar + +# Unsigned maximum +vmaxu.vv vd, vs2, vs1, vm # Vector-vector +vmaxu.vx vd, vs2, rs1, vm # vector-scalar + +# Signed maximum +vmax.vv vd, vs2, vs1, vm # Vector-vector +vmax.vx vd, vs2, rs1, vm # vector-scalar +---- + +==== Vector Single-Width Integer Multiply Instructions + +The single-width multiply instructions perform a SEW-bit*SEW-bit +multiply to generate a 2*SEW-bit product, then return one half of the +product in the SEW-bit-wide destination. The `*mul*` versions write +the low word of the product to the destination register, while the +`*mulh*` versions write the high word of the product to the +destination register. + +---- +# Signed multiply, returning low bits of product +vmul.vv vd, vs2, vs1, vm # Vector-vector +vmul.vx vd, vs2, rs1, vm # vector-scalar + +# Signed multiply, returning high bits of product +vmulh.vv vd, vs2, vs1, vm # Vector-vector +vmulh.vx vd, vs2, rs1, vm # vector-scalar + +# Unsigned multiply, returning high bits of product +vmulhu.vv vd, vs2, vs1, vm # Vector-vector +vmulhu.vx vd, vs2, rs1, vm # vector-scalar + +# Signed(vs2)-Unsigned multiply, returning high bits of product +vmulhsu.vv vd, vs2, vs1, vm # Vector-vector +vmulhsu.vx vd, vs2, rs1, vm # vector-scalar +---- + +NOTE: There is no `vmulhus.vx` opcode to return high half of +unsigned-vector * signed-scalar product. The scalar can be splatted +to a vector, then a `vmulhsu.vv` used. + +NOTE: The current `vmulh*` opcodes perform simple fractional +multiplies, but with no option to scale, round, and/or saturate the +result. A possible future extension can consider variants of `vmulh`, +`vmulhu`, `vmulhsu` that use the `vxrm` rounding mode when discarding +low half of product. There is no possibility of overflow in these +cases. + +==== Vector Integer Divide Instructions + +The divide and remainder instructions are equivalent to the RISC-V +standard scalar integer multiply/divides, with the same results for +extreme inputs. + +---- + # Unsigned divide. + vdivu.vv vd, vs2, vs1, vm # Vector-vector + vdivu.vx vd, vs2, rs1, vm # vector-scalar + + # Signed divide + vdiv.vv vd, vs2, vs1, vm # Vector-vector + vdiv.vx vd, vs2, rs1, vm # vector-scalar + + # Unsigned remainder + vremu.vv vd, vs2, vs1, vm # Vector-vector + vremu.vx vd, vs2, rs1, vm # vector-scalar + + # Signed remainder + vrem.vv vd, vs2, vs1, vm # Vector-vector + vrem.vx vd, vs2, rs1, vm # vector-scalar +---- + +NOTE: The decision to include integer divide and remainder was +contentious. The argument in favor is that without a standard +instruction, software would have to pick some algorithm to perform the +operation, which would likely perform poorly on some +microarchitectures versus others. + +NOTE: There is no instruction to perform a "scalar divide by vector" +operation. + +==== Vector Widening Integer Multiply Instructions + +The widening integer multiply instructions return the full 2*SEW-bit +product from an SEW-bit*SEW-bit multiply. + +---- +# Widening signed-integer multiply +vwmul.vv vd, vs2, vs1, vm # vector-vector +vwmul.vx vd, vs2, rs1, vm # vector-scalar + +# Widening unsigned-integer multiply +vwmulu.vv vd, vs2, vs1, vm # vector-vector +vwmulu.vx vd, vs2, rs1, vm # vector-scalar + +# Widening signed(vs2)-unsigned integer multiply +vwmulsu.vv vd, vs2, vs1, vm # vector-vector +vwmulsu.vx vd, vs2, rs1, vm # vector-scalar +---- + +==== Vector Single-Width Integer Multiply-Add Instructions + +The integer multiply-add instructions are destructive and are provided +in two forms, one that overwrites the addend or minuend +(`vmacc`, `vnmsac`) and one that overwrites the first multiplicand +(`vmadd`, `vnmsub`). + +The low half of the product is added or subtracted from the third operand. + +NOTE: `sac` is intended to be read as "subtract from accumulator". The +opcode is `vnmsac` to match the (unfortunately counterintuitive) +floating-point `fnmsub` instruction definition. Similarly for the +`vnmsub` opcode. + +---- +# Integer multiply-add, overwrite addend +vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] + +# Integer multiply-sub, overwrite minuend +vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] +vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] + +# Integer multiply-add, overwrite multiplicand +vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] +vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] + +# Integer multiply-sub, overwrite multiplicand +vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] +vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i] +---- + +==== Vector Widening Integer Multiply-Add Instructions + +The widening integer multiply-add instructions add the full 2*SEW-bit +product from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and +produce a 2*SEW-bit result. All combinations of signed and unsigned +multiply operands are supported. + +---- +# Widening unsigned-integer multiply-add, overwrite addend +vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] + +# Widening signed-integer multiply-add, overwrite addend +vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] + +# Widening signed-unsigned-integer multiply-add, overwrite addend +vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] +vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] + +# Widening unsigned-signed-integer multiply-add, overwrite addend +vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i] +---- + +==== Vector Integer Merge Instructions + +The vector integer merge instructions combine two source operands +based on a mask. Unlike regular arithmetic instructions, the +merge operates on all body elements (i.e., the set of elements from +`vstart` up to the current vector length in `vl`). + +The `vmerge` instructions are encoded as masked instructions (`vm=0`). +The instructions combine two +sources as follows. At elements where the mask value is zero, the +first operand is copied to the destination element, otherwise the +second operand is copied to the destination element. The first +operand is always a vector register group specified by `vs2`. The +second operand is a vector register group specified by `vs1` or a +scalar `x` register specified by `rs1` or a 5-bit sign-extended +immediate. + +---- +vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] +vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] +vmerge.vim vd, vs2, imm, v0 # vd[i] = v0.mask[i] ? imm : vs2[i] +---- + +==== Vector Integer Move Instructions + +The vector integer move instructions copy a source operand to a vector +register group. +The `vmv.v.v` variant copies a vector register group, whereas the `vmv.v.x` +and `vmv.v.i` variants __splat__ a scalar register or immediate to all active +elements of the destination vector register group. +These instructions are encoded as unmasked instructions (`vm=1`). +The first operand specifier (`vs2`) must contain `v0`, and any other vector +register number in `vs2` is _reserved_. + +---- +vmv.v.v vd, vs1 # vd[i] = vs1[i] +vmv.v.x vd, rs1 # vd[i] = x[rs1] +vmv.v.i vd, imm # vd[i] = imm +---- + +NOTE: Mask values can be widened into SEW-width elements using a +sequence `vmv.v.i vd, 0; vmerge.vim vd, vd, 1, v0`. + +NOTE: The vector integer move instructions share the encoding with the vector +merge instructions, but with `vm=1` and `vs2=v0`. + +The form `vmv.v.v vd, vd`, which leaves body elements unchanged, +can be used to indicate that the register will next be used +with an EEW equal to SEW. + +NOTE: Implementations that internally reorganize data according to EEW +can shuffle the internal representation according to SEW. +Implementations that do not internally reorganize data can dynamically +elide this instruction, and treat as a NOP. + +NOTE: The `vmv.v.v vd. vd` instruction is not a RISC-V HINT as a +tail-agnostic setting may cause an architectural state change on some +implementations. + +[[sec-vector-fixed-point]] +=== Vector Fixed-Point Arithmetic Instructions + +The preceding set of integer arithmetic instructions is extended to support +fixed-point arithmetic. + +A fixed-point number is a two's-complement signed or unsigned integer +interpreted as the numerator in a fraction with an implicit denominator. +The fixed-point instructions are intended to be applied to the numerators; +it is the responsibility of software to manage the denominators. +An N-bit element can hold two's-complement signed integers in the +range -2^N-1^...+2^N-1^-1, and unsigned integers in the range 0 +... +2^N^-1. The fixed-point instructions help preserve precision in +narrow operands by supporting scaling and rounding, and can handle +overflow by saturating results into the destination format range. + +NOTE: The widening integer operations described above can also be used +to avoid overflow. + +==== Vector Single-Width Saturating Add and Subtract + +Saturating forms of integer add and subtract are provided, for both +signed and unsigned integers. If the result would overflow the +destination, the result is replaced with the closest representable +value, and the `vxsat` bit is set. + +---- +# Saturating adds of unsigned integers. +vsaddu.vv vd, vs2, vs1, vm # Vector-vector +vsaddu.vx vd, vs2, rs1, vm # vector-scalar +vsaddu.vi vd, vs2, imm, vm # vector-immediate + +# Saturating adds of signed integers. +vsadd.vv vd, vs2, vs1, vm # Vector-vector +vsadd.vx vd, vs2, rs1, vm # vector-scalar +vsadd.vi vd, vs2, imm, vm # vector-immediate + +# Saturating subtract of unsigned integers. +vssubu.vv vd, vs2, vs1, vm # Vector-vector +vssubu.vx vd, vs2, rs1, vm # vector-scalar + +# Saturating subtract of signed integers. +vssub.vv vd, vs2, vs1, vm # Vector-vector +vssub.vx vd, vs2, rs1, vm # vector-scalar +---- + +==== Vector Single-Width Averaging Add and Subtract + +The averaging add and subtract instructions right shift the result by +one bit and round off the result according to the setting in `vxrm`. +Both unsigned and signed versions are provided. +For `vaaddu` and `vaadd` there can be no overflow in the result. +For `vasub` and `vasubu`, overflow is ignored and the result wraps around. + +NOTE: For `vasub`, overflow occurs only when subtracting the smallest number +from the largest number under `rnu` or `rne` rounding. + +---- +# Averaging add + +# Averaging adds of unsigned integers. +vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) +vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) + +# Averaging adds of signed integers. +vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) +vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) + +# Averaging subtract + +# Averaging subtract of unsigned integers. +vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1) +vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1) + +# Averaging subtract of signed integers. +vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1) +vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1) +---- + +==== Vector Single-Width Fractional Multiply with Rounding and Saturation + +The signed fractional multiply instruction produces a 2*SEW product of +the two SEW inputs, then shifts the result right by SEW-1 bits, +rounding these bits according to `vxrm`, then saturates the result to +fit into SEW bits. If the result causes saturation, the `vxsat` bit +is set. + +---- +# Signed saturating and rounding fractional multiply +# See vxrm description for rounding calculation +vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)) +vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1)) +---- + +NOTE: When multiplying two N-bit signed numbers, the largest magnitude +is obtained for -2^N-1^ * -2^N-1^ producing a result +2^2N-2^, which +has a single (zero) sign bit when held in 2N bits. All other products +have two sign bits in 2N bits. To retain greater precision in N +result bits, the product is shifted right by one bit less than N, +saturating the largest magnitude result but increasing result +precision by one bit for all other products. + +NOTE: We do not provide an equivalent fractional multiply where one +input is unsigned, as these would retain all upper SEW bits and would +not need to saturate. This operation is partly covered by the +`vmulhu` and `vmulhsu` instructions, for the case where rounding is +simply truncation (`rdn`). + +==== Vector Single-Width Scaling Shift Instructions + +These instructions shift the input value right, and round off the +shifted out bits according to `vxrm`. The scaling right shifts have +both zero-extending (`vssrl`) and sign-extending (`vssra`) forms. The +data to be shifted is in the vector register group specified by `vs2` +and the shift amount value can come from a vector register group +`vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit +immediate. Only the low lg2(SEW) bits of the shift-amount value are +used to control the shift amount. + +---- + # Scaling shift right logical + vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) + vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) + vssrl.vi vd, vs2, uimm, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) + + # Scaling shift right arithmetic + vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) + vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) + vssra.vi vd, vs2, uimm, vm # vd[i] = roundoff_signed(vs2[i], uimm) +---- + +==== Vector Narrowing Fixed-Point Clip Instructions + +The `vnclip` instructions are used to pack a fixed-point value into a +narrower destination. The instructions support rounding, scaling, and +saturation into the final destination format. The source data is in +the vector register group specified by `vs2`. The scaling shift amount +value can come from a vector register group `vs1`, a scalar integer +register `rs1`, or a zero-extended 5-bit immediate. The low +lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the +low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are +used to control the right shift amount, which provides the scaling. +---- +# Narrowing unsigned clip +# SEW 2*SEW SEW + vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) + vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) + vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm)) + +# Narrowing signed clip + vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) + vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) + vnclip.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm)) +---- + +For `vnclipu`/`vnclip`, the rounding mode is specified in the `vxrm` +CSR. Rounding occurs around the least-significant bit of the +destination and before saturation. + +For `vnclipu`, the shifted rounded source value is treated as an +unsigned integer and saturates if the result would overflow the +destination viewed as an unsigned integer. + +NOTE: There is no single instruction that can saturate a signed value +into an unsigned destination. A sequence of two vector instructions +that first removes negative numbers by performing a max against 0 +using `vmax` then clips the resulting unsigned value into the +destination using `vnclipu` can be used if setting `vxsat` value for +negative numbers is not required. A `vsetvli` is required inbetween +these two instructions to change SEW. + +For `vnclip`, the shifted rounded source value is treated as a signed +integer and saturates if the result would overflow the destination viewed +as a signed integer. + +If any destination element is saturated, the `vxsat` bit is set in the +`vxsat` register. + +[[sec-vector-float]] +=== Vector Floating-Point Instructions + +The standard vector floating-point instructions treat elements as +IEEE-754/2008-compatible values. If the EEW of a vector +floating-point operand does not correspond to a supported IEEE +floating-point type, the instruction encoding is reserved. + +NOTE: Whether floating-point is supported, and for which element +widths, is determined by the specific vector extension. The current +set of extensions include support for 32-bit and 64-bit floating-point +values. When 16-bit and 128-bit element widths are added, they will be +also be treated as IEEE-754/2008-compatible values. Other +floating-point formats may be supported in future extensions. + +Vector floating-point instructions require the presence of base scalar +floating-point extensions corresponding to the supported vector +floating-point element widths. + +NOTE: In particular, future vector extensions supporting 16-bit +half-precision floating-point values will also require some scalar +half-precision floating-point support. + +If the floating-point unit status field `mstatus.FS` is `Off` then any +attempt to execute a vector floating-point instruction will raise an +illegal instruction exception. Any vector floating-point instruction +that modifies any floating-point extension state (i.e., floating-point +CSRs or `f` registers) must set `mstatus.FS` to `Dirty`. + +If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is +additionally in effect for vector floating-point instructions. If +`vsstatus.FS` or `mstatus.FS` is `Off` then any +attempt to execute a vector floating-point instruction will raise an +illegal instruction exception. Any vector floating-point instruction +that modifies any floating-point extension state (i.e., floating-point +CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`. + +The vector floating-point instructions have the same behavior as the +scalar floating-point instructions with regard to NaNs. + +Scalar values for floating-point vector-scalar operations are sourced +as described in Section <<sec-arithmetic-encoding>>. + +==== Vector Floating-Point Exception Flags + +A vector floating-point exception at any active floating-point element +sets the standard FP exception flags in the `fflags` register. Inactive +elements do not set FP exception flags. + +==== Vector Single-Width Floating-Point Add/Subtract Instructions + +---- + # Floating-point add + vfadd.vv vd, vs2, vs1, vm # Vector-vector + vfadd.vf vd, vs2, rs1, vm # vector-scalar + + # Floating-point subtract + vfsub.vv vd, vs2, vs1, vm # Vector-vector + vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] + vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] +---- + +==== Vector Widening Floating-Point Add/Subtract Instructions + +---- +# Widening FP add/subtract, 2*SEW = SEW +/- SEW +vfwadd.vv vd, vs2, vs1, vm # vector-vector +vfwadd.vf vd, vs2, rs1, vm # vector-scalar +vfwsub.vv vd, vs2, vs1, vm # vector-vector +vfwsub.vf vd, vs2, rs1, vm # vector-scalar + +# Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW +vfwadd.wv vd, vs2, vs1, vm # vector-vector +vfwadd.wf vd, vs2, rs1, vm # vector-scalar +vfwsub.wv vd, vs2, vs1, vm # vector-vector +vfwsub.wf vd, vs2, rs1, vm # vector-scalar +---- + +==== Vector Single-Width Floating-Point Multiply/Divide Instructions + +---- + # Floating-point multiply + vfmul.vv vd, vs2, vs1, vm # Vector-vector + vfmul.vf vd, vs2, rs1, vm # vector-scalar + + # Floating-point divide + vfdiv.vv vd, vs2, vs1, vm # Vector-vector + vfdiv.vf vd, vs2, rs1, vm # vector-scalar + + # Reverse floating-point divide vector = scalar / vector + vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] +---- + +==== Vector Widening Floating-Point Multiply + +---- +# Widening floating-point multiply +vfwmul.vv vd, vs2, vs1, vm # vector-vector +vfwmul.vf vd, vs2, rs1, vm # vector-scalar +---- + +==== Vector Single-Width Floating-Point Fused Multiply-Add Instructions + +All four varieties of fused multiply-add are provided, and in two +destructive forms that overwrite one of the operands, either the +addend or the first multiplicand. + +---- +# FP multiply-accumulate, overwrites addend +vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] + +# FP negate-(multiply-accumulate), overwrites subtrahend +vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] +vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] + +# FP multiply-subtract-accumulator, overwrites subtrahend +vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] +vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] + +# FP negate-(multiply-subtract-accumulator), overwrites minuend +vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] +vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] + +# FP multiply-add, overwrites multiplicand +vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] +vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] + +# FP negate-(multiply-add), overwrites multiplicand +vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i] +vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i] + +# FP multiply-sub, overwrites multiplicand +vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i] +vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i] + +# FP negate-(multiply-sub), overwrites multiplicand +vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] +vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i] +---- + +NOTE: While we considered using the two unused rounding modes +in the scalar FP FMA encoding to provide a few non-destructive FMAs, +these would complicate microarchitectures by being the only maskable +operation with three inputs and separate output. + +==== Vector Widening Floating-Point Fused Multiply-Add Instructions + +The widening floating-point fused multiply-add instructions all +overwrite the wide addend with the result. The multiplier inputs are +all SEW wide, while the addend and destination is 2*SEW bits wide. + +---- +# FP widening multiply-accumulate, overwrites addend +vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] + +# FP widening negate-(multiply-accumulate), overwrites addend +vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] +vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] + +# FP widening multiply-subtract-accumulator, overwrites addend +vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] +vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] + +# FP widening negate-(multiply-subtract-accumulator), overwrites addend +vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] +vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] +---- + +==== Vector Floating-Point Square-Root Instruction + +This is a unary vector-vector instruction. + +---- + # Floating-point square root + vfsqrt.v vd, vs2, vm # Vector-vector square root +---- + +==== Vector Floating-Point Reciprocal Square-Root Estimate Instruction + +---- + # Floating-point reciprocal square-root estimate to 7 bits. + vfrsqrt7.v vd, vs2, vm +---- + +This is a unary vector-vector instruction that returns an estimate of +1/sqrt(x) accurate to 7 bits. + +NOTE: An earlier draft version had used the assembler name `vfrsqrte7` +but this was deemed to cause confusion with the ``e``__x__ notation for element +width. The earlier name can be retained as alias in tool chains for +backward compatibility. + +The following table describes the instruction's behavior for all +classes of floating-point inputs: + +[cols="1,1,1"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Input | Output | Exceptions raised + +| -{inf} {le} _x_ < -0.0 | canonical NaN | NV +| -0.0 | -{inf} | DZ +| +0.0 | +{inf} | DZ +| +0.0 < _x_ < +{inf} | _estimate of 1/sqrt(x)_ | +| +{inf} | +0.0 | +| qNaN | canonical NaN | +| sNaN | canonical NaN | NV +|=== + +NOTE: All positive normal and subnormal inputs produce normal outputs. + +NOTE: The output value is independent of the dynamic rounding mode. + +For the non-exceptional cases, the low bit of the exponent and the six high +bits of significand (after the leading one) are concatenated and used to +address the following table. +The output of the table becomes the seven high bits of the result significand +(after the leading one); the remainder of the result significand is zero. +Subnormal inputs are normalized and the exponent adjusted appropriately before +the lookup. +The output exponent is chosen to make the result approximate the reciprocal of +the square root of the argument. + +More precisely, the result is computed as follows. +Let the normalized input exponent be equal to the input exponent if the input +is normal, or 0 minus the number of leading zeros in the significand +otherwise. +If the input is subnormal, the normalized input significand is given by +shifting the input significand left by 1 minus the normalized input exponent, +discarding the leading 1 bit. +The output exponent equals floor((3*B - 1 - the normalized input exponent) / 2), +where B is the exponent bias. The output sign equals the input sign. + +The following table gives the seven MSBs of the output significand as a +function of the LSB of the normalized input exponent and the six MSBs of the +normalized input significand; the other bits of the output significand are zero. + +include::images/wavedrom/vfrsqrt7.adoc[] + +NOTE: For example, when SEW=32, vfrsqrt7(0x00718abc ({approx} 1.043e-38)) = 0x5f080000 ({approx} 9.800e18), and vfrsqrt7(0x7f765432 ({approx} 3.274e38)) = 0x1f820000 ({approx} 5.506e-20). + +NOTE: The 7 bit accuracy was chosen as it requires 0,1,2,3 +Newton-Raphson iterations to converge to close to bfloat16, FP16, +FP32, FP64 accuracy respectively. Future instructions can be defined +with greater estimate accuracy. + +==== Vector Floating-Point Reciprocal Estimate Instruction + +---- + # Floating-point reciprocal estimate to 7 bits. + vfrec7.v vd, vs2, vm +---- + +NOTE: An earlier draft version had used the assembler name `vfrece7` +but this was deemed to cause confusion with ``e``__x__ notation for element +width. The earlier name can be retained as alias in tool chains for +backward compatibility. + +This is a unary vector-vector instruction that returns an estimate of +1/x accurate to 7 bits. + +The following table describes the instruction's behavior for all +classes of floating-point inputs, where _B_ is the exponent bias: + +[cols="1,1,1,1"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Input (_x_) | Rounding Mode | Output (_y_ {approx} _1/x_) | Exceptions raised + +| -{inf} | _any_ | -0.0 | +| -2^B+1^ < _x_ {le} -2^B^ (normal) | _any_ | -2^-(B+1)^ {ge} _y_ > -2^-B^ (subnormal, sig=01...) | +| -2^B^ < _x_ {le} -2^B-1^ (normal) | _any_ | -2^-B^ {ge} _y_ > -2^-B+1^ (subnormal, sig=1...) | +| -2^B-1^ < _x_ {le} -2^-B+1^ (normal) | _any_ | -2^-B+1^ {ge} _y_ > -2^B-1^ (normal) | +| -2^-B+1^ < _x_ {le} -2^-B^ (subnormal, sig=1...) | _any_ | -2^B-1^ {ge} _y_ > -2^B^ (normal) | +| -2^-B^ < _x_ {le} -2^-(B+1)^ (subnormal, sig=01...) | _any_ | -2^B^ {ge} _y_ > -2^B+1^ (normal) | +| -2^-(B+1)^ < _x_ < -0.0 (subnormal, sig=00...) | RUP, RTZ | greatest-mag. negative finite value | NX, OF +| -2^-(B+1)^ < _x_ < -0.0 (subnormal, sig=00...) | RDN, RNE, RMM | -{inf} | NX, OF +| -0.0 | _any_ | -{inf} | DZ +| +0.0 | _any_ | +{inf} | DZ +| +0.0 < _x_ < 2^-(B+1)^ (subnormal, sig=00...) | RUP, RNE, RMM | +{inf} | NX, OF +| +0.0 < _x_ < 2^-(B+1)^ (subnormal, sig=00...) | RDN, RTZ | greatest finite value | NX, OF +| 2^-(B+1)^ {le} _x_ < 2^-B^ (subnormal, sig=01...) | _any_ | 2^B+1^ > _y_ {ge} 2^B^ (normal) | +| 2^-B^ {le} _x_ < 2^-B+1^ (subnormal, sig=1...) | _any_ | 2^B^ > _y_ {ge} 2^B-1^ (normal) | +| 2^-B+1^ {le} _x_ < 2^B-1^ (normal) | _any_ | 2^B-1^ > _y_ {ge} 2^-B+1^ (normal) | +| 2^B-1^ {le} _x_ < 2^B^ (normal) | _any_ | 2^-B+1^ > _y_ {ge} 2^-B^ (subnormal, sig=1...) | +| 2^B^ {le} _x_ < 2^B+1^ (normal) | _any_ | 2^-B^ > _y_ {ge} 2^-(B+1)^ (subnormal, sig=01...) | +| +{inf} | _any_ | +0.0 | +| qNaN | _any_ | canonical NaN | +| sNaN | _any_ | canonical NaN | NV +|=== + +NOTE: Subnormal inputs with magnitude at least 2^-(B+1)^ produce normal outputs; +other subnormal inputs produce infinite outputs. +Normal inputs with magnitude at least 2^B-1^ produce subnormal outputs; +other normal inputs produce normal outputs. + +NOTE: The output value depends on the dynamic rounding mode when +the overflow exception is raised. + +For the non-exceptional cases, the seven high bits of significand (after the +leading one) are used to address the following table. +The output of the table becomes the seven high bits of the result significand +(after the leading one); the remainder of the result significand is zero. +Subnormal inputs are normalized and the exponent adjusted appropriately before +the lookup. +The output exponent is chosen to make the result approximate the reciprocal of +the argument, and subnormal outputs are denormalized accordingly. + +More precisely, the result is computed as follows. +Let the normalized input exponent be equal to the input exponent if the input +is normal, or 0 minus the number of leading zeros in the significand +otherwise. +The normalized output exponent equals (2*B - 1 - the normalized input exponent). +If the normalized output exponent is outside the range [-1, 2*B], the result +corresponds to one of the exceptional cases in the table above. + +If the input is subnormal, the normalized input significand is given by +shifting the input significand left by 1 minus the normalized input exponent, +discarding the leading 1 bit. +Otherwise, the normalized input significand equals the input significand. +The following table gives the seven MSBs of the normalized output significand +as a function of the seven MSBs of the normalized input significand; the other +bits of the normalized output significand are zero. + +include::images/wavedrom/vfrec7.adoc[] + +If the normalized output exponent is 0 or -1, the result is subnormal: the +output exponent is 0, and the output significand is given by concatenating +a 1 bit to the left of the normalized output significand, then shifting that +quantity right by 1 minus the normalized output exponent. +Otherwise, the output exponent equals the normalized output exponent, and the +output significand equals the normalized output significand. +The output sign equals the input sign. + +NOTE: For example, when SEW=32, vfrec7(0x00718abc ({approx} 1.043e-38)) = 0x7e900000 ({approx} 9.570e37), and vfrec7(0x7f765432 ({approx} 3.274e38)) = 0x00214000 ({approx} 3.053e-39). + +NOTE: The 7 bit accuracy was chosen as it requires 0,1,2,3 +Newton-Raphson iterations to converge to close to bfloat16, FP16, +FP32, FP64 accuracy respectively. Future instructions can be defined +with greater estimate accuracy. + +==== Vector Floating-Point MIN/MAX Instructions + +The vector floating-point `vfmin` and `vfmax` instructions have the +same behavior as the corresponding scalar floating-point instructions +in version 2.2 of the RISC-V F/D/Q extension: they perform the `minimumNumber` +or `maximumNumber` operation on active elements. + +---- + # Floating-point minimum + vfmin.vv vd, vs2, vs1, vm # Vector-vector + vfmin.vf vd, vs2, rs1, vm # vector-scalar + + # Floating-point maximum + vfmax.vv vd, vs2, vs1, vm # Vector-vector + vfmax.vf vd, vs2, rs1, vm # vector-scalar +---- + +==== Vector Floating-Point Sign-Injection Instructions + +Vector versions of the scalar sign-injection instructions. The result +takes all bits except the sign bit from the vector `vs2` operands. + +---- + vfsgnj.vv vd, vs2, vs1, vm # Vector-vector + vfsgnj.vf vd, vs2, rs1, vm # vector-scalar + + vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector + vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar + + vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector + vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar +---- + +NOTE: A vector of floating-point values can be negated using a +sign-injection instruction with both source operands set to the same +vector operand. An assembly pseudoinstruction is provided: `vfneg.v vd,vs` = `vfsgnjn.vv vd,vs,vs`. + +NOTE: The absolute value of a vector of floating-point elements can be +calculated using a sign-injection instruction with both source +operands set to the same vector operand. An assembly +pseudoinstruction is provided: `vfabs.v vd,vs` = `vfsgnjx.vv vd,vs,vs`. + +==== Vector Floating-Point Compare Instructions + +These vector FP compare instructions compare two source operands and +write the comparison result to a mask register. The destination mask +vector is always held in a single vector register, with a layout of +elements as described in Section <<sec-mask-register-layout>>. The +destination mask vector register may be the same as the source vector +mask register (`v0`). Compares write mask registers, and so always +operate under a tail-agnostic policy. + +The compare instructions follow the semantics of the scalar +floating-point compare instructions. `vmfeq` and `vmfne` raise the invalid +operation exception only on signaling NaN inputs. `vmflt`, `vmfle`, `vmfgt`, +and `vmfge` raise the invalid operation exception on both signaling and +quiet NaN inputs. +`vmfne` writes 1 to the destination element when either +operand is NaN, whereas the other compares write 0 when either operand +is NaN. + +---- + # Compare equal + vmfeq.vv vd, vs2, vs1, vm # Vector-vector + vmfeq.vf vd, vs2, rs1, vm # vector-scalar + + # Compare not equal + vmfne.vv vd, vs2, vs1, vm # Vector-vector + vmfne.vf vd, vs2, rs1, vm # vector-scalar + + # Compare less than + vmflt.vv vd, vs2, vs1, vm # Vector-vector + vmflt.vf vd, vs2, rs1, vm # vector-scalar + + # Compare less than or equal + vmfle.vv vd, vs2, vs1, vm # Vector-vector + vmfle.vf vd, vs2, rs1, vm # vector-scalar + + # Compare greater than + vmfgt.vf vd, vs2, rs1, vm # vector-scalar + + # Compare greater than or equal + vmfge.vf vd, vs2, rs1, vm # vector-scalar +---- + +---- +Comparison Assembler Mapping Assembler pseudoinstruction + +va < vb vmflt.vv vd, va, vb, vm +va <= vb vmfle.vv vd, va, vb, vm +va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, vb, vm +va >= vb vmfle.vv vd, vb, va, vm vmfge.vv vd, va, vb, vm + +va < f vmflt.vf vd, va, f, vm +va <= f vmfle.vf vd, va, f, vm +va > f vmfgt.vf vd, va, f, vm +va >= f vmfge.vf vd, va, f, vm + +va, vb vector register groups +f scalar floating-point register +---- + +NOTE: Providing all forms is necessary to correctly handle unordered +compares for NaNs. + +NOTE: C99 floating-point quiet compares can be implemented by masking +the signaling compares when either input is NaN, as follows. When +the comparand is a non-NaN constant, the middle two instructions can be +omitted. + +---- + # Example of implementing isgreater() + vmfeq.vv v0, va, va # Only set where A is not NaN. + vmfeq.vv v1, vb, vb # Only set where B is not NaN. + vmand.mm v0, v0, v1 # Only set where A and B are ordered, + vmfgt.vv v0, va, vb, v0.t # so only set flags on ordered values. +---- + +NOTE: In the above sequence, it is tempting to mask the second `vmfeq` +instruction and remove the `vmand` instruction, but this more efficient +sequence incorrectly fails to raise the invalid exception when an +element of `va` contains a quiet NaN and the corresponding element in +`vb` contains a signaling NaN. + +==== Vector Floating-Point Classify Instruction + +This is a unary vector-vector instruction that operates in the same +way as the scalar classify instruction. + +---- + vfclass.v vd, vs2, vm # Vector-vector +---- + +The 10-bit mask produced by this instruction is placed in the +least-significant bits of the result elements. The upper (SEW-10) +bits of the result are filled with zeros. The instruction is only +defined for SEW=16b and above, so the result will always fit in the +destination elements. + +==== Vector Floating-Point Merge Instruction + +A vector-scalar floating-point merge instruction is provided, which +operates on all body elements from `vstart` up to the current vector +length in `vl` regardless of mask value. + +The `vfmerge.vfm` instruction is encoded as a masked instruction (`vm=0`). +At elements where the mask value is zero, the first vector operand is +copied to the destination element, otherwise a scalar floating-point +register value is copied to the destination element. + +---- +vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i] +---- + +[[sec-vector-float-move]] +==== Vector Floating-Point Move Instruction + +The vector floating-point move instruction __splats__ a floating-point +scalar operand to a vector register group. The instruction copies a +scalar `f` register value to all active elements of a vector register +group. This instruction is encoded as an unmasked instruction (`vm=1`). +The instruction must have the `vs2` field set to `v0`, with all other +values for `vs2` reserved. + +---- +vfmv.v.f vd, rs1 # vd[i] = f[rs1] +---- + +NOTE: The `vfmv.v.f` instruction shares the encoding with the `vfmerge.vfm` +instruction, but with `vm=1` and `vs2=v0`. + +==== Single-Width Floating-Point/Integer Type-Convert Instructions + +Conversion operations are provided to convert to and from +floating-point values and unsigned and signed integers, where both +source and destination are SEW wide. + +---- +vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. +vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. + +vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. +vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. + +vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. +vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float. +---- + +The conversions follow the same rules on exceptional conditions as the +scalar conversion instructions. +The conversions use the dynamic rounding mode in `frm`, except for the `rtz` +variants, which round towards zero. + +NOTE: The `rtz` variants are provided to accelerate truncating conversions +from floating-point to integer, as is common in languages like C and Java. + +==== Widening Floating-Point/Integer Type-Convert Instructions + +A set of conversion instructions is provided to convert between +narrower integer and floating-point datatypes to a type of twice the +width. + +---- +vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. +vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. + +vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. +vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. + +vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. +vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. + +vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float. +---- + +These instructions have the same constraints on vector register overlap +as other widening instructions (see <<sec-widening>>). + +NOTE: A double-width IEEE floating-point value can always represent a +single-width integer exactly. + +NOTE: A double-width IEEE floating-point value can always represent a +single-width IEEE floating-point value exactly. + +NOTE: A full set of floating-point widening conversions is not +supported as single instructions, but any widening conversion can be +implemented as several doubling steps with equivalent results and no +additional exception flags raised. + +==== Narrowing Floating-Point/Integer Type-Convert Instructions + +A set of conversion instructions is provided to convert wider integer +and floating-point datatypes to a type of half the width. + +---- +vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. +vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. + +vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. +vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. + +vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. +vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. + +vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. +vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, + # rounding towards odd. +---- + +These instructions have the same constraints on vector register overlap +as other narrowing instructions (see <<sec-narrowing>>). + +NOTE: A full set of floating-point narrowing conversions is not +supported as single instructions. Conversions can be implemented in +a sequence of halving steps. Results are equivalently rounded and +the same exception flags are raised if all but the last halving step +use round-towards-odd (`vfncvt.rod.f.f.w`). Only the final step +should use the desired rounding mode. + +NOTE: For `vfncvt.rod.f.f.w`, a finite value that exceeds the range of the +destination format is converted to the destination format's largest finite value with the same sign. + +=== Vector Reduction Operations + +Vector reduction operations take a vector register group of elements +and a scalar held in element 0 of a vector register, and perform a +reduction using some binary operator, to produce a scalar result in +element 0 of a vector register. The scalar input and output operands +are held in element 0 of a single vector register, not a vector +register group, so any vector register can be the scalar source or +destination of a vector reduction regardless of LMUL setting. + +The destination vector register can overlap the source operands, +including the mask register. + +NOTE: Vector reductions read and write the scalar operand and result +into element 0 of a vector register instead of a scalar register to +avoid a loss of decoupling with the scalar processor, and to support +future polymorphic use with future types not supported in the scalar +unit. + +Inactive elements from the source vector register group are excluded +from the reduction, but the scalar operand is always included +regardless of the mask values. + +The other elements in the destination vector register ( 0 < index < +VLEN/SEW) are considered the tail and are managed with the current +tail agnostic/undisturbed policy. + +If `vl`=0, no operation is performed and the destination register is +not updated. + +NOTE: This choice of behavior for `vl`=0 reduces implementation +complexity as it is consistent with other operations on vector +register state. For the common case that the source and destination +scalar operand are the same vector register, this behavior also +produces the expected result. For the uncommon case that the source +and destination scalar operand are in different vector registers, this +instruction will not copy the source into the destination when `vl`=0. +However, it is expected that in most of these cases it will be +statically known that `vl` is not zero. In other cases, a check for +`vl`=0 will have to be added to ensure that the source scalar is +copied to the destination (e.g., by explicitly setting `vl`=1 and +performing a register-register copy). + +Traps on vector reduction instructions are always reported with a +`vstart` of 0. Vector reduction operations raise an illegal +instruction exception if `vstart` is non-zero. + +The assembler syntax for a reduction operation is `vredop.vs`, where +the `.vs` suffix denotes the first operand is a vector register group +and the second operand is a scalar stored in element 0 of a vector +register. + +[[sec-vector-integer-reduce]] +==== Vector Single-Width Integer Reduction Instructions + +All operands and results of single-width reduction instructions have +the same SEW width. Overflows wrap around on arithmetic sums. + +---- + # Simple reductions, where [*] denotes all active elements: + vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) + vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) + vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) + vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) + vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) + vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) + vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) + vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] ) +---- + +[[sec-vector-integer-reduce-widen]] +==== Vector Widening Integer Reduction Instructions + +The unsigned `vwredsumu.vs` instruction zero-extends the SEW-wide +vector elements before summing them, then adds the 2*SEW-width scalar +element, and stores the result in a 2*SEW-width scalar element. + +The `vwredsum.vs` instruction sign-extends the SEW-wide vector +elements before summing them. + +For both `vwredsumu.vs` and `vwredsum.vs`, overflows wrap around. + +---- + # Unsigned sum reduction into double-width accumulator + vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) + + # Signed sum reduction into double-width accumulator + vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW)) +---- + +[[sec-vector-float-reduce]] +==== Vector Single-Width Floating-Point Reduction Instructions + +---- + # Simple reductions. + vfredosum.vs vd, vs2, vs1, vm # Ordered sum + vfredusum.vs vd, vs2, vs1, vm # Unordered sum + vfredmax.vs vd, vs2, vs1, vm # Maximum value + vfredmin.vs vd, vs2, vs1, vm # Minimum value + +---- + +NOTE: Older assembler mnemonic `vfredsum` is retained as alias for `vfredusum`. + +===== Vector Ordered Single-Width Floating-Point Sum Reduction + +The `vfredosum` instruction must sum the floating-point values in +element order, starting with the scalar in `vs1[0]`--that is, it +performs the computation: + +---- + vd[0] = `(((vs1[0] + vs2[0]) + vs2[1]) + ...) + vs2[vl-1]` +---- +where each addition operates identically to the scalar floating-point +instructions in terms of raising exception flags and generating or +propagating special values. + +NOTE: The ordered reduction supports compiler autovectorization, while +the unordered FP sum allows for faster implementations. + +When the operation is masked (`vm=0`), the masked-off elements do not +affect the result or the exception flags. + +NOTE: If no elements are active, no additions are performed, so the scalar in +`vs1[0]` is simply copied to the destination register, without canonicalizing +NaN values and without setting any exception flags. This behavior preserves +the handling of NaNs, exceptions, and rounding when autovectorizing a scalar +summation loop. + +===== Vector Unordered Single-Width Floating-Point Sum Reduction + +The unordered sum reduction instruction, `vfredusum`, provides an +implementation more freedom in performing the reduction. + +The implementation must produce a result equivalent to a reduction tree +composed of binary operator nodes, with the inputs being elements from +the source vector register group (`vs2`) and the source scalar value +(`vs1[0]`). Each operator in the tree accepts two inputs and produces +one result. +Each operator first computes an exact sum as a RISC-V scalar floating-point +addition with infinite exponent range and precision, then converts this exact +sum to a floating-point format with range and precision each at least as great +as the element floating-point format indicated by SEW, rounding using the +currently active floating-point dynamic rounding mode and raising exception +flags as necessary. +A different floating-point range and precision may be chosen for the result of +each operator. +A node where one input is derived only from elements masked-off or beyond the +active vector length may either treat that input as the additive identity of the +appropriate EEW or simply copy the other input to its output. +The rounded result from the root node in the tree is converted (rounded again, +using the dynamic rounding mode) to the standard floating-point format +indicated by SEW. +An implementation +is allowed to add an additional additive identity to the final result. + +The additive identity is +0.0 when rounding down (towards -{inf}) or +-0.0 for all other rounding modes. + +The reduction tree structure must be deterministic for a given value +in `vtype` and `vl`. + +NOTE: As a consequence of this definition, implementations need not propagate +NaN payloads through the reduction tree when no elements are active. In +particular, if no elements are active and the scalar input is NaN, +implementations are permitted to canonicalize the NaN and, if the NaN is +signaling, set the invalid exception flag. Implementations are alternatively +permitted to pass through the original NaN and set no exception flags, as with +`vfredosum`. + +NOTE: The `vfredosum` instruction is a valid implementation of the +`vfredusum` instruction. + +===== Vector Single-Width Floating-Point Max and Min Reductions + +The `vfredmin` and `vfredmax` instructions reduce the scalar argument in +`vs1[0]` and active elements in `vs2` using the `minimumNumber` and +`maximumNumber` operations, respectively. + +NOTE: Floating-point max and min reductions should return the same +final value and raise the same exception flags regardless of operation +order. + +NOTE: If no elements are active, the scalar in `vs1[0]` is simply copied to +the destination register, without canonicalizing NaN values and without +setting any exception flags. + +[[sec-vector-float-reduce-widen]] +==== Vector Widening Floating-Point Reduction Instructions + +Widening forms of the sum reductions are provided that +read and write a double-width reduction result. + +---- + # Simple reductions. + vfwredosum.vs vd, vs2, vs1, vm # Ordered sum + vfwredusum.vs vd, vs2, vs1, vm # Unordered sum +---- + +NOTE: Older assembler mnemonic `vfwredsum` is retained as alias for `vfwredusum`. + +The reduction of the SEW-width elements is performed as in the +single-width reduction case, with the elements in `vs2` promoted +to 2*SEW bits before adding to the 2*SEW-bit accumulator. + +NOTE: `vfwredosum.vs` handles inactive elements and NaN payloads analogously +to `vfredosum.vs`; `vfwredusum.vs` does so analogously to `vfredusum.vs`. + +[[sec-vector-mask]] +=== Vector Mask Instructions + +Several instructions are provided to help operate on mask values held in +a vector register. + +[[sec-mask-register-logical]] +==== Vector Mask-Register Logical Instructions + +Vector mask-register logical operations operate on mask registers. +Each element in a mask register is a single bit, so these instructions +all operate on single vector registers regardless of the setting of +the `vlmul` field in `vtype`. They do not change the value of +`vlmul`. The destination vector register may be the same as either +source vector register. + +As with other vector instructions, the elements with indices less than +`vstart` are unchanged, and `vstart` is reset to zero after execution. +Vector mask logical instructions are always unmasked, so there are no +inactive elements, and the encodings with `vm=0` are reserved. +Mask elements past `vl`, the tail elements, are +always updated with a tail-agnostic policy. + +---- + vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] + vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) + vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] + vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] + vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] + vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) + vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] + vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) +---- + +NOTE: The previous assembler mnemonics `vmandnot` and `vmornot` have +been changed to `vmandn` and `vmorn` to be consistent with the +equivalent scalar instructions. The old `vmandnot` and `vmornot` +mnemonics can be retained as assembler aliases for compatibility. + +Several assembler pseudoinstructions are defined as shorthand for +common uses of mask logical operations: +---- + vmmv.m vd, vs => vmand.mm vd, vs, vs # Copy mask register + vmclr.m vd => vmxor.mm vd, vd, vd # Clear mask register + vmset.m vd => vmxnor.mm vd, vd, vd # Set mask register + vmnot.m vd, vs => vmnand.mm vd, vs, vs # Invert bits +---- + +NOTE: The `vmmv.m` instruction was previously called `vmcpy.m`, but +with new layout it is more consistent to name as a "mv" because bits +are copied without interpretation. The `vmcpy.m` assembler +pseudoinstruction can be retained for compatibility. For +implementations that internally rearrange bits according to EEW, a +`vmmv.m` instruction with same source and destination can be used as +idiom to force an internal reformat into a mask vector. + +The set of eight mask logical instructions can generate any of the 16 +possibly binary logical functions of the two input masks: + +[cols="1,1,1,1,12"] +|=== +4+| inputs | + +| 0 | 0 | 1 | 1 | src1 +| 0 | 1 | 0 | 1 | src2 +|=== + +[cols="1,1,1,1,6,6"] +|=== +4+| output | instruction | pseudoinstruction + +| 0 | 0 | 0 | 0 | vmxor.mm vd, vd, vd | vmclr.m vd +| 1 | 0 | 0 | 0 | vmnor.mm vd, src1, src2 | +| 0 | 1 | 0 | 0 | vmandn.mm vd, src2, src1 | +| 1 | 1 | 0 | 0 | vmnand.mm vd, src1, src1 | vmnot.m vd, src1 +| 0 | 0 | 1 | 0 | vmandn.mm vd, src1, src2 | +| 1 | 0 | 1 | 0 | vmnand.mm vd, src2, src2 | vmnot.m vd, src2 +| 0 | 1 | 1 | 0 | vmxor.mm vd, src1, src2 | +| 1 | 1 | 1 | 0 | vmnand.mm vd, src1, src2 | +| 0 | 0 | 0 | 1 | vmand.mm vd, src1, src2 | +| 1 | 0 | 0 | 1 | vmxnor.mm vd, src1, src2 | +| 0 | 1 | 0 | 1 | vmand.mm vd, src2, src2 | vmmv.m vd, src2 +| 1 | 1 | 0 | 1 | vmorn.mm vd, src2, src1 | +| 0 | 0 | 1 | 1 | vmand.mm vd, src1, src1 | vmmv.m vd, src1 +| 1 | 0 | 1 | 1 | vmorn.mm vd, src1, src2 | +| 0 | 1 | 1 | 1 | vmor.mm vd, src1, src2 | +| 1 | 1 | 1 | 1 | vmxnor.mm vd, vd, vd | vmset.m vd +|=== + +NOTE: The vector mask logical instructions are designed to be easily +fused with a following masked vector operation to effectively expand +the number of predicate registers by moving values into `v0` before +use. + + +==== Vector count population in mask `vcpop.m` + +---- + vcpop.m rd, vs2, vm +---- + +NOTE: This instruction previously had the assembler mnemonic `vpopc.m` +but was renamed to be consistent with the scalar instruction. The +assembler instruction alias `vpopc.m` is being retained for software +compatibility. + +The source operand is a single vector register holding mask register +values as described in Section <<sec-mask-register-layout>>. + +The `vcpop.m` instruction counts the number of mask elements of the +active elements of the vector source mask register that have the value +1 and writes the result to a scalar `x` register. + +The operation can be performed under a mask, in which case only the +masked elements are counted. + +---- + vcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] ) +---- + +The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the +value 0, since no mask elements are active). + +Traps on `vcpop.m` are always reported with a `vstart` of 0. The +`vcpop.m` instruction will raise an illegal instruction exception if +`vstart` is non-zero. + +==== `vfirst` find-first-set mask bit + +---- + vfirst.m rd, vs2, vm +---- + +The `vfirst` instruction finds the lowest-numbered active element of +the source mask vector that has the value 1 and writes that element's +index to a GPR. If no active element has the value 1, -1 is written +to the GPR. + +NOTE: Software can assume that any negative value (highest bit set) +corresponds to no element found, as vector lengths will never reach +2^(XLEN-1)^ on any implementation. + +The `vfirst.m` instruction writes `x[rd]` even if `vl`=0 (with the +value -1, since no mask elements are active). + +Traps on `vfirst` are always reported with a `vstart` of 0. The +`vfirst` instruction will raise an illegal instruction exception if +`vstart` is non-zero. + +==== `vmsbf.m` set-before-first mask bit + +---- + vmsbf.m vd, vs2, vm + + # Example + + 7 6 5 4 3 2 1 0 Element number + + 1 0 0 1 0 1 0 0 v3 contents + vmsbf.m v2, v3 + 0 0 0 0 0 0 1 1 v2 contents + + 1 0 0 1 0 1 0 1 v3 contents + vmsbf.m v2, v3 + 0 0 0 0 0 0 0 0 v2 + + 0 0 0 0 0 0 0 0 v3 contents + vmsbf.m v2, v3 + 1 1 1 1 1 1 1 1 v2 + + 1 1 0 0 0 0 1 1 v0 vcontents + 1 0 0 1 0 1 0 0 v3 contents + vmsbf.m v2, v3, v0.t + 0 1 x x x x 1 1 v2 contents +---- + +The `vmsbf.m` instruction takes a mask register as input and writes +results to a mask register. The instruction writes a 1 to all active +mask elements before the first active source element that is a 1, then +writes a 0 to that element and all following active elements. If +there is no set bit in the active elements of the source vector, then +all active elements in the destination are written with a 1. + +The tail elements in the destination mask register are updated under a +tail-agnostic policy. + +Traps on `vmsbf.m` are always reported with a `vstart` of 0. The +`vmsbf` instruction will raise an illegal instruction exception if +`vstart` is non-zero. + +The destination register cannot overlap the source register +and, if masked, cannot overlap the mask register ('v0'). + +==== `vmsif.m` set-including-first mask bit + +The vector mask set-including-first instruction is similar to +set-before-first, except it also includes the element with a set bit. + +---- + vmsif.m vd, vs2, vm + + # Example + + 7 6 5 4 3 2 1 0 Element number + + 1 0 0 1 0 1 0 0 v3 contents + vmsif.m v2, v3 + 0 0 0 0 0 1 1 1 v2 contents + + 1 0 0 1 0 1 0 1 v3 contents + vmsif.m v2, v3 + 0 0 0 0 0 0 0 1 v2 + + 1 1 0 0 0 0 1 1 v0 vcontents + 1 0 0 1 0 1 0 0 v3 contents + vmsif.m v2, v3, v0.t + 1 1 x x x x 1 1 v2 contents +---- + +The tail elements in the destination mask register are updated under a +tail-agnostic policy. + +Traps on `vmsif.m` are always reported with a `vstart` of 0. The +`vmsif` instruction will raise an illegal instruction exception if +`vstart` is non-zero. + +The destination register cannot overlap the source register +and, if masked, cannot overlap the mask register ('v0'). + +==== `vmsof.m` set-only-first mask bit + +The vector mask set-only-first instruction is similar to +set-before-first, except it only sets the first element with a bit +set, if any. + +---- + vmsof.m vd, vs2, vm + + # Example + + 7 6 5 4 3 2 1 0 Element number + + 1 0 0 1 0 1 0 0 v3 contents + vmsof.m v2, v3 + 0 0 0 0 0 1 0 0 v2 contents + + 1 0 0 1 0 1 0 1 v3 contents + vmsof.m v2, v3 + 0 0 0 0 0 0 0 1 v2 + + 1 1 0 0 0 0 1 1 v0 vcontents + 1 1 0 1 0 1 0 0 v3 contents + vmsof.m v2, v3, v0.t + 0 1 x x x x 0 0 v2 contents +---- + +The tail elements in the destination mask register are updated under a +tail-agnostic policy. + +Traps on `vmsof.m` are always reported with a `vstart` of 0. The +`vmsof` instruction will raise an illegal instruction exception if +`vstart` is non-zero. + +The destination register cannot overlap the source register +and, if masked, cannot overlap the mask register ('v0'). + +==== Example using vector mask instructions + +The following is an example of vectorizing a data-dependent exit loop. + +---- +include::example/strcpy.s[lines=4..-1] +---- +---- +include::example/strncpy.s[lines=4..-1] +---- + +==== Vector Iota Instruction + +The `viota.m` instruction reads a source vector mask register and +writes to each element of the destination vector register group the +sum of all the bits of elements in the mask register +whose index is less than the element, e.g., a parallel prefix sum of +the mask values. + +This instruction can be masked, in which case only the enabled +elements contribute to the sum. + +---- + viota.m vd, vs2, vm + + # Example + + 7 6 5 4 3 2 1 0 Element number + + 1 0 0 1 0 0 0 1 v2 contents + viota.m v4, v2 # Unmasked + 2 2 2 1 1 1 1 0 v4 result + + 1 1 1 0 1 0 1 1 v0 contents + 1 0 0 1 0 0 0 1 v2 contents + 2 3 4 5 6 7 8 9 v4 contents + viota.m v4, v2, v0.t # Masked, vtype.vma=0 + 1 1 1 5 1 7 1 0 v4 results +---- + +The result value is zero-extended to fill the destination element if +SEW is wider than the result. If the result value would overflow the +destination SEW, the least-significant SEW bits are retained. + +Traps on `viota.m` are always reported with a `vstart` of 0, and +execution is always restarted from the beginning when resuming after a +trap handler. An illegal instruction exception is raised if `vstart` +is non-zero. + +The destination register group cannot overlap the source register +and, if masked, cannot overlap the mask register (`v0`). + +The `viota.m` instruction can be combined with memory scatter +instructions (indexed stores) to perform vector compress functions. + +---- + # Compact non-zero elements from input memory array to output memory array + # + # size_t compact_non_zero(size_t n, const int* in, int* out) + # { + # size_t i; + # size_t count = 0; + # int *p = out; + # + # for (i=0; i<n; i++) + # { + # const int v = *in++; + # if (v != 0) + # *p++ = v; + # } + # + # return (size_t) (p - out); + # } + # + # a0 = n + # a1 = &in + # a2 = &out + +compact_non_zero: + li a6, 0 # Clear count of non-zero elements +loop: + vsetvli a5, a0, e32, m8, ta, ma # 32-bit integers + vle32.v v8, (a1) # Load input vector + sub a0, a0, a5 # Decrement number done + slli a5, a5, 2 # Multiply by four bytes + vmsne.vi v0, v8, 0 # Locate non-zero values + add a1, a1, a5 # Bump input pointer + vcpop.m a5, v0 # Count number of elements set in v0 + viota.m v16, v0 # Get destination offsets of active elements + add a6, a6, a5 # Accumulate number of elements + vsll.vi v16, v16, 2, v0.t # Multiply offsets by four bytes + slli a5, a5, 2 # Multiply number of non-zero elements by four bytes + vsuxei32.v v8, (a2), v16, v0.t # Scatter using scaled viota results under mask + add a2, a2, a5 # Bump output pointer + bnez a0, loop # Any more? + + mv a0, a6 # Return count + ret +---- + +==== Vector Element Index Instruction + +The `vid.v` instruction writes each element's index to the +destination vector register group, from 0 to `vl`-1. + +---- + vid.v vd, vm # Write element ID to destination. +---- + +The instruction can be masked. Masking does not change the +index value written to active elements. + +The `vs2` field of the instruction must be set to `v0`, otherwise the +encoding is _reserved_. + +The result value is zero-extended to fill the destination element if +SEW is wider than the result. If the result value would overflow the +destination SEW, the least-significant SEW bits are retained. + +NOTE: Microarchitectures can implement `vid.v` instruction using the +same datapath as `viota.m` but with an implicit set mask source. + +[[sec-vector-permute]] +=== Vector Permutation Instructions + +A range of permutation instructions are provided to move elements +around within the vector registers. + +==== Integer Scalar Move Instructions + +The integer scalar read/write instructions transfer a single +value between a scalar `x` register and element 0 of a vector +register. The instructions ignore LMUL and vector register groups. + +---- +vmv.x.s rd, vs2 # x[rd] = vs2[0] (vs1=0) +vmv.s.x vd, rs1 # vd[0] = x[rs1] (vs2=0) +---- + +The `vmv.x.s` instruction copies a single SEW-wide element from index 0 of the +source vector register to a destination integer register. If SEW > XLEN, the +least-significant XLEN bits are transferred and the upper SEW-XLEN bits are +ignored. If SEW < XLEN, the value is sign-extended to XLEN bits. + +NOTE: `vmv.x.s` performs its operation even if `vstart` {ge} `vl` or `vl`=0. + +The `vmv.s.x` instruction copies the scalar integer register to element 0 of +the destination vector register. If SEW < XLEN, the least-significant bits +are copied and the upper XLEN-SEW bits are ignored. If SEW > XLEN, the value +is sign-extended to SEW bits. The other elements in the destination vector +register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy. If `vstart` {ge} `vl`, no +operation is performed and the destination register is not updated. + +NOTE: As a consequence, when `vl`=0, no elements are updated in the +destination vector register group, regardless of `vstart`. + +The encodings corresponding to the masked versions (`vm=0`) of `vmv.x.s` +and `vmv.s.x` are reserved. + +==== Floating-Point Scalar Move Instructions + +The floating-point scalar read/write instructions transfer a single +value between a scalar `f` register and element 0 of a vector +register. The instructions ignore LMUL and vector register groups. + +---- +vfmv.f.s rd, vs2 # f[rd] = vs2[0] (rs1=0) +vfmv.s.f vd, rs1 # vd[0] = f[rs1] (vs2=0) +---- + +The `vfmv.f.s` instruction copies a single SEW-wide element from index +0 of the source vector register to a destination scalar floating-point +register. + +NOTE: `vfmv.f.s` performs its operation even if `vstart` {ge} `vl` or `vl`=0. + +The `vfmv.s.f` instruction copies the scalar floating-point register +to element 0 of the destination vector register. The other elements +in the destination vector register ( 0 < index < VLEN/SEW) are treated +as tail elements using the current tail agnostic/undisturbed policy. +If `vstart` {ge} `vl`, no operation is performed and the destination +register is not updated. + +NOTE: As a consequence, when `vl`=0, no elements are updated in the +destination vector register group, regardless of `vstart`. + +The encodings corresponding to the masked versions (`vm=0`) of `vfmv.f.s` +and `vfmv.s.f` are reserved. + +==== Vector Slide Instructions + +The slide instructions move elements up and down a vector register +group. + +NOTE: The slide operations can be implemented much more efficiently +than using the arbitrary register gather instruction. Implementations +may optimize certain OFFSET values for `vslideup` and `vslidedown`. +In particular, power-of-2 offsets may operate substantially faster +than other offsets. + +For all of the `vslideup`, `vslidedown`, `v[f]slide1up`, and +`v[f]slide1down` instructions, if `vstart` {ge} `vl`, the instruction performs no +operation and leaves the destination vector register unchanged. + +NOTE: As a consequence, when `vl`=0, no elements are updated in the +destination vector register group, regardless of `vstart`. + +The tail agnostic/undisturbed policy is followed for tail elements. + +The slide instructions may be masked, with mask element _i_ +controlling whether _destination_ element _i_ is written. The mask +undisturbed/agnostic policy is followed for inactive elements. + +===== Vector Slideup Instructions + +---- + vslideup.vx vd, vs2, rs1, vm # vd[i+x[rs1]] = vs2[i] + vslideup.vi vd, vs2, uimm, vm # vd[i+uimm] = vs2[i] +---- + +For `vslideup`, the value in `vl` specifies the maximum number of destination +elements that are written. The start index (_OFFSET_) for the +destination can be either specified using an unsigned integer in the +`x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits. +If XLEN > SEW, _OFFSET_ is _not_ truncated to SEW bits. +Destination elements _OFFSET_ through `vl`-1 are written if unmasked and +if _OFFSET_ < `vl`. + +---- + vslideup behavior for destination elements (`vstart` < `vl`) + + OFFSET is amount to slideup, either from x register or a 5-bit immediate + + 0 <= i < min(vl, max(vstart, OFFSET)) Unchanged + max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy +---- + +The destination vector register group for `vslideup` cannot overlap +the source vector register group, otherwise the instruction encoding +is reserved. + +NOTE: The non-overlap constraint avoids WAR hazards on the +input vectors during execution, and enables restart with non-zero +`vstart`. + +===== Vector Slidedown Instructions + +---- + vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+x[rs1]] + vslidedown.vi vd, vs2, uimm, vm # vd[i] = vs2[i+uimm] +---- + +For `vslidedown`, the value in `vl` specifies the maximum number of +destination elements that are written. The remaining elements past +`vl` are handled according to the current tail policy (Section +<<sec-agnostic>>). + +The start index (_OFFSET_) for the source can be either specified +using an unsigned integer in the `x` register specified by `rs1`, or a +5-bit immediate, zero-extended to XLEN bits. +If XLEN > SEW, _OFFSET_ is _not_ truncated to SEW bits. + +---- + vslidedown behavior for source elements for element i in slide (`vstart` < `vl`) + 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] + VLMAX <= i+OFFSET src[i] = 0 + + vslidedown behavior for destination element i in slide (`vstart` < `vl`) + 0 <= i < vstart Unchanged + vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy + +---- + +===== Vector Slide1up + +Variants of slide are provided that only move by one element but which +also allow a scalar integer value to be inserted at the vacated +element position. + +---- + vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] +---- + +The `vslide1up` instruction places the `x` register argument at +location 0 of the destination vector register group, provided that +element 0 is active, otherwise the destination element update follows the +current mask agnostic/undisturbed policy. If XLEN < SEW, the value is +sign-extended to SEW bits. If XLEN > SEW, the least-significant bits +are copied over and the high XLEN-SEW bits are ignored. + +The remaining active `vl`-1 elements are copied over from index _i_ in +the source vector register group to index _i_+1 in the destination +vector register group. + +The `vl` register specifies the maximum number of destination vector +register elements updated with source values, and remaining elements +past `vl` are handled according to the current tail policy (Section +<<sec-agnostic>>). + + +---- + vslide1up behavior when vl > 0 + + i < vstart unchanged + 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled + max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy +---- + +The `vslide1up` instruction requires that the destination vector +register group does not overlap the source vector register group. +Otherwise, the instruction encoding is reserved. + +[[sec-vfslide1up]] +===== Vector Floating-Point Slide1up Instruction + +---- + vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] +---- + +The `vfslide1up` instruction is defined analogously to `vslide1up`, +but sources its scalar argument from an `f` register. + +===== Vector Slide1down Instruction + +The `vslide1down` instruction copies the first `vl`-1 active elements +values from index _i_+1 in the source vector register group to index +_i_ in the destination vector register group. + +The `vl` register specifies the maximum number of destination vector +register elements written with source values, and remaining elements +past `vl` are handled according to the current tail policy (Section +<<sec-agnostic>>). + +---- + vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] +---- + +The `vslide1down` instruction places the `x` register argument at +location `vl`-1 in the destination vector register, provided that +element `vl-1` is active, otherwise the destination element update +follows the current mask agnostic/undisturbed policy. +If XLEN < SEW, the value is sign-extended to SEW bits. If +XLEN > SEW, the least-significant bits are copied over and the high +SEW-XLEN bits are ignored. + +---- + vslide1down behavior + + i < vstart unchanged + vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled + vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled + vl <= i < VLMAX Follow tail policy +---- + +NOTE: The `vslide1down` instruction can be used to load values into a +vector register without using memory and without disturbing other +vector registers. This provides a path for debuggers to modify the +contents of a vector register, albeit slowly, with multiple repeated +`vslide1down` invocations. + +[[sec-vfslide1down]] +===== Vector Floating-Point Slide1down Instruction + +---- + vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] +---- + +The `vfslide1down` instruction is defined analogously to `vslide1down`, +but sources its scalar argument from an `f` register. + +==== Vector Register Gather Instructions + +The vector register gather instructions read elements from a first +source vector register group at locations given by a second source +vector register group. The index values in the second vector are +treated as unsigned integers. The source vector can be read at any +index < VLMAX regardless of `vl`. The maximum number of elements to write to +the destination register is given by `vl`, and the remaining elements +past `vl` are handled according to the current tail policy +(Section <<sec-agnostic>>). The operation can be masked, and the mask +undisturbed/agnostic policy is followed for inactive elements. + +---- +vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +---- + +The `vrgather.vv` form uses SEW/LMUL for both the data and +indices. The `vrgatherei16.vv` form uses SEW/LMUL for the data in +`vs2` but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in `vs1`. + +NOTE: When SEW=8, `vrgather.vv` can only reference vector elements +0-255. The `vrgatherei16` form can index 64K elements, and can also +be used to reduce the register capacity needed to hold indices when +SEW > 16. + +If an element index is out of range ( `vs1[i]` {ge} VLMAX ) +then zero is returned for the element value. + +Vector-scalar and vector-immediate forms of the register gather are +also provided. These read one element from the source vector at the +given index, and write this value to the active elements +of the destination vector register. The index value in the scalar +register and the immediate, zero-extended to XLEN bits, are treated as +unsigned integers. If XLEN > SEW, the index value is _not_ truncated +to SEW bits. + +NOTE: These forms allow any vector element to be "splatted" to an entire vector. + +---- +vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] +vrgather.vi vd, vs2, uimm, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm] +---- + +For any `vrgather` instruction, the destination vector register group +cannot overlap with the source vector register groups, otherwise the +instruction encoding is reserved. + +==== Vector Compress Instruction + +The vector compress instruction allows elements selected by a vector +mask register from a source vector register group to be packed into +contiguous elements at the start of the destination vector register +group. + +---- + vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled +---- + +The vector mask register specified by `vs1` indicates which of the +first `vl` elements of vector register group `vs2` should be extracted +and packed into contiguous elements at the beginning of vector +register `vd`. The remaining elements of `vd` are treated as tail +elements according to the current tail policy (Section +<<sec-agnostic>>). + +---- + Example use of vcompress instruction + + 8 7 6 5 4 3 2 1 0 Element number + + 1 1 0 1 0 0 1 0 1 v0 + 8 7 6 5 4 3 2 1 0 v1 + 1 2 3 4 5 6 7 8 9 v2 + vsetivli t0, 9, e8, m1, tu, ma + vcompress.vm v2, v1, v0 + 1 2 3 4 8 7 5 2 0 v2 +---- + +`vcompress` is encoded as an unmasked instruction (`vm=1`). The equivalent +masked instruction (`vm=0`) is reserved. + +The destination vector register group cannot overlap the source vector +register group or the source mask register, otherwise the instruction +encoding is reserved. + +A trap on a `vcompress` instruction is always reported with a +`vstart` of 0. Executing a `vcompress` instruction with a non-zero +`vstart` raises an illegal instruction exception. + +NOTE: Although possible, `vcompress` is one of the more difficult +instructions to restart with a non-zero `vstart`, so assumption is +implementations will choose not do that but will instead restart from +element 0. This does mean elements in destination register after +`vstart` will already have been updated. + +===== Synthesizing `vdecompress` + +There is no inverse `vdecompress` provided, as this operation can be +readily synthesized using iota and a masked vrgather: + +---- + Desired functionality of 'vdecompress' + 7 6 5 4 3 2 1 0 # vid + + e d c b a # packed vector of 5 elements + 1 0 0 1 1 1 0 1 # mask vector of 8 elements + p q r s t u v w # destination register before vdecompress + + e q r d c b v a # result of vdecompress +---- + +---- + # v0 holds mask + # v1 holds packed data + # v11 holds input expanded vector and result + viota.m v10, v0 # Calc iota from mask in v0 + vrgather.vv v11, v1, v10, v0.t # Expand into destination +---- +---- + p q r s t u v w # v11 destination register + e d c b a # v1 source vector + 1 0 0 1 1 1 0 1 # v0 mask vector + + 4 4 4 3 2 1 1 0 # v10 result of viota.m + e q r d c b v a # v11 destination after vrgather using viota.m under mask +---- + +==== Whole Vector Register Move + +The `vmv<nr>r.v` instructions copy whole vector registers (i.e., all +VLEN bits) and can copy whole vector register groups. The `nr` value +in the opcode is the number of individual vector registers, NREG, to +copy. The instructions operate as if EEW=SEW, EMUL = NREG, effective +length `evl`= EMUL * VLEN/SEW. + +NOTE: These instructions are intended to aid compilers to shuffle +vector registers without needing to know or change `vl` or `vtype`. + +NOTE: The usual property that no elements are written if `vstart` {ge} `vl` +does not apply to these instructions. +Instead, no elements are written if `vstart` {ge} `evl`. + +NOTE: If `vd` is equal to `vs2` the instruction is an architectural +NOP, but is treated as a hint to implementations that rearrange data +internally that the register group will next be accessed with an EEW +equal to SEW. + +The instruction is encoded as an OPIVI instruction. The number of +vector registers to copy is encoded in the low three bits of the +`simm` field (`simm[2:0]`) using the same encoding as the `nf[2:0]` field for memory +instructions (Figure <<fig-nf>>), i.e., `simm[2:0]` = NREG-1. + +The value of NREG must be 1, 2, 4, or 8, and values of `simm[4:0]` +other than 0, 1, 3, and 7 are reserved. + +NOTE: A future extension may support other numbers of registers to be moved. + +NOTE: The instruction uses the same funct6 encoding as the `vsmul` +instruction but with an immediate operand, and only the unmasked +version (`vm=1`). This encoding is chosen as it is close to the +related `vmerge` encoding, and it is unlikely the `vsmul` instruction +would benefit from an immediate form. + +---- + vmv<nr>r.v vd, vs2 # General form + + vmv1r.v v1, v2 # Copy v1=v2 + vmv2r.v v10, v12 # Copy v10=v12; v11=v13 + vmv4r.v v4, v8 # Copy v4=v8; v5=v9; v6=v10; v7=v11 + vmv8r.v v0, v8 # Copy v0=v8; v1=v9; ...; v7=v15 +---- + +The source and destination vector register numbers must be aligned +appropriately for the vector register group size, and encodings with +other vector register numbers are reserved. + +NOTE: A future extension may relax the vector register alignment +restrictions. + +=== Exception Handling + +On a trap during a vector instruction (caused by either a synchronous +exception or an asynchronous interrupt), the existing `*epc` CSR is +written with a pointer to the trapping vector instruction, while the +`vstart` CSR contains the element index on which the trap was +taken. + +NOTE: We chose to add a `vstart` CSR to allow resumption of a +partially executed vector instruction to reduce interrupt latencies +and to simplify forward-progress guarantees. This is similar to the +scheme in the IBM 3090 vector facility. To ensure forward progress +without the `vstart` CSR, implementations would have to guarantee an +entire vector instruction can always complete atomically without +generating a trap. This is particularly difficult to ensure in the +presence of strided or scatter/gather operations and demand-paged +virtual memory. + +==== Precise vector traps + +NOTE: We assume most supervisor-mode environments with demand-paging +will require precise vector traps. + +Precise vector traps require that: + +. all instructions older than the trapping vector instruction have committed their results +. no instructions newer than the trapping vector instruction have altered architectural state +. any operations within the trapping vector instruction affecting result elements preceding the index in the `vstart` CSR have committed their results +. no operations within the trapping vector instruction affecting elements at or following the `vstart` CSR have altered architectural state except if restarting and completing the affected vector instruction will nevertheless produce the correct final state. + +We relax the last requirement to allow elements following `vstart` to +have been updated at the time the trap is reported, provided that +re-executing the instruction from the given `vstart` will correctly +overwrite those elements. + +In idempotent memory regions, vector store instructions may have +updated elements in memory past the element causing a synchronous +trap. Non-idempotent memory regions must not have been updated for +indices equal to or greater than the element that caused a synchronous +trap during a vector store instruction. + +Except where noted above, vector instructions are allowed to overwrite +their inputs, and so in most cases, the vector instruction restart +must be from the `vstart` element index. However, there are a number of +cases where this overwrite is prohibited to enable execution of the +vector instructions to be idempotent and hence restartable from an +earlier index location. + +Implementations must ensure forward progress can be eventually +guaranteed for the element or segment reported by `vstart`. + +==== Imprecise vector traps + +Imprecise vector traps are traps that are not precise. In particular, +instructions newer than `*epc` may have committed results, and +instructions older than `*epc` may have not completed execution. +Imprecise traps are primarily intended to be used in situations where +reporting an error and terminating execution is the appropriate +response. + +NOTE: A profile might specify that interrupts are precise while other +traps are imprecise. We assume many embedded implementations will +generate only imprecise traps for vector instructions on fatal errors, +as they will not require resumable traps. + +Imprecise traps shall report the faulting element in `vstart` for +traps caused by synchronous vector exceptions. + +There is no support for imprecise traps in the current standard extensions. + +==== Selectable precise/imprecise traps + +Some profiles may choose to provide a privileged mode bit to select +between precise and imprecise vector traps. Imprecise mode would run +at high-performance but possibly make it difficult to discern error +causes, while precise mode would run more slowly, but support +debugging of errors albeit with a possibility of not experiencing the +same errors as in imprecise mode. + +This mechanism is not defined in the current standard extensions. + +==== Swappable traps + +Another trap mode can support swappable state in the vector unit, +where on a trap, special instructions can save and restore the vector +unit microarchitectural state, to allow execution to continue +correctly around imprecise traps. + +This mechanism is not defined in the current standard extensions. + +NOTE: A future extension might define a standard way of saving and +restoring opaque microarchitectural state from a vector unit +implementation to support context switching with imprecise traps. + +[[sec-vector-extensions]] +=== Standard Vector Extensions + +This section describes the standard vector extensions. +A set of smaller extensions intended for embedded +use are named with a "Zve" prefix, while a larger vector extension +designed for application processors is named as a single-letter V +extension. A set of vector length extension names with prefix "Zvl" +are also provided. + +The initial vector extensions are designed to act as a base for +additional vector extensions in various domains, including +cryptography and machine learning. + +==== Zvl*: Minimum Vector Length Standard Extensions + +All standard vector extensions have a minimum required VLEN as +described below. A set of vector length extensions are provided to +increase the minimum vector length of a vector extension. + +NOTE: The vector length extensions can be used to either specify +additional software or architecture profile requirements, or to +advertise hardware capabilities. + +.Vector length extensions +[cols="1,1"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Extension | Minimum VLEN + +| Zvl32b | 32 +| Zvl64b | 64 +| Zvl128b | 128 +| Zvl256b | 256 +| Zvl512b | 512 +| Zvl1024b | 1024 +|=== + +NOTE: Longer vector length extensions should follow the same pattern. + +NOTE: Every vector length extension effectively includes all shorter +vector length extensions. + +NOTE: The syntax for extension names is being revised, and these names +are subject to change. The trailing "b" will be required to +disambiguate numeric fields from version numbers. + +NOTE: Explicit use of the Zvl32b extension string is not required for +any standard vector extension as they all effectively mandate at least +this minimum, but the string can be useful when stating hardware +capabilities. + +==== Zve*: Vector Extensions for Embedded Processors + +The following five standard extensions are defined to provide varying +degrees of vector support and are intended for use with embedded +processors. Any of these extensions can be added to base ISAs with +XLEN=32 or XLEN=64. The table lists the minimum VLEN and supported +EEWs for each extension as well as what floating-point types are +supported. + +.Embedded vector extensions +[cols="1,1,2,1,1"] +[%autowidth,float="center",align="center",options="header"] +|=== +| Extension | Minimum VLEN | Supported EEW | FP32 | FP64 + +| Zve32x | 32 | 8, 16, 32 | N | N +| Zve32f | 32 | 8, 16, 32 | Y | N +| Zve64x | 64 | 8, 16, 32, 64 | N | N +| Zve64f | 64 | 8, 16, 32, 64 | Y | N +| Zve64d | 64 | 8, 16, 32, 64 | Y | Y +|=== + +The Zve32f and Zve64x extensions depend on the Zve32x extension. +The Zve64f extension depends on the Zve32f and Zve64x extensions. +The Zve64d extension depends on the Zve64f extension. + +All Zve* extensions have precise traps. + +NOTE: There is currently no standard support for handling imprecise +traps, so standard extensions have to provide precise traps. + +All Zve* extensions provide support for EEW of 8, 16, and 32, and +Zve64* extensions also support EEW of 64. + +All Zve* extensions support the vector configuration instructions +(Section <<sec-vector-config>>). + +All Zve* extensions support all vector load and store instructions +(Section <<sec-vector-memory>>), except Zve64* extensions do not +support EEW=64 for index values when XLEN=32. + +All Zve* extensions support all vector integer instructions (Section +<<sec-vector-integer>>), except that the `vmulh` integer multiply +variants that return the high word of the product (`vmulh.vv`, +`vmulh.vx`, `vmulhu.vv`, `vmulhu.vx`, `vmulhsu.vv`, `vmulhsu.vx`) are +not included for EEW=64 in Zve64*. + +NOTE: Producing the high-word of a product can take substantial +additional gates for large EEW. + +All Zve* extensions support all vector fixed-point arithmetic +instructions (<<sec-vector-fixed-point>>), except that `vsmul.vv` and +`vsmul.vx` are not included in EEW=64 in Zve64*. + +NOTE: As with `vmulh`, `vsmul` requires a large amount of additional +logic, and 64-bit fixed-point multiplies are relatively rare. + +All Zve* extensions support all vector integer single-width and +widening reduction operations (Sections <<sec-vector-integer-reduce>>, +<<sec-vector-integer-reduce-widen>>). + +All Zve* extensions support all vector mask instructions (Section +<<sec-vector-mask>>). + +All Zve* extensions support all vector permutation instructions +(Section <<sec-vector-permute>>), except that Zve32x and Zve64x +do not include those with floating-point operands, and Zve64f does not include those +with EEW=64 floating-point operands. + +The Zve32x extension depends on the Zicsr extension. +The Zve32f and Zve64f extensions depend upon the F extension, +and implement all +vector floating-point instructions (Section <<sec-vector-float>>) for +floating-point operands with EEW=32. Vector single-width floating-point reduction +operations (<<sec-vector-float-reduce>>) for EEW=32 are supported. + +The Zve64d extension depends upon the D extension, +and implements all vector +floating-point instructions (Section <<sec-vector-float>>) for +floating-point operands with EEW=32 or EEW=64 (including widening +instructions and conversions between FP32 and FP64). Vector +single-width floating-point reductions (<<sec-vector-float-reduce>>) +for EEW=32 and EEW=64 are supported as well as widening reductions +from FP32 to FP64. + +==== V: Vector Extension for Application Processors + +The single-letter V extension is intended for use in application +processor profiles. + +The `misa.v` bit is set for implementations providing `misa` and +supporting V. + +The V vector extension has precise traps. + +The V vector extension depends upon the Zvl128b and Zve64d extensions. + +NOTE: The value of 128 was chosen as a compromise for application +processors. Providing a larger VLEN allows stripmining code to be +elided in some cases for short vectors, but also increases the size of +the minimum implementation. Note that larger LMUL can be used to +avoid stripmining for longer known-size application vectors at the +cost of having fewer available vector register groups. For example, an +LMUL of 8 allows vectors of up to sixteen 64-bit elements to be +processed without stripmining using four vector register groups. + +The V extension supports EEW of 8, 16, and 32, and 64. + +The V extension supports the vector configuration instructions +(Section <<sec-vector-config>>). + +The V extension supports all vector load and store instructions +(Section <<sec-vector-memory>>), except the V extension does not +support EEW=64 for index values when XLEN=32. + +The V extension supports all vector integer instructions (Section +<<sec-vector-integer>>). + +The V extension supports all vector fixed-point arithmetic +instructions (<<sec-vector-fixed-point>>). + +The V extension supports all vector integer single-width and +widening reduction operations (Sections <<sec-vector-integer-reduce>>, +<<sec-vector-integer-reduce-widen>>). + +The V extension supports all vector mask instructions (Section +<<sec-vector-mask>>). + +The V extension supports all vector permutation instructions (Section +<<sec-vector-permute>>). + +The V extension depends upon the F and D +extensions, and implements all vector floating-point instructions +(Section <<sec-vector-float>>) for floating-point operands with EEW=32 +or EEW=64 (including widening instructions and conversions between +FP32 and FP64). Vector single-width floating-point reductions +(<<sec-vector-float-reduce>>) for EEW=32 and EEW=64 are supported as +well as widening reductions from FP32 to FP64. + +[NOTE] +==== +As is the case with other RISC-V extensions, it is valid to +include overlapping extensions in the same ISA string. For example, +RV64GCV and RV64GCV_Zve64f are both valid and equivalent ISA strings, +as is RV64GCV_Zve64f_Zve32x_Zvl128b. +==== + +==== Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point + +The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008 +binary16 values, adding conversions to and from binary32. +When the Zvfhmin extension is implemented, the `vfwcvt.f.f.v` and +`vfncvt.f.f.w` instructions become defined when SEW=16. +The EEW=16 floating-point operands of these instructions use the binary16 +format. + +The Zvfhmin extension depends on the Zve32f extension. + +==== Zvfh: Vector Extension for Half-Precision Floating-Point + +The Zvfh extension provides support for vectors of IEEE 754-2008 +binary16 values. +When the Zvfh extension is implemented, all instructions in Sections +<<sec-vector-float>>, <<sec-vector-float-reduce>>, +<<sec-vector-float-reduce-widen>>, <<sec-vector-float-move>>, +<<sec-vfslide1up>>, and <<sec-vfslide1down>> +become defined when SEW=16. +The EEW=16 floating-point operands of these instructions use the binary16 +format. + +Additionally, conversions between 8-bit integers and binary16 values are +provided. The floating-point-to-integer narrowing conversions +(`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point +widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8. + +The Zvfh extension depends on the Zve32f and Zfhmin extensions. + +NOTE: Requiring basic scalar half-precision support makes Zvfh's +vector-scalar instructions substantially more useful. +We considered requiring more complete scalar half-precision support, but we +reasoned that, for many half-precision vector workloads, performing the scalar +computation in single-precision will suffice. + +=== Vector Instruction Listing + +include::images/wavedrom/v-inst-table.adoc[] + diff --git a/src/vector-crypto.adoc b/src/vector-crypto.adoc new file mode 100644 index 0000000..dc1d08f --- /dev/null +++ b/src/vector-crypto.adoc @@ -0,0 +1,4964 @@ +== RISC-V Cryptography Extensions Volume II: Vector Instructions, Version 1.0.0 + +This document describes the Vector Cryptography extensions to the +RISC-V Instruction Set Architecture. + +This document is _Ratified_. +No changes are allowed. Any desired or needed changes can be the +subject of a follow-on new extension. Ratified extensions are never +revised. +For more information, see link:http://riscv.org/spec-state[here]. + +[[crypto_vector_introduction]] +=== Introduction + +This document describes the proposed _vector_ cryptography +extensions for RISC-V. +All instructions proposed here are based on the Vector registers. +The instructions are designed to be highly performant, with large +application and server-class cores being the main target. +A companion chapter _Volume I: Scalar & Entropy Source Instructions_, +describes +cryptographic instruction proposals for smaller cores which do not +implement the vector extension. + +[[crypto_vector_audience]] +==== Intended Audience + +Cryptography is a specialized subject, requiring people with many different +backgrounds to cooperate in its secure and efficient implementation. +Where possible, we have written this specification to be understandable by +all, though we recognize that the motivations and references to +algorithms or other specifications and standards may be unfamiliar to those +who are not domain experts. + +This specification anticipates being read and acted on by various people +with different backgrounds. +We have tried to capture these backgrounds +here, with a brief explanation of what we expect them to know, and how +it relates to the specification. +We hope this aids people's understanding of which aspects of the specification +are particularly relevant to them, and which they may (safely!) ignore or +pass to a colleague. + +Cryptographers and cryptographic software developers:: +These are the people we expect to write code using the instructions +in this specification. +They should understand the motivations for the +instructions we include, and be familiar with most of the algorithms +and outside standards to which we refer. + +Computer architects:: +We do not expect architects to have a cryptography background. +We nonetheless expect architects to be able to examine our instructions +for implementation issues, understand how the instructions will be used +in context, and advise on how best to fit the functionality the +cryptographers want. + +Digital design engineers & micro-architects:: +These are the people who will implement the specification inside a +core. Again, no cryptography expertise is assumed, but we expect them to +interpret the specification and anticipate any hardware implementation +issues, e.g., where high-frequency design considerations apply, or where +latency/area tradeoffs exist etc. +In particular, they should be aware of the literature around efficiently +implementing AES and SM4 SBoxes in hardware. + +Verification engineers:: +These people are responsible for ensuring the correct implementation of the +extensions in hardware. +No cryptography background is assumed. +We expect them to identify interesting test cases from the +specification. An understanding of their real-world usage will help with this. + +These are by no means the only people concerned with the specification, +but they are the ones we considered most while writing it. + +[[crypto_vector_sail_specifications]] +==== Sail Specifications + +RISC-V maintains a +link:https://github.com/riscv/sail-riscv[formal model] +of the ISA specification, +implemented in the Sail ISA specification language +cite:[sail]. +Note that _Sail_ refers to the specification language itself, +and that there is a _model of RISC-V_, written using Sail. + +It was our intention to include actual Sail code in this specification. +However, the Vector Crypto Sail model needs the Vector Sail model as a +basis on which to build. This Vector Cryptography extensions specification +was completed before there was an approved RISC-V Vector Sail Model. +Therefore, we don't have any Sail code to include in the instruction +descriptions. Instead we have included Sail-like pseudo code. While we have +endeavored to adhere to Sail syntax, we have taken some liberties for the +sake of simplicity where we believe that that our intent is clear to the +reader. + +[NOTE] +==== +Where variables are concatenated, the order shown is how they would appear +in a vector register from left to right. +For example, an element group specified as `{a, b, e, f}` would appear in a vector +register with `a` having the highest element index of the group and `f` having the +lowest index of the group. +==== + +For the sake of brevity, our pseudo code does not include the handling of +masks or tail elements. We follow the _undisturbed_ and _agnostic_ policies +for masks and tails as described in the *RISC-V "V" Vector Extension* +specification. Furthermore, the code does not explicitly handle overlap and SEW +constraints; these are, however, explicitly stated in the text. + +In many cases the pseudo code includes +calls to supporting functions which are too verbose to include directly +in the specification. +This supporting code is listed in +<<crypto_vector_appx_sail>>. + + +The +link:https://github.com/rems-project/sail/blob/sail2/manual.pdf[Sail Manual] +is recommended reading in order to best understand the code snippets. +Also, the +link:https://github.com/billmcspadden-riscv/sail/blob/cookbook_br/cookbook/doc/TheSailCookbook_Complete.pdf[The Sail Programming Language: A Sail Cookbook] +is a good reference that is in the process of being written. + +For the latest RISC-V Sail model, refer to +the formal model Github +link:https://github.com/riscv/sail-riscv[repository]. + +[[crypto_vector_policies]] +==== Policies + +In creating this proposal, we tried to adhere to the following +policies: + +* Where there is a choice between: + 1) supporting diverse implementation strategies for an algorithm + or + 2) supporting a single implementation style which is more performant / + less expensive; + the vector crypto extensions will pick the more constrained but performant + option. + This fits a common pattern in other parts of the RISC-V specifications, + where recommended (but not required) instruction sequences for performing + particular tasks are given as an example, such that both hardware and + software implementers can optimize for only a single use-case. + +* The extensions will be designed to support _existing_ standardized + cryptographic constructs well. + It will not try to support proposed standards, or cryptographic + constructs which exist only in academia. + Cryptographic standards which are settled upon concurrently with or after + the RISC-V vector cryptographic extensions standardization will be dealt with + by future RISC-V vector cryptographic + standard extensions. + +* Historically, there has been some discussion + cite:[LSYRR:04] + on how newly supported operations in general-purpose computing might + enable new bases for cryptographic algorithms. + The standard will not try to anticipate new useful low-level + operations which _may_ be useful as building blocks for + future cryptographic constructs. + +* Regarding side-channel countermeasures: + Where relevant, proposed instructions must aim to remove the + possibility of any timing side-channels. All instructions + shall be implemented with data-independent timing. That is, the latency of + the execution of these instructions shall not vary with different input values. + +[[crypto-vector-element-groups]] +==== Element Groups + +Many vector crypto instructions operate on operands that are wider than elements (which are currently limited +to 64 bits wide). +Typically, these operands are 128- and 256-bits wide. In many cases, these operands are comprised of smaller +operands that are combined (for example, each SHA-2 operand is comprised of 4 words). However, in other cases +these operands are a single value (for example, in the AES round instructions, each operand is 128-bit block +or round key). + +We treat these operands as a vector of one or more _element groups_ as defined in the +link:https://github.com/riscv/riscv-v-spec/blob/master/element_groups.adoc[RISC-V Vector Element Groups] +specification. + +Each vector crypto instruction that operates on element groups explicitly specifies their three defining +parameters: EGW, EGS, and EEW. + +[%autowidth] +[%header,cols="4,4,4,4,4"] +|=== +| Instruction Group +| Extension +| EGW +| EEW +| EGS + +| AES | <<zvkned>> | 128 | 32 | 4 +| SHA256 | <<zvknh,zvknh[ab]>> | 128 | 32 | 4 +| SHA512 | <<zvknh,zvknhb>> | 256 | 64 | 4 +| GCM | <<zvkg>> | 128 | 32 | 4 +| SM4 | <<zvksed>> | 128 | 32 | 4 +| SM3 | <<Zvksh>> | 256 | 32 | 8 +|=== + +[NOTE] +==== +- Element Group Width (`EGW`) - total number of bits in an element group +- Effective Element Width (`EEW`) - number of bits in each element +- Element Group Size (`EGS`) - number of elements in an element group +==== + +For all of the vector crypto instructions in this specification, `EEW`=`SEW`. + +[NOTE] +==== +The required `SEW` for each cryptographic instruction was chosen to match what is +typically needed for other instructions when implementing the targeted algorithm. +==== + +- A *Vector Element Group* is a vector of one or more element groups. +- A *Scalar Element Group* is a single element group. + +Element groups can be formed across registers in implementations where +`VLEN`< `EGW` by using an `LMUL`>1. + +[NOTE] +==== +Since the the *vector extension for application processors* requires a minimum of VLEN of 128, +at most such implementations would require LMUL=2 to form the largest element groups in this specification. + +However, implementations with a smaller VLEN, such as embedded designs, will requires a larger `LMUL` +to form the necessary element groups. +It is important to keep in mind that this reduces the number of register groups available such +that it may be difficult or impossible to write efficient code for the intended cryptographic algorithms. + +For example, an implementation with `VLEN`=32 would need to set `LMUL`=8 to create a +256-bit element group for `SM3`. This would mean that there would only be 4 register groups, +3 of which would be consumed by a single `SM3` message-expansion instruction. +==== + +As with all vector instructions, the number of elements processed is specified by the +vector length `vl`. The number of element groups operated upon is then `vl`/`EGS`. +Likewise the starting element group is `vstart`/`EGS`. +See <<crypto-vector-instruction-constraints>> for limitations on `vl` and `vstart` +for vector crypto instructions. + +// If this ratio is not an integer for a vector crypto instruction, an illegal instruction exception is raised. + +// Since `vstart` is expressed in elements, the starting element group is `vstart`/`EGS`. +// If this ratio is not an integer for a vector crypto instruction, an illegal instruction exception is raised. + +[[crypto-vector-instruction-constraints]] +==== Instruction Constraints +The following is a quick reference for the various constraints of specific Vector Crypto instructions. + +vl and vstart constraints:: +Since `vl` and `vstart` refer to elements, Vector Crypto instructions that use elements groups +(See <<crypto-vector-element-groups>>) require that these values are an integer multiple of the +Element Group Size (`EGS`). + +- Instructions that violate the `vl` or `vstart` requirements are _reserved_. + +[%autowidth] +[%header,cols="4,4"] +|=== +| Instructions +| EGS + +| vaes* | 4 +| vsha2* | 4 +| vg* | 4 +| vsm3* | 8 +| vsm4* | 4 + +|=== + +LMUL constraints:: +For element-group instructions, `LMUL`*`VLEN` must always be at least as large as `EGW`, otherwise an +_illegal instruction exception_ is raised, even if `vl`=0. + +[%autowidth] +[%header,cols="4,2,2"] +|=== +| Instructions +| SEW +| EGW + +| vaes* | 32 | 128 +| vsha2* | 32 | 128 +| vsha2* | 64 | 256 +| vg* | 32 | 128 +| vsm3* | 32 | 256 +| vsm4* | 32 | 128 + +|=== + + +SEW constraints:: +Some Vector Crypto instructions are only defined for a specific `SEW`. In such a case +all other `SEW` values are _reserved_. + +[%autowidth] +[%header,cols="4,4"] +|=== +| Instructions +| Required SEW + +| vaes* | 32 +| Zvknha: vsha2* | 32 +| Zvknhb: vsha2* | 32 or 64 +| vclmul[h] | 64 +| vg* | 32 +| vsm3* | 32 +| vsm4* | 32 + + +|=== + +Source/Destination overlap constraints:: +Some Vector Crypto instructions have overlap constraints. Encodings that violate these constraints are _reserved_. + +In the case of the `.vs` instructions defined in this specification, `vs2` holds a 128-bit scalar element group. +For implementations with `VLEN` ≥ 128, `vs2` refers to a single register. Thus, the `vd` register group must not +overlap the `vs2` register. +However, in implementations where `VLEN` < 128, `vs2` refers to a register group comprised of the number +of registers needed to hold the 128-bit scalar element group. In this case, the `vd` register group must not +overlap this `vs2` register group. + +[%autowidth] +[%header,cols="4,4,4"] +|=== +| Instruction +| Register +| Cannot Overlap + +| vaes*.vs | vs2 | vd +| vsm4r.vs | vs2 | vd +| vsha2c[hl] | vs1, vs2 | vd +| vsha2ms | vs1, vs2 | vd +| sm3me | vs2 | vd +| vsm3c | vs2 | vd + + +|=== + +[[crypto-vector-scalar-instructions]] +==== Vector-Scalar Instructions + +The RISC-V Vector Extension defines three encodings for Vector-Scalar operations which get their scalar operand from a GPR or FP register: + +- OPIVX: Scalar GPR _x_ register +- OPFVF: Scalar FP _f_ register +- OPMVX: Scalar GPR _x_ register + +However, the Vector Extensions include Vector Reduction Operations which can also be considered +Vector-Scalar operations because a scalar operand is provided from element 0 of +vector register `vs1`. The vector operand is provided in vector register group `vs2`. +These reduction operations all use the `.vs` suffix in their mnemonics. Additionally, the reduction operations all produce a scalar result in element 0 of the destination register, `vd`. + +The Vector Crypto Extensions define Vector-Scalar instructions that are similar to these +Vector Reduction Operations in that they get a scalar operand from a vector register. However, they differ +in that they get a scalar element group +(see <<crypto-vector-element-groups>>) +// link:https://github.com/riscv/riscv-v-spec/blob/master/element_groups.adoc[RISC-V Vector Element Groups]) +from `vs2` and they return _vector_ results to `vd`, which is also a source vector operand. +These Vector-Scalar crypto instructions also use the `.vs` suffix in their mnemonics. + +[NOTE] +==== +We chose to use `vs2` as the scalar operand, and `vd` as the vector operand, so that we could use the `vs1` +specifier as additional encoding bits for these instructions. This allows these instructions to have a +much smaller encoding footprint, leaving more rooms for other instructions in the future. +==== + +These instructions enable a single key, specified as a scalar element group in `vs2`, to be +applied to each element group of register group `vd`. + +[NOTE] +==== +Scalar element groups will occupy at most a single register in application processors. However, in implementations where +VLEN<128, they will occupy 2 (VLEN=64) or 4 (VLEN=32) registers. +==== + + +[NOTE] +==== +It is common for multiple AES encryption rounds (for example) to be performed in parallel with the same +round key (e.g. in counter modes). +Rather than having to first splat the common key across the whole vector group, these vector-scalar +crypto instructions allow the round key to be specified as a scalar element group. +==== + +// In the case of AES256 all-rounds instructions we need to provide two 128-bit keys; one is held in `vs1` and +// the other is held in `vs2`. The 128-bit data to be processed is held in `vd`. +// A vector-scalar form of this instruction looks different from the existing vector-scalar instructions in that +// both `vs1` and `vs2` are treated as scalar operands that apply to the vector operands of `vd`. + +// [NOTE] +// ==== +// Previously, the AES and SM4 instructions that performed rounds operations (including AES all-rounds instructions) +// were defined to be destructive operations where the data source was provided in `vd` and the key was provided in +// `vs2`. With the advent of the new crypto vector-scalar instructions, we are changing these instructions +// to use `vs1` for the key and `vs2` for the data. +// In the case of vector-scalar instructions, the scalar key will be held in +// element group 0 of `vs1` . This is done to remain consistent with the use of `vs1` for the scalar element in +// all of the existing vector-scalar operations as well as the vector reduction operations. +// ==== + +[[crypto-vector-software-portability]] +==== Software Portability +The following contains some guidelines that enable the portability of vector-crypto-based code +to implementations with different values for `VLEN` + +Application Processors:: +Application processors are expected to follow the V-extension and will therefore have `VLEN` ≥ 128. + + + +// [NOTE] +// ==== +Since most of the _cryptography-specific_ instructions have an `EGW`=128, nothing special needs to be done +for these instructions to support implementations with `VLEN`=128. + +However, the SHA-512 and SM3 instructions have an `EGW`=256. Implementations with `VLEN` = 128, require that +`LMUL` is doubled for these instructions in order to create 256-bit elements across a pair of registers. +Code written with this doubling of `LMUL` will not affect the results returned by implementations with `VLEN` ≥ 256 +because `vl` controls how many element groups are processed. Therefore, we recommend that libraries that implement +SHA-512 and SM3 employ this doubling of `LMUL` to ensure that the software can run on all implementation +with `VLEN` ≥ 128. + +While the doubling of `LMUL` for these instructions is _safe_ for implementations with `VLEN` ≥ 256, it may be less +optimal as it will result in unnecessary register pressure and might exact a performance penalty in +some microarchitectures. Therefore, we suggest that in addition to providing portable code for SHA-512 and SM3, +libraries should also include more optimal code for these instructions when `VLEN` ≥ 256. +// ==== + +[%autowidth] +[%header,cols="4,4,4,4"] +|=== +| Algorithm +| Instructions +| VLEN +| LMUL + +| SHA-512 | vsha2* | 64 | vl/2 +| SM3 | vsm3* | 32 | vl/4 +|=== + +// [NOTE] +// ==== +// We recommend that all library code for application processors be written so that it can be run on any +// implementation with `VLEN` ≥ 128. Such libraries are also encouraged to have versions of code for +// SHA-512 and SM3 optimized for implementations with `VLEN` ≥ 256. +// ==== + +Embedded Processors:: + +Embedded processors will typically have implementations with `VLEN` < 128. This will require code to be written with +larger `LMUL` values to enable the element groups to be formed. + +The `.vs` instructions require scalar element groups of `EGW`=128. On implementations with `VLEN` < 128, these scalar +element groups will necessarily be formed across registers. This is different from most scalars in vector instructions +that typically consume part of a single register. + + +// [NOTE] +// ==== +We recommend that different code be available for `VLEN`=32 and `VLEN`=64, as code written for `VLEN`=32 will +likely be too burdensome for `VLEN`=64 implementations. +// ==== + +[[crypto_vector_extensions]] +=== Extensions Overview + +The section introduces all of the extensions in the Vector Cryptography +Instruction Set Extension Specification. + +The <<zvknh,Zvknhb>> and <<zvbc>> Vector Crypto Extensions +--and accordingly the composite extensions <<Zvkn>> and <<Zvks>>-- +require a Zve64x base, +or application ("V") base Vector Extension. + +All of the other Vector Crypto Extensions can be built +on _any_ embedded (Zve*) or application ("V") base Vector Extension. + +// See <<crypto-vector-element-groups>> for more details on vector element groups and the drawbacks of +// small `VLEN` values. + + +All _cryptography-specific_ instructions defined in this Vector Crypto specification (i.e., those +in <<zvkned>>, <<zvknh,Zvknh[ab]>>, <<Zvkg>>, <<Zvksed>> and <<zvksh>> but _not_ <<zvbb>>,<<zvkb>>, or <<zvbc>>) shall +be executed with data-independent execution latency as defined in the +link:https://github.com/riscv/riscv-crypto/releases/tag/v1.0.1-scalar[RISC-V Scalar Cryptography Extensions specification]. +It is important to note that the Vector Crypto instructions are independent of the +implementation of the `Zkt` extension and do not require that `Zkt` is implemented. + +This specification includes a <<Zvkt>> extension that, when implemented, requires certain vector instructions +(including <<zvbb>>, <<zvkb>>, and <<zvbc>>) to be executed with data-independent execution latency. + +Detection of individual cryptography extensions uses the +unified software-based RISC-V discovery method. + +[NOTE] +==== +At the time of writing, these discovery mechanisms are still a work in +progress. +==== + +[[zvbb,Zvbb]] +==== `Zvbb` - Vector Basic Bit-manipulation + +Vector basic bit-manipulation instructions. + +[NOTE] +==== +This extension is a superset of the <<Zvkb>> extension. +==== + +[%autowidth] +[%header,cols="2,4"] +|=== +|Mnemonic +|Instruction + +| vandn.[vv,vx] | <<insns-vandn>> +| vbrev.v | <<insns-vbrev>> +| vbrev8.v | <<insns-vbrev8>> +| vrev8.v | <<insns-vrev8>> +| vclz.v | <<insns-vclz>> +| vctz.v | <<insns-vctz>> +| vcpop.v | <<insns-vcpop>> +| vrol.[vv,vx] | <<insns-vrol>> +| vror.[vv,vx,vi] | <<insns-vror>> +| vwsll.[vv,vx,vi] | <<insns-vwsll>> + +|=== + +<<< + +[[zvbc,Zvbc]] +==== `Zvbc` - Vector Carryless Multiplication + +General purpose carryless multiplication instructions which are commonly used in cryptography +and hashing (e.g., Elliptic curve cryptography, GHASH, CRC). + +These instructions are only defined for `SEW`=64. + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Mnemonic +|Instruction +| vclmul.[vv,vx] | <<insns-vclmul>> +| vclmulh.[vv,vx] | <<insns-vclmulh>> + +|=== + +<<< + +[[zvkb,Zvkb]] +==== `Zvkb` - Vector Cryptography Bit-manipulation + +Vector bit-manipulation instructions that are essential +for implementing common cryptographic workloads securely & +efficiently. + +[NOTE] +==== +This Zvkb extension is a proper subset of the Zvbb extension. +Zvkb allows for vector crypto implementations without incuring +the the cost of implementing the additional bitmanip instructions +in the Zvbb extension: vbrev.v, vclz.v, vctz.v, vcpop.v, and vwsll.[vv,vx,vi]. +==== + +[%autowidth] +[%header,cols="2,4"] +|=== +|Mnemonic +|Instruction + +| vandn.[vv,vx] | <<insns-vandn>> +// | vbrev.v | <<insns-vbrev>> +| vbrev8.v | <<insns-vbrev8>> +| vrev8.v | <<insns-vrev8>> +// | vclz.v | <<insns-vclz>> +// | vctz.v | <<insns-vctz>> +// | vcpop.v | <<insns-vcpop>> +| vrol.[vv,vx] | <<insns-vrol>> +| vror.[vv,vx,vi] | <<insns-vror>> +// | vwsll.[vv,vx,vi] | <<insns-vwsll>> +|=== + +<<< + +[[zvkg,Zvkg]] +==== `Zvkg` - Vector GCM/GMAC + +Instructions to enable the efficient implementation of GHASH~H~ which is used in Galois/Counter Mode (GCM) and +Galois Message Authentication Code (GMAC). + +All of these instructions work on 128-bit element groups comprised of four 32-bit elements. + +GHASH~H~ is defined in the +// link:https://csrc.nist.gov/publications/detail/sp/800-38d/final[NIST Special Publication 800-38D] + "Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC" + cite:[nist:gcm] +(NIST Specification). + +[NOTE] +==== +GCM is used in conjunction with block ciphers (e.g., AES and SM4) to encrypt a message and +provide authentication. +GMAC is used to provide authentication of a message without encryption. +==== + +To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. + +The number of element groups to be processed is `vl`/`EGS`. +`vl` must be set to the number of `SEW=32` elements to be processed and +therefore must be a multiple of `EGS=4`. + +Likewise, `vstart` must be a multiple of `EGS=4`. + +[%autowidth] +[%header,cols="^2,4,4,4"] +|=== + +|SEW +|EGW +|Mnemonic +|Instruction +| 32 | 128 | vghsh.vv | <<insns-vghsh>> +| 32 | 128 | vgmul.vv | <<insns-vgmul>> + +|=== + +<<< + +[[zvkned,Zvkned]] +==== `Zvkned` - NIST Suite: Vector AES Block Cipher + +Instructions for accelerating +encryption, decryption and key-schedule +functions of the AES block cipher as defined in +Federal Information Processing Standards Publication 197 +cite:[nist:fips:197] + +All of these instructions work on 128-bit element groups comprised of four +32-bit elements. + +For the best performance, it is suggested that these instruction be implemented on systems with `VLEN`>=128. +On systems with `VLEN`<128, element groups may be formed by concatenating 32-bit elements +from two or four registers by using an LMUL =2 and LMUL=4 respectively. + +// Implementations with `VLEN<128` should consider the existing +// Scalar Cryptography Extensions, specifically <<Zkne,Zkne>> and <<Zknd,Zknd>> +// for accelerated cryptographic operations. + +To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. + +The number of element groups to be processed is `vl`/`EGS`. +`vl` must be set to the number of `SEW=32` elements to be processed and +therefore must be a multiple of `EGS=4`. + +Likewise, `vstart` must be a multiple of `EGS=4`. + +[%autowidth] +[%header,cols="^2,4,4,4"] +|=== +|SEW +|EGW +|Mnemonic +|Instruction + +| 32| 128 | vaesef.[vv,vs] | <<insns-vaesef>> +| 32| 128 | vaesem.[vv,vs] | <<insns-vaesem>> +| 32| 128 | vaesdf.[vv,vs] | <<insns-vaesdf>> +| 32| 128 | vaesdm.[vv,vs] | <<insns-vaesdm>> +| 32| 128 | vaeskf1.vi | <<insns-vaeskf1>> +| 32| 128 | vaeskf2.vi | <<insns-vaeskf2>> +| 32| 128 | vaesz.vs | <<insns-vaesz>> +|=== + +<<< + +[[zvknh, zvknh[ab]]] +==== `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash + +Instructions for accelerating SHA-2 as defined in FIPS PUB 180-4 Secure Hash Standard (SHS) +cite:[nist:fips:180:4] + +`SEW` differentiates between SHA-256 (`SEW`=32) and SHA-512 (`SEW`=64). + +- SHA-256: these instructions work on 128-bit element groups comprised of four 32-bit elements. +- SHA-512: these instructions work on 256-bit element groups comprised of four 64-bit elements. + +[%autowidth] +[%header,cols="^2,^2,^2,2"] +|=== +|SEW +|EGW +|SHA-2 +|Extension + +|32 | 128 | SHA-256 | Zvknha, Zvknhb +|64 | 256 | SHA-512 | Zvknhb +|=== + +// link:https://doi.org/10.6028/NIST.FIPS.180-4[FIPS PUB 180-4 Secure Hash Standard (SHS)]) + +- Zvknhb supports SHA-256 and SHA-512. +- Zvknha supports only SHA-256. + +// [NOTE] +// ==== +// Zvknhb is implemented, `SEW` is used to differentiate between SHA-256 (SEW=32) and SHA-512 (SEW=64). +// If Zvknha is implemented, only SHA-256 is supported, and SEW must be 32. +// ==== + +SHA-256 implementations with VLEN < 128 require LMUL>1 to combine +32-bit elements from register groups to provide all four elements of the element group. + +SHA-512 implementations with VLEN < 256 require LMUL>1 to combine +64-bit elements from register groups to provide all four elements of the element group. + +// SHA-2 is defined in +// link:https://doi.org/10.6028/NIST.FIPS.180-4[FIPS PUB 180-4 Secure Hash Standard (SHS)]. + +To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. + +// [NOTE] +// ==== +// It is recommended that implementations have VLEN≥128 for these instructions. +// // Furthermore, for the best performance in SHA512, it is recommended that implementations have VLEN≥256. +// When VLEN<EGW, an appropriate LMUL needs to be used by software so that elements from the +// specified register groups can be combined to form the full element group. +// ==== + +The number of element groups to be processed is `vl`/`EGS`. +`vl` must be set to the number of `SEW` elements to be processed and +therefore must be a multiple of `EGS=4`. + +Likewise, `vstart` must be a multiple of `EGS=4`. + +[%autowidth] +[%header,cols="2,4"] +|=== +// |`VLENmin` +|Mnemonic +|Instruction + +// | 128 +| vsha2ms.vv | <<insns-vsha2ms>> +// | 128 +| vsha2c[hl].vv | <<insns-vsha2c>> +|=== + +<<< + +[[zvksed,Zvksed]] +==== `Zvksed` - ShangMi Suite: SM4 Block Cipher + +Instructions for accelerating +encryption, decryption and key-schedule +functions of the SM4 block cipher. + +The SM4 block cipher is specified in _32907-2016: {SM4} Block Cipher Algorithm_ +cite:[gbt:sm4] + +There are other various sources available that describe the SM4 block cipher. +While not the final version of the standard, +link:https://www.rfc-editor.org/rfc/rfc8998.html[RFC 8998 ShangMi (SM) Cipher Suites for TLS 1.3] +is useful and easy to access. + +// https://datatracker.ietf.org/doc/id/draft-crypto-sm4-00 + +All of these instructions work on 128-bit element groups comprised of four +32-bit elements. + +// Systems which implement `VLEN<128` should consider the existing +// Scalar Cryptography Extensions, specifically <<Zkne,Zkne>> and <<Zknd,Zknd>> +// for accelerated cryptographic operations. + +To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. + +The number of element groups to be processed is `vl`/`EGS`. +`vl` must be set to the number of `SEW=32` elements to be processed and +therefore must be a multiple of `EGS=4`. + +Likewise, `vstart` must be a multiple of `EGS=4`. + +[%autowidth] +[%header,cols="^2,4,4,4"] +|=== +|SEW +|EGW +|Mnemonic +|Instruction + +| 32 | 128 | vsm4k.vi | <<insns-vsm4k>> +| 32 | 128 | vsm4r.[vv,vs] | <<insns-vsm4r>> +|=== + +<<< + +[[zvksh,Zvksh]] +==== `Zvksh` - ShangMi Suite: SM3 Secure Hash + +Instructions for accelerating +functions of the SM3 Hash Function. + +The SM3 secure hash algorithm is specified in _32905-2016: SM3 Cryptographic Hash Algorithm_ +cite:[gbt:sm4] + +There are other various sources available that describe the SM3 secure hash. +While not the final version of the standard, +link:https://www.rfc-editor.org/rfc/rfc8998.html[RFC 8998 ShangMi (SM) Cipher Suites for TLS 1.3] +is useful and easy to access. + +// https://datatracker.ietf.org/doc/id/draft-crypto-sm4-00 + +All of these instructions work on 256-bit element groups comprised of +eight 32-bit elements. + +Implementations with VLEN < 256 require LMUL>1 to combine 32-bit elements from register groups +to provide all eight elements of the element group. + +// The instructions will be most efficient on implementations where `VLEN`≥256. +// They will also provide substantial benefit on implementations where +// `VLEN`=128, but will require an `LMUL`>1 in order to combine elements +// within a register group to form the full element group. +// Implementations with `VLEN`<128 might not be as efficient and should +// consider the existing +// Scalar Cryptography Extensions, specifically `Zkne` and `Zknd`, +// for accelerated cryptographic operations. + +To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. + +The number of element groups to be processed is `vl`/`EGS`. +`vl` must be set to the number of `SEW=32` elements to be processed and +therefore must be a multiple of `EGS=8`. + +Likewise, `vstart` must be a multiple of `EGS=8`. + +[%autowidth] +[%header,cols="2,4,4,4"] +|=== +| SEW +| EGW +| Mnemonic +| Instruction + +| 32 | 256 | vsm3me.vv | <<insns-vsm3me>> +| 32 | 256 | vsm3c.vi | <<insns-vsm3c>> +|=== + +<<< + +[[zvkn,Zvkn]] +==== `Zvkn` - NIST Algorithm Suite + +This extension is shorthand for the following set of other extensions: + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Included Extension +|Description + + +| Zvkned | <<Zvkned>> +| Zvknhb | <<zvknh,Zvknhb>> +// | Zvbb | <<Zvbb>> +| Zvkb | <<Zvkb>> +// | Zvbc | <<Zvbc>> +| Zvkt | <<Zvkt>> +|=== + +[NOTE] +==== +While Zvkg and Zvbc are not part of this extension, it is recommended that at least one of them is implemented with this extension to enable efficient AES-GCM. +==== + +<<< + +[[zvknc,Zvknc]] +==== `Zvknc` - NIST Algorithm Suite with carryless multiply + +This extension is shorthand for the following set of other extensions: + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Included Extension +|Description + + +| Zvkn | <<Zvkn>> +| Zvbc | <<Zvbc>> +|=== + +[NOTE] +==== +This extension combines the NIST Algorithm Suite with the +vector carryless multiply extension to enable AES-GCM. +==== + +<<< + +[[zvkng,Zvkng]] +==== `Zvkng` - NIST Algorithm Suite with GCM + +This extension is shorthand for the following set of other extensions: + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Included Extension +|Description + + +| Zvkn | <<Zvkn>> +| Zvkg | <<Zvkg>> +|=== + +[NOTE] +==== +This extension combines the NIST Algorithm Suite with the +GCM/GMAC extension to enable high-performace AES-GCM. +==== + +<<< + +[[zvks,Zvks]] +==== `Zvks` - ShangMi Algorithm Suite + +This extension is shorthand for the following set of other extensions: + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Included Extension +|Description + + +| Zvksed | <<Zvksed>> +| Zvksh | <<Zvksh>> +// | Zvbb | <<Zvbb>> +| Zvkb | <<Zvkb>> +// | Zvbc | <<Zvbc>> +| Zvkt | <<Zvkt>> +|=== + +[NOTE] +==== +While Zvkg and Zvbc are not part of this extension, it is recommended that at least one of them is implemented with this extension to enable efficient SM4-GCM. +==== + +<<< + +[[zvksc,Zvksc]] +==== `Zvksc` - ShangMi Algorithm Suite with carryless multiplication + +This extension is shorthand for the following set of other extensions: + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Included Extension +|Description + + +| Zvks | <<Zvks>> +| Zvbc | <<Zvbc>> +|=== + +[NOTE] +==== +This extension combines the ShangMi Algorithm Suite with the +vector carryless multiply extension to enable SM4-GCM. +==== + +<<< + +[[zvksg,Zvksg]] +==== `Zvksg` - ShangMi Algorithm Suite with GCM + +This extension is shorthand for the following set of other extensions: + +[%autowidth] +[%header,cols="^2,4"] +|=== +|Included Extension +|Description + + +| Zvks | <<Zvks>> +| Zvkg | <<Zvkg>> +|=== + +[NOTE] +==== +This extension combines the ShangMi Algorithm Suite with the +GCM/GMAC extension to enable high-performace SM4-GCM. +==== + +<<< + +[[zvkt,Zvkt]] +==== `Zvkt` - Vector Data-Independent Execution Latency + +The Zvkt extension requires all implemented instructions from the following list to be +executed with data-independent execution latency as defined in the +link:https://github.com/riscv/riscv-crypto/releases/tag/v1.0.1-scalar[RISC-V Scalar Cryptography Extensions specification]. + +Data-independent execution latency (DIEL) applies to all _data operands_ of an instruction, even those that are not a +part of the body or that are inactive. However, DIEL does not apply +to other values such as vl, vtype, and the mask (when used to control +execution of a masked vector instruction). +Also, DIEL does not apply to constant values specified in the +instruction encoding such as the use of the zero register (`x0`), and, in the +case of immediate forms of an instruction, the values in the immediate +fields (i.e., imm, and uimm). + +In some cases --- which are explicitly specified in the lists below +--- operands that are used as control rather than data +are exempt from DIEL. + +[NOTE] +==== +DIEL helps protect against side-channel timing attacks that are used +to determine data values that are intended to be kept secret. Such +values include cryptographic keys, plain text, and partially encrypted +text. DIEL is not intended to keep software (and cryptographic +algorithms contained therein) secret as it is assumed that an adversary +would already know these. This is why DIEL doesn't apply to constants +embedded in instruction encodings. + +It is important that the _values_ of elements that are not in the body or that are masked off do not affect the execution +latency of the instruction. Sometimes such elements contain data that +also needs to be kept secret. +==== + +===== All <<Zvbb>> instructions +- vandn.v[vx] +- vclz.v +- vcpop.v +- vctz.v +- vbrev.v +- vbrev8.v +- vrev8.v +- vrol.v[vx] +- vror.v[vxi] +- vwsll.[vv,vx,vi] + +[NOTE] +==== +All <<Zvkb>> instructions are also covered by DIEL as they are a +proper subset of <<Zvbb>> +==== + +===== All <<Zvbc>> instructions +- vclmul[h].v[vx] + +===== add/sub +- v[r]sub.v[vx] +- vadd.v[ivx] +- vsub.v[vx] +- vwadd[u].[vw][vx] +- vwsub[u].[vw][vx] + +===== add/sub with carry +- vadc.v[ivx]m +- vmadc.v[ivx][m] +- vmsbc.v[vx]m +- vsbc.v[vx]m + +===== compare and set +- vmseq.v[vxi] +- vmsgt[u].v[xi] +- vmsle[u].v[xi] +- vmslt[u].v[xi] +- vmsne.v[ivx] + +===== copy +- vmv.s.x +- vmv.v.[ivxs] +- vmv[1248]r.v + +===== extend +- vsext.vf[248] +- vzext.vf[248] + +===== logical +- vand.v[ivx] +- vm[n]or.mm +- vmand[n].mm +- vmnand.mm +- vmorn.mm +- vmx[n]or.mm +- vor.v[ivx] +- vxor.v[ivx] + +===== multiply +- vmul[h].v[vx] +- vmulh[s]u.v[vx] +- vwmul.v[vx] +- vwmul[s]u.v[vx] + +===== multiply-add +- vmacc.v[vx] +- vmadd.v[vx] +- vnmsac.v[vx] +- vnmsub.v[vx] +- vwmacc.v[vx] +- vwmacc[s]u.v[vx] +- vwmaccus.vx + +===== Integer Merge +- vmerge.v[ivx]m + +===== permute +In the `.vv` and `.xv` forms of the `vragather[ei16]` instructions, +the values in `vs1` and `rs1` are used for control and therefore are exempt from DIEL. + +- vrgather.v[ivx] +- vrgatherei16.vv + +===== shift +// The values in `vs1`, `rs1`, `imm` are used for control (i.e., shift amount) and are exempt from DIEL. + +- vnsr[al].w[ivx] +- vsll.v[ivx] +- vsr[al].v[ivx] + +===== slide +- vslide1[up|down].vx +- vfslide1[up|down].vf + +In the vslide[up|down].vx instructions, the value in `rs1` +is used for control (i.e., slide amount) and therefore is exempt +from DIEL. + +- vslide[up|down].v[ix] + +[NOTE] +==== +The following instructions are not affected by Zvkt: + +- *All storage operations* +- *All floating-point operations* +- add/sub saturate +* vsadd[u].v[ivx] +* vssub[u].v[vx] +- clip +* vnclip[u].w[ivx] +- compress +* vcompress.vm +- divide +* vdiv[u].v[vx] +* vrem[u].v[vx] +- average +* vaadd[u].v[vx] +* vasub[u].v[vx] +- mask Op +* vcpop.m +* vfirst.m +* vid.v +* viota.m +* vms[bio]f.m +- min/max +* vmax[u].v[vx] +* vmin[u].v[vx] +- Multiply-saturate +* vsmul.v[vx] +- reduce +* vredsum.vs +* vwredsum[u].vs +* vred[and|or|xor].vs +* vred[min|max][u].vs +- shift round +* vssra.v[ivx] +* vssrl.v[ivx] +- vset +* vsetivli +* vsetvl[i] +==== + +[[crypto_vector_insns, reftext="Vector Cryptography Instructions"]] +=== Instructions + +[[insns-vaesdf, Vector AES decrypt final round]] +==== vaesdf.[vv,vs] + +Synopsis:: +Vector AES final-round decryption + +Mnemonic:: +vaesdf.vv vd, vs2 + +vaesdf.vs vd, vs2 + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00001'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101000'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00001'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101001`'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 128 | 4 | 32 | round state +| Vs2 | input | 128 | 4 | 32 | round key +| Vd | output | 128 | 4 | 32 | new round state +|=== + +Description:: +A final-round AES block cipher decryption is performed. + +The InvShiftRows and InvSubBytes steps are applied to each round state element group from `vd`. +This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector +form) or scalar element group in `vs2` (vector-scalar form). + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. + +// if( ((vl%EGS)<>0) | ((vstart%EGS)<>0) | (LMUL*VLEN < EGW)) then { + +Operation:: +[source,sail] +-- +function clause execute (VAESDF(vs2, vd, suffix)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let keyelem = if suffix == "vv" then i else 0; + let state : bits(128) = get_velem(vd, EGW=128, i); + let rkey : bits(128) = get_velem(vs2, EGW=128, keyelem); + let sr : bits(128) = aes_shift_rows_inv(state); + let sb : bits(128) = aes_subbytes_inv(sr); + let ark : bits(128) = sb ^ rkey; + set_velem(vd, EGW=128, i, ark); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vaesdm, Vector AES decrypt middle round]] +==== vaesdm.[vv,vs] + +Synopsis:: +Vector AES middle-round decryption + +Mnemonic:: +vaesdm.vv vd, vs2 + +vaesdm.vs vd, vs2 + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00000'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101000'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00000'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101001'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 128 | 4 | 32 | round state +| Vs2 | input | 128 | 4 | 32 | round key +| Vd | output | 128 | 4 | 32 | new round state +|=== + +Description:: +A middle-round AES block cipher decryption is performed. + +The InvShiftRows and InvSubBytes steps are applied to each round state element group from `vd`. +This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector +form) or the scalar element group in `vs2` (vector-scalar form). The result is then applied to the +InvMixColumns step. + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. +// +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,sail] +-- +function clause execute (VAESDM(vs2, vd, suffix)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let keyelem = if suffix == "vv" then i else 0; + let state : bits(128) = get_velem(vd, EGW=128, i); + let rkey : bits(128) = get_velem(vs2, EGW=128, keyelem); + let sr : bits(128) = aes_shift_rows_inv(state); + let sb : bits(128) = aes_subbytes_inv(sr); + let ark : bits(128) = sb ^ rkey; + let mix : bits(128) = aes_mixcolumns_inv(ark); + set_velem(vd, EGW=128, i, mix); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vaesef, Vector AES encrypt final round]] +==== vaesef.[vv,vs] + +Synopsis:: +Vector AES final-round encryption + +Mnemonic:: +vaesef.vv vd, vs2 + +vaesef.vs vd, vs2 + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00011'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101000'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00011'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101001'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| vd | input | 128 | 4 | 32 | round state +| vs2 | input | 128 | 4 | 32 | round key +| vd | output | 128 | 4 | 32 | new round state +|=== + +Description:: +A final-round encryption function of the AES block cipher is performed. + +The SubBytes and ShiftRows steps are applied to each round state element group from `vd`. +This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector +form) or the scalar element group in `vs2` (vector-scalar form). + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. +// +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + + +Operation:: +[source,sail] +-- +function clause execute (VAESEF(vs2, vd, suffix) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let keyelem = if suffix == "vv" then i else 0; + let state : bits(128) = get_velem(vd, EGW=128, i); + let rkey : bits(128) = get_velem(vs2, EGW=128, keyelem); + let sb : bits(128) = aes_subbytes_fwd(state); + let sr : bits(128) = aes_shift_rows_fwd(sb); + let ark : bits(128) = sr ^ rkey; + set_velem(vd, EGW=128, i, ark); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vaesem, Vector AES encrypt middle round]] +==== vaesem.[vv,vs] + +Synopsis:: +Vector AES middle-round encryption + +Mnemonic:: +vaesem.vv vd, vs2 + +vaesem.vs vd, vs2 + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00010'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101000'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00010'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101001'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group + + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 128 | 4 | 32 | round state +| Vs2 | input | 128 | 4 | 32 | Round key +| Vd | output | 128 | 4 | 32 | new round state +|=== + +Description:: +A middle-round encryption function of the AES block cipher is performed. + +The SubBytes, ShiftRows, and MixColumns steps are applied to each round state element group from `vd`. +This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector +form) or the scalar element group in `vs2` (vector-scalar form). + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. +// +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,sail] +-- +function clause execute (VAESEM(vs2, vd, suffix)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let keyelem = if suffix == "vv" then i else 0; + let state : bits(128) = get_velem(vd, EGW=128, i); + let rkey : bits(128) = get_velem(vs2, EGW=128, keyelem); + let sb : bits(128) = aes_subbytes_fwd(state); + let sr : bits(128) = aes_shift_rows_fwd(sb); + let mix : bits(128) = aes_mixcolumns_fwd(sr); + let ark : bits(128) = mix ^ rkey; + set_velem(vd, EGW=128, i, ark); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vaeskf1, Vector AES-128 Forward KeySchedule]] +==== vaeskf1.vi + +Synopsis:: +Vector AES-128 Forward KeySchedule generation + +Mnemonic:: +vaeskf1.vi vd, vs2, uimm + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'uimm'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '100010'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| uimm | input | - | - | - | Round Number (rnd) +| Vs2 | input | 128 | 4 | 32 | Current round key +| Vd | output | 128 | 4 | 32 | Next round key +|=== + +Description:: +A single round of the forward AES-128 KeySchedule is performed. + +// Within each element group, +The next round key is generated word by word from the +current round key element group in `vs2` and the immediately previous word of the +round key. The least significant word is generated using the most significant +word of the current round key as well as a round constant which is selected by +the round number. + +The round number, which ranges from 1 to 10, comes from `uimm[3:0]`; +`uimm[4]` is ignored. +The out-of-range `uimm[3:0]` values of 0 and 11-15 are mapped to in-range +values by inverting `uimm[3]`. Thus, 0 maps to 8, and 11-15 maps to 3-7. +The round number is used to specify a round constant which is used in generating +the first round key word. + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. + +[NOTE] +==== +We chose to map out-of-range round numbers to in-range values as this allows the instruction's +behavior to be fully defined for all values of `uimm[4:0]` with minimal extra logic. +==== + +// Each `EGW=128` element group next-round-key output is produced and is written to each `EGW=128` +// element group of `vd`. + + +// +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + + +Operation:: +[source,Sail] +-- +function clause execute (VAESKF1(rnd, vd, vs2)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + // project out-of-range immediates onto in-range values + if( (unsigned(rnd[3:0]) > 10) | (rnd[3:0] = 0)) then rnd[3] = ~rnd[3] + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + let r : bits(4) = rnd-1; + + foreach (i from eg_start to eg_len-1) { + let CurrentRoundKey[3:0] : bits(128) = get_velem(vs2, EGW=128, i); + let w[0] : bits(32) = aes_subword_fwd(aes_rotword(CurrentRoundKey[3])) XOR + aes_decode_rcon(r) XOR CurrentRoundKey[0] + let w[1] : bits(32) = w[0] XOR CurrentRoundKey[1] + let w[2] : bits(32) = w[1] XOR CurrentRoundKey[2] + let w[3] : bits(32) = w[2] XOR CurrentRoundKey[3] + set_velem(vd, EGW=128, i, w[3:0]); + } + RETIRE_SUCCESS + } +} + +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vaeskf2, Vector AES-256 Forward KeySchedule]] +==== vaeskf2.vi + +Synopsis:: +Vector AES-256 Forward KeySchedule generation + +Mnemonic:: +vaeskf2.vi vd, vs2, uimm + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'uimm'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101010'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 128 | 4 | 32 | Previous Round key +| uimm | input | - | - | - | Round Number (rnd) +| Vs2 | input | 128 | 4 | 32 | Current Round key +| Vd | output | 128 | 4 | 32 | Next round key +|=== + +Description:: +A single round of the forward AES-256 KeySchedule is performed. + +// Within each element group, +The next round key is generated word by word from the +previous round key element group in `vd` and the immediately previous word of the +round key. The least significant word of the next round key is generated by +applying a function to the most significant word of the current round key and +then XORing the result with the round constant. +The round number is used to select the round constant as well as the function. + +The round number, which ranges from 2 to 14, comes from `uimm[3:0]`; +`uimm[4]` is ignored. +The out-of-range `uimm[3:0]` values of 0-1 and 15 are mapped to in-range +values by inverting `uimm[3]`. Thus, 0-1 maps to 8-9, and 15 maps to 7. + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. + +[NOTE] +==== +We chose to map out-of-range round numbers to in-range values as this allows the instruction's +behavior to be fully defined for all values of `uimm[4:0]` with minimal extra logic. +==== + +// + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,Sail] +-- +function clause execute (VAESKF2(rnd, vd, vs2)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + // project out-of-range immediates into in-range values + if((unsigned(rnd[3:0]) < 2) | (unsigned(rnd[3:0]) > 14)) then rnd[3] = ~rnd[3] + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let CurrentRoundKey[3:0] : bits(128) = get_velem(vs2, EGW=128, i); + let RoundKeyB[3:0] : bits(32) = get_velem(vd, EGW=128, i); // Previous round key + + let w[0] : bits(32) = if (rnd[0]==1) then + aes_subword_fwd(CurrentRoundKey[3]) XOR RoundKeyB[0]; + else + aes_subword_fwd(aes_rotword(CurrentRoundKey[3])) XOR aes_decode_rcon((rnd>>1) - 1) XOR RoundKeyB[0]; + w[1] : bits(32) = w[0] XOR RoundKeyB[1] + w[2] : bits(32) = w[1] XOR RoundKeyB[2] + w[3] : bits(32) = w[2] XOR RoundKeyB[3] + set_velem(vd, EGW=128, i, w[3:0]); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vaesz, Vector AES round zero]] +==== vaesz.vs + +Synopsis:: +Vector AES round zero encryption/decryption + +Mnemonic:: +vaesz.vs vd, vs2 + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '00111'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101001'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* The `vd` register group overlaps the `vs2` register + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| vd | input | 128 | 4 | 32 | round state +| vs2 | input | 128 | 4 | 32 | round key +| vd | output | 128 | 4 | 32 | new round state +|=== + +Description:: +A round-0 AES block cipher operation is performed. This operation is used for both encryption and decryption. + +There is only a `.vs` form of the instruction. +`Vs2` holds a +scalar element group that is used +as the round key for all of the round state element groups. +The new round state output of each element group is produced by XORing +the round key with each element group of `vd`. + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. + +[NOTE] +==== +This instruction is needed to avoid the need to "splat" a 128-bit vector register group when the round key is the same for +all 128-bit "lanes". Such a splat would typically be implemented with a `vrgather` instruction which would hurt performance +in many implementations. +This instruction only exists in the `.vs` form because the `.vv` form would be identical to the `vxor.vv vd, vs2, vd` instruction. +==== + +// +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,sail] +-- +function clause execute (VAESZ(vs2, vd) = { + if(((vstart%EGS)<>0) | (LMUL*VLEN < EGW)) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let state : bits(128) = get_velem(vd, EGW=128, i); + let rkey : bits(128) = get_velem(vs2, EGW=128, 0); + let ark : bits(128) = state ^ rkey; + set_velem(vd, EGW=128, i, ark); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkned>>, <<zvkng>> + +<<< + +[[insns-vandn, Vector And-Not]] +==== vandn.[vv,vx] + +Synopsis:: +Bitwise And-Not + +Mnemonic:: +vandn.vv vd, vs2, vs1, vm + +vandn.vx vd, vs2, rs1, vm + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '000001'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVX'}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '000001'}, +]} +.... + +Vector-Vector Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs1 | input | Op1 (to be inverted) +| Vs2 | input | Op2 +| Vd | output | Result +|=== + +Vector-Scalar Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Rs1 | input | Op1 (to be inverted) +| Vs2 | input | Op2 +| Vd | output | Result +|=== + +Description:: +A bitwise _and-not_ operation is performed. + +Each bit of `Op1` is inverted and logically ANDed with the corresponding bits in `vs2`. +In the vector-scalar version, `Op1` is the sign-extended or truncated value in scalar +register `rs1`. +In the vector-vector version, `Op1` is `vs1`. + +// This instruction must always be implemented such that its execution latency does not depend +// on the data being operated upon. + +[NOTE] +.Note on necessity of instruction +==== +This instruction is performance-critical to SHA3. Specifically, the Chi step of the FIPS 202 Keccak Permutation. +Emulating it via 2 instructions is expected to have significant performance impact. +The `.vv` form of the instruction is what is needed for SHA3; the `.vx` form was added for completeness. +==== + +[NOTE] +==== +There is no .vi version of this instruction because the same functionality can be achieved by using an inversion +of the immediate value with the `vand.vi` instruction. +==== + +Operation:: +[source,sail] +-- +function clause execute (VANDN(vs2, vs1, vd, suffix)) = { + foreach (i from vstart to vl-1) { + let op1 = match suffix { + "vv" => get_velem(vs1, SEW, i), + "vx" => sext_or_truncate_to_sew(X(vs1)) + }; + let op2 = get_velem(vs2, SEW, i); + set_velem(vd, EEW=SEW, i, ~op1 & op2); + } + RETIRE_SUCCESS +} + +-- + +Included in:: +<<zvbb>>, <<zvkb>>, <<zvkn>>, <<zvknc>>, <<Zvkng>>, <<zvks>> +<<Zvksc>>, <<Zvksg>> + +<<< + +[[insns-vbrev, Vector Reverse Bits in Elements]] +==== vbrev.v + +Synopsis:: +Vector Reverse Bits in Elements + +Mnemonic:: +vbrev.v vd, vs2, vm + +Encoding (Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '01010'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010010'}, +]} +.... + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs2 | input | Input elements +| Vd | output | Elements with bits reversed +|=== + +Description:: +A bit reversal is performed on the bits of each element. + +Operation:: +[source,sail] +-- +function clause execute (VBREV(vs2)) = { + + foreach (i from vstart to vl-1) { + let input = get_velem(vs2, SEW, i); + let output : bits(SEW) = 0; + foreach (i from 0 to SEW-1) + let output[SEW-1-i] = input[i]; + set_velem(vd, SEW, i, output) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>> + +<<< + +[[insns-vbrev8, Vector Reverse Bits in Bytes]] +==== vbrev8.v + +Synopsis:: +Vector Reverse Bits in Bytes + +Mnemonic:: +vbrev8.v vd, vs2, vm + +Encoding (Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '01000'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010010'}, +]} +.... + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs2 | input | Input elements +| Vd | output | Elements with bit-reversed bytes +|=== + +Description:: +A bit reversal is performed on the bits of each byte. + +// This instruction must always be implemented such that its execution latency does not depend +// on the data being operated upon. + +[NOTE] +==== +This instruction is commonly used for GCM when the zvkg extension is not implemented. +This byte-wise instruction is defined for all SEWs to eliminate the need to change SEW when operating on wider elements. +==== + +Operation:: +[source,sail] +-- +function clause execute (VBREV8(vs2)) = { + + foreach (i from vstart to vl-1) { + let input = get_velem(vs2, SEW, i); + let output : bits(SEW) = 0; + foreach (i from 0 to SEW-8 by 8) + let output[i+7..i] = reverse_bits_in_byte(input[i+7..i]); + set_velem(vd, SEW, i, output) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>>, <<zvkb>>, <<zvkn>>, <<zvknc>>, <<Zvkng>>, <<zvks>> +<<Zvksc>>, <<Zvksg>> + +<<< + +[[insns-vclmul, Vector Carry-less Multiply]] +==== vclmul.[vv,vx] + +Synopsis:: +Vector Carry-less Multiply by vector or scalar - returning low half of product. + +Mnemonic:: +vclmul.vv vd, vs2, vs1, vm + +vclmul.vx vd, vs2, rs1, vm + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '001100'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVX'}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '001100'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 64 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs1/Rs1 | input | multiplier +| Vs2 | input | multiplicand +| Vd | output | carry-less product low +|=== + +Description:: +Produces the low half of 128-bit carry-less product. + +Each 64-bit element in the `vs2` vector register is carry-less multiplied by +either each 64-bit element in `vs1` (vector-vector), or the 64-bit value +from integer register `rs1` (vector-scalar). The result is the least +significant 64 bits of the carry-less product. + +[NOTE] +==== +The 64-bit carryless multiply instructions can be used for implementing GCM in the absence of the `zvkg` extension. +We do not make these instructions exclusive as the 64-bit carryless multiply is readily derived from the +instructions in the `zvkg` extension and can have utility in other areas. +Likewise, we treat other SEW values as reserved so as not to preclude +future extensions from using this opcode with different element widths. +For example, a future extension might define an `SEW`=32 version of this instruction to enable `Zve32*` implementations to have +vector carryless multiplication instructions. +==== + +Operation:: +[source,sail] +-- + + +function clause execute (VCLMUL(vs2, vs1, vd, suffix)) = { + + foreach (i from vstart to vl-1) { + let op1 : bits (64) = if suffix =="vv" then get_velem(vs1,i) + else zext_or_truncate_to_sew(X(vs1)); + let op2 : bits (64) = get_velem(vs2,i); + let product : bits (64) = clmul(op1,op2,SEW); + set_velem(vd, i, product); + } + RETIRE_SUCCESS +} + +function clmul(x, y, width) = { + let result : bits(width) = zeros(); + foreach (i from 0 to (width - 1)) { + if y[i] == 1 then result = result ^ (x << i); + } + result +} +-- + +Included in:: +<<zvbc>>, <<zvknc>>, <<zvksc>> + +<<< + +[[insns-vclmulh, Vector Carry-less Multiply Return High Half]] +==== vclmulh.[vv,vx] + +Synopsis:: +Vector Carry-less Multiply by vector or scalar - returning high half of product. + +Mnemonic:: +vclmulh.vv vd, vs2, vs1, vm + +vclmulh.vx vd, vs2, rs1, vm + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '001101'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVX'}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '001101'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 64 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs1 | input | multiplier +| Vs2 | input | multiplicand +| Vd | output | carry-less product high +|=== + +Description:: +Produces the high half of 128-bit carry-less product. + +Each 64-bit element in the `vs2` vector register is carry-less multiplied by +either each 64-bit element in `vs1` (vector-vector), or the 64-bit value +from integer register `rs1` (vector-scalar). The result is the most +significant 64 bits of the carry-less product. + +// This instruction must always be implemented such that its execution latency does not depend +// on the data being operated upon. + +Operation:: +[source,sail] +-- +function clause execute (VCLMULH(vs2, vs1, vd, suffix)) = { + + foreach (i from vstart to vl-1) { + let op1 : bits (64) = if suffix =="vv" then get_velem(vs1,i) + else zext_or_truncate_to_sew(X(vs1)); + let op2 : bits (64) = get_velem(vs2, i); + let product : bits (64) = clmulh(op1, op2, SEW); + set_velem(vd, i, product); + } + RETIRE_SUCCESS +} + +function clmulh(x, y, width) = { + let result : bits(width) = 0; + foreach (i from 1 to (width - 1)) { + if y[i] == 1 then result = result ^ (x >> (width - i)); + } + result +} + +-- + +Included in:: +<<zvbc>>, <<zvknc>>, <<zvksc>> + +<<< + +[[insns-vclz, Vector Count Leading Zeros]] +==== vclz.v + +Synopsis:: +Vector Count Leading Zeros + +Mnemonic:: +vclz.v vd, vs2, vm + +Encoding (Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '01100'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010010'}, +]} +.... + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs2 | input | Input elements +| Vd | output | Count of leading zero bits +|=== + +Description:: +A leading zero count is performed on each element. + +The result for zero-valued inputs is the value SEW. + +Operation:: +[source,sail] +-- +function clause execute (VCLZ(vs2)) = { + + foreach (i from vstart to vl-1) { + let input = get_velem(vs2, SEW, i); + for (j = (SEW - 1); j >= 0; j--) + if [input[j]] == 0b1 then break; + set_velem(vd, SEW, i, SEW - 1 - j) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>> + +[[insns-vcpop, Vector Population Count]] +==== vcpop.v + +Synopsis:: +Count the number of bits set in each element + +Mnemonic:: +vcpop.v vd, vs2, vm + +Encoding (Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '01110'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010010'}, +]} +.... + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs2 | input | Input elements +| Vd | output | Count of bits set +|=== + +Description:: +A population count is performed on each element. + +Operation:: +[source,sail] +-- +function clause execute (VCPOP(vs2)) = { + + foreach (i from vstart to vl-1) { + let input = get_velem(vs2, SEW, i); + let output : bits(SEW) = 0; + for (j = 0; j < SEW; j++) + output = output + input[j]; + set_velem(vd, SEW, i, output) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>> + +[[insns-vctz, Vector Count Trailing Zeros]] +==== vctz.v + +Synopsis:: +Vector Count Trailing Zeros + +Mnemonic:: +vctz.v vd, vs2, vm + +Encoding (Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '01101'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010010'}, +]} +.... + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs2 | input | Input elements +| Vd | output | Count of trailing zero bits +|=== + +Description:: +A trailing zero count is performed on each element. + +// The result for zero-valued inputs is the value SEW. + +Operation:: +[source,sail] +-- +function clause execute (VCTZ(vs2)) = { + + foreach (i from vstart to vl-1) { + let input = get_velem(vs2, SEW, i); + for (j = 0; j < SEW; j++) + if [input[j]] == 0b1 then break; + set_velem(vd, SEW, i, j) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>> + +<<< + +[[insns-vghsh, Vector GHASH Add-Multiply]] +==== vghsh.vv + +Synopsis:: +Vector Add-Multiply over GHASH Galois-Field + +Mnemonic:: +vghsh.vv vd, vs2, vs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101100'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|SEW +|Definition + +| Vd | input | 128 | 4 | 32 | Partial hash (Y~i~) +| Vs1 | input | 128 | 4 | 32 | Cipher text (X~i~) +| Vs2 | input | 128 | 4 | 32 | Hash Subkey (H) +| Vd | output | 128 | 4 | 32 | Partial-hash (Y~i+1~) +|=== + +Description:: +A single "iteration" of the GHASH~H~ algorithm is performed. + +This instruction treats all of the inputs and outputs as 128-bit polynomials and +performs operations over GF[2]. +It produces the next partial hash (Y~i+1~) by adding the current partial +hash (Y~i~) to the cipher text block (X~i~) and then multiplying (over GF(2^128^)) +this sum by the Hash Subkey (H). + +The multiplication over GF(2^128^) is a carryless multiply of two 128-bit polynomials +modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1). + +The operation can be compactly defined as +// Y~i+1~ = (Y~i~ · H) ^ X~i~ +Y~i+1~ = ((Y~i~ ^ X~i~) · H) + +The NIST specification (see <<zvkg>>) orders the coefficients from left to right x~0~x~1~x~2~...x~127~ +for a polynomial x~0~ + x~1~u +x~2~ u^2^ + ... + x~127~u^127^. This can be viewed as a collection of +byte elements in memory with the byte containing the lowest coefficients (i.e., 0,1,2,3,4,5,6,7) +residing at the lowest memory address. Since the bits in the bytes are reversed, +This instruction internally performs bit swaps within bytes to put the bits in the standard ordering +(e.g., 7,6,5,4,3,2,1,0). + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. + +[NOTE] +==== +We are bit-reversing the bytes of inputs and outputs so that the intermediate values are consistent +with the NIST specification. These reversals are inexpensive to implement as they unconditionally +swap bit positions and therefore do not require any logic. +==== + +[NOTE] +==== +Since the same hash subkey `H` will typically be used repeatedly on a given message, +a future extension might define a vector-scalar version of this instruction where +`vs2` is the scalar element group. This would help reduce register pressure when `LMUL` > 1. +==== + +Operation:: +[source,pseudocode] +-- +function clause execute (VGHSH(vs2, vs1, vd)) = { + // operands are input with bits reversed in each byte + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let Y = (get_velem(vd,EGW=128,i)); // current partial-hash + let X = get_velem(vs1,EGW=128,i); // block cipher output + let H = brev8(get_velem(vs2,EGW=128,i)); // Hash subkey + + let Z : bits(128) = 0; + + let S = brev8(Y ^ X); + + for (int bit = 0; bit < 128; bit++) { + if bit_to_bool(S[bit]) + Z ^= H + + bool reduce = bit_to_bool(H[127]); + H = H << 1; // left shift H by 1 + if (reduce) + H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial + } + + let result = brev8(Z); // bit reverse bytes to get back to GCM standard ordering + set_velem(vd, EGW=128, i, result); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkg>>, <<zvkng>>, <<zvksg>> + +<<< + +[[insns-vgmul, Vector GHASH Multiply]] +==== vgmul.vv + +Synopsis:: +Vector Multiply over GHASH Galois-Field + +Mnemonic:: +vgmul.vv vd, vs2 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '10001'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101000'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|SEW +|Definition + +| Vd | input | 128 | 4 | 32 | Multiplier +| Vs2 | input | 128 | 4 | 32 | Multiplicand +| Vd | output | 128 | 4 | 32 | Product +|=== + +Description:: +A GHASH~H~ multiply is performed. + +This instruction treats all of the inputs and outputs as 128-bit polynomials and +performs operations over GF[2]. +It produces the product over GF(2^128^) of the two 128-bit inputs. + +The multiplication over GF(2^128^) is a carryless multiply of two 128-bit polynomials +modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1). + +The NIST specification (see <<zvkg>>) orders the coefficients from left to right x~0~x~1~x~2~...x~127~ +for a polynomial x~0~ + x~1~u +x~2~ u^2^ + ... + x~127~u^127^. This can be viewed as a collection of +byte elements in memory with the byte containing the lowest coefficients (i.e., 0,1,2,3,4,5,6,7) +residing at the lowest memory address. Since the bits in the bytes are reversed, +This instruction internally performs bit swaps within bytes to put the bits in the standard ordering +(e.g., 7,6,5,4,3,2,1,0). + +This instruction must always be implemented such that its execution latency does not depend +on the data being operated upon. + +[NOTE] +==== +We are bit-reversing the bytes of inputs and outputs so that the intermediate values are consistent +with the NIST specification. These reversals are inexpensive to implement as they unconditionally +swap bit positions and therefore do not require any logic. +==== + +[NOTE] +==== +Since the same multiplicand will typically be used repeatedly on a given message, +a future extension might define a vector-scalar version of this instruction where +`vs2` is the scalar element group. This would help reduce register pressure when `LMUL` > 1. +==== + +[NOTE] +==== +This instruction is identical to `vghsh.vv` with vs1=0. +This instruction is often used in GHASH code. In some cases it is followed +by an XOR to perform a multiply-add. Implementations may choose to fuse these +two instructions to improve performance on GHASH code that +doesn't use the add-multiply form of the `vghsh.vv` instruction. +==== + + +Operation:: +[source,pseudocode] +-- +function clause execute (VGMUL(vs2, vs1, vd)) = { + // operands are input with bits reversed in each byte + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let Y = brev8(get_velem(vd,EGW=128,i)); // Multiplier + let H = brev8(get_velem(vs2,EGW=128,i)); // Multiplicand + let Z : bits(128) = 0; + + for (int bit = 0; bit < 128; bit++) { + if bit_to_bool(Y[bit]) + Z ^= H + + bool reduce = bit_to_bool(H[127]); + H = H << 1; // left shift H by 1 + if (reduce) + H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial + } + + + let result = brev8(Z); + set_velem(vd, EGW=128, i, result); + } + RETIRE_SUCCESS + } +} +-- + +Included in:: +<<zvkg>>, <<zvkng>>, <<zvksg>> + +<<< + +[[insns-vrev8, Vector Reverse Bytes]] +==== vrev8.v + +Synopsis:: +Vector Reverse Bytes + +Mnemonic:: +vrev8.v vd, vs2, vm + +Encoding (Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '01001'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010010'}, +]} +.... + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs2 | input | Input elements +| Vd | output | Byte-reversed elements +|=== + +Description:: +A byte reversal is performed on each element of `vs2`, effectively performing an endian swap. + +// This instruction must always be implemented such that its execution latency does not depend +// on the data being operated upon. + +[NOTE] +==== +This element-wise endian swapping is needed for several cryptographic algorithms including SHA2 and SM3. +==== + +Operation:: +[source,sail] +-- +function clause execute (VREV8(vs2)) = { + foreach (i from vstart to vl-1) { + input = get_velem(vs2, SEW, i); + let output : SEW = 0; + let j = SEW - 1; + foreach (k from 0 to (SEW - 8) by 8) { + output[k..(k + 7)] = input[(j - 7)..j]; + j = j - 8; + set_velem(vd, SEW, i, output) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>>, <<zvkb>>, <<zvkn>>, <<zvknc>>, <<Zvkng>>, <<zvks>> +<<Zvksc>>, <<Zvksg>> + +<<< + +[[insns-vrol, Vector Rotate Left]] +==== vrol.[vv,vx] + +Synopsis:: +Vector rotate left by vector/scalar. + +Mnemonic:: +vrol.vv vd, vs2, vs1, vm + +vrol.vx vd, vs2, rs1, vm + + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010101'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVX'}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010101'}, +]} +.... + +Vector-Vector Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs1 | input | Rotate amount +| Vs2 | input | Data +| Vd | output | Rotated data +|=== + +Vector-Scalar Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Rs1 | input | Rotate amount +| Vs2 | input | Data +| Vd | output | Rotated data +|=== + +Description:: +A bitwise left rotation is performed on each element of `vs2` + +The elements in `vs2` are rotated left by the rotate amount specified by either +the corresponding elements of `vs1` (vector-vector), or integer register `rs1` +(vector-scalar). +Only the low log2(`SEW`) bits of the rotate-amount value are used, all other +bits are ignored. + +// This instruction must always be implemented such that its execution latency does not depend +// on the data being operated upon. + +[NOTE] +==== +There is no immediate form of this instruction (i.e., `vrol.vi`) as the same result can be achieved by negating +the rotate amount and using the immediate form of rotate right instruction (i.e., vror.vi). +==== + +Operation:: +[source,sail] +-- +function clause execute (VROL_VV(vs2, vs1, vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=SEW, i, + get_velem(vs2, i) <<< (get_velem(vs1, i) & (SEW-1)) + ) + } + RETIRE_SUCCESS +} + +function clause execute (VROL_VX(vs2, rs1, vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=SEW, i, + get_velem(vs2, i) <<< (X(rs1) & (SEW-1)) + ) + } + RETIRE_SUCCESS +} + +-- + +Included in:: +<<zvbb>>, <<zvkb>>, <<zvkn>>, <<zvknc>>, <<Zvkng>>, <<zvks>> +<<Zvksc>>, <<Zvksg>> + +<<< + +[[insns-vror, Vector Rotate Right]] +==== vror.[vv,vx,vi] + +Synopsis:: +Vector rotate right by vector/scalar/immediate. + +Mnemonic:: +vror.vv vd, vs2, vs1, vm + +vror.vx vd, vs2, rs1, vm + +vror.vi vd, vs2, uimm, vm + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010100'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVX'}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '010100'}, +]} +.... + +Encoding (Vector-Immediate):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVI'}, +{bits: 5, name: 'uimm[4:0]'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 1, name: 'i5'}, +{bits: 5, name: '01010'}, +]} +.... + +Vector-Vector Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs1 | input | Rotate amount +| Vs2 | input | Data +| Vd | output | Rotated data +|=== + +Vector-Scalar/Immediate Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Rs1/imm | input | Rotate amount +| Vs2 | input | Data +| Vd | output | Rotated data +|=== + + +Description:: +A bitwise right rotation is performed on each element of `vs2`. + +The elements in `vs2` are rotated right by the rotate amount specified by either +the corresponding elements of `vs1` (vector-vector), integer register `rs1` +(vector-scalar), or an immediate value (vector-immediate). +Only the low log2(`SEW`) bits of the rotate-amount value are used, all other +bits are ignored. + +// This instruction must always be implemented such that its execution latency does not depend +// on the data being operated upon. + +Operation:: +[source,sail] +-- +function clause execute (VROR_VV(vs2, vs1, vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=SEW, i, + get_velem(vs2, i) >>> (get_velem(vs1, i) & (SEW-1)) + ) + } + RETIRE_SUCCESS +} + +function clause execute (VROR_VX(vs2, rs1, vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=SEW, i, + get_velem(vs2, i) >>> (X(rs1) & (SEW-1)) + ) + } + RETIRE_SUCCESS +} + +function clause execute (VROR_VI(vs2, imm[5:0], vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=SEW, i, + get_velem(vs2, i) >>> (imm[5:0] & (SEW-1)) + ) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>>, <<zvkb>>, <<zvkn>>, <<zvknc>>, <<Zvkng>>, <<zvks>> +<<Zvksc>>, <<Zvksg>> + +<<< + +[[insns-vsha2c, Vector SHA-2 Compression]] +==== vsha2c[hl].vv + +Synopsis:: +Vector SHA-2 two rounds of compression. + +Mnemonic:: +vsha2ch.vv vd, vs2, vs1 + +vsha2cl.vv vd, vs2, vs1 + +Encoding (Vector-Vector) High part:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101110'}, +]} +.... + +Encoding (Vector-Vector) Low part:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101111'}, +]} +.... +Reserved Encodings:: +* `zvknha`: `SEW` is any value other than 32 +* `zvknhb`: `SEW` is any value other than 32 or 64 +* The `vd` register group overlaps with either `vs1` or `vs2` + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 4*SEW | 4 | SEW | current state {c, d, g, h} +| Vs1 | input | 4*SEW | 4 | SEW | MessageSched plus constant[3:0] +| Vs2 | input | 4*SEW | 4 | SEW | current state {a, b, e, f} +| Vd | output | 4*SEW | 4 | SEW | next state {a, b, e, f} +|=== + +Description:: +- `SEW`=32: 2 rounds of SHA-256 compression are performed (`zvknha` and `zvknhb`) +- `SEW`=64: 2 rounds of SHA-512 compression are performed (`zvkhnb`) + +Two words of `vs1` are processed with +the 8 words of current state held in `vd` and `vs1` to perform two +rounds of hash computation producing four words of the +next state. + + +// These instructions take in two SEW words _W1_ and _W0_ which are the next two words of the message +// schedule incremented by the appropriate constant (see +// link:https://doi.org/10.6028/NIST.FIPS.180-4[FIPS PUB 180-4 Secure Hash Standard (SHS)]) +// and eight SEW word variables: _a_, _b_, _c_, _d_, _e_, _f_, _g,_ and _h_. The +// output is the new values of _a, b, e_ and _f_ after performing 2 rounds of the hash +// computation. The new values, _c_, _d_, _g_, and _h_, are equal to the input values for _a_, _b_, // _e_, _f_ respectively. + +// [TIP] +// .Note to software developers +// ==== +// The MessageSchedplus constant input to this instruction is generated by Software +// increment each message schedule word by the corresponding +// round constant as defined in the NIST specification (see <<zvknh>>). +// ==== + +[TIP] +.Note to software developers +==== +The NIST standard (see <<zvknh>>) requires the final hash to be in big-endian byte ordering +within SEW-sized words. Since this instruction treats all words as little-endian, +software needs to perform an endian swap on the final output of this instruction +after all of the message blocks have been processed. +==== + +[NOTE] +==== +The `vsha2ch` version of this instruction uses the two most significant message schedule +words from the element group in `vs1` +while the `vsha2cl` version uses the two least significant message schedule words. +Otherwise, these versions of the instruction are identical. +Having a high and low version of this instruction typically improves performance when +interleaving independent hashing operations (i.e., when hashing several files at once). +==== + +// [TIP] +// .Note to software developers +// ==== +// These instructions take in two SEW words _W1_ and _W0_ which are the next two words of the message +// schedule incremented by the appropriate constant, +// and eight SEW word variables: _a_, _b_, _c_, _d_, _e_, _f_, _g,_ and _h_. The +// output is the new values of _a, b, e_ and _f_ after performing 2 rounds of the hash +// computation. The new values, _c_, _d_, _g_, and _h_, are equal to the input values for _a_, _b_, _e_, _f_ respectively. +// ==== + +// [NOTE] +// ==== +// Between executions this instruction it is helpful to swap the register _specifiers_ for +// `vd` and `vs2`. This is because the first instruction's `vd` next state output +// (_a_, _b_, _e_, _f_) +// becomes the second instruction's `vs2` current state input (_a_, _b_, _e_, _f_). +// Likewise the first instruction's `vs2` input (_a_, _b_, _e_, _f_) "ages" to +// becomes the second instruction's `vd` current state input of (_c_, _d_, _g_, _h_). +// ==== + + +[NOTE] +==== +Preventing overlap between `vd` and `vs1` or `vs2` simplifies implementation with `VLEN < EGW`. +This restriction does not have any coding impact since proper implementation of the algorithm requires +that `vd`, `vs1` and `vs2` each are different registers. +==== + + + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,sail] +-- +function clause execute (VSHA2c(vs2, vs1, vd)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let {a @ b @ e @ f} : bits(4*SEW) = get_velem(vs2, 4*SEW, i); + let {c @ d @ g @ h} : bits(4*SEW) = get_velem(vd, 4*SEW, i); + let MessageShedPlusC[3:0] : bits(4*SEW) = get_velem(vs1, 4*SEW, i); + let {W1, W0} == VSHA2cl ? MessageSchedPlusC[1:0] : MessageSchedPlusC[3:2]; // l vs h difference is the words selected + + let T1 : bits(SEW) = h + sum1(e) + ch(e,f,g) + W0; + let T2 : bits(SEW) = sum0(a) + maj(a,b,c); + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + + + T1 = h + sum1(e) + ch(e,f,g) + W1; + T2 = sum0(a) + maj(a,b,c); + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + set_velem(vd, 4*SEW, i, {a @ b @ e @ f}); + } + RETIRE_SUCCESS + } +} + +function sum0(x) = { + match SEW { + 32 => rotr(x,2) XOR rotr(x,13) XOR rotr(x,22), + 64 => rotr(x,28) XOR rotr(x,34) XOR rotr(x,39) + } +} + +function sum1(x) = { + match SEW { + 32 => rotr(x,6) XOR rotr(x,11) XOR rotr(x,25), + 64 => rotr(x,14) XOR rotr(x,18) XOR rotr(x,41) + } +} + +function ch(x, y, z) = ((x & y) ^ ((~x) & z)) + + +function maj(x, y, z) = ((x & y) ^ (x & z) ^ (y & z)) + +function ROTR(x,n) = (x >> n) | (x << SEW - n) + +-- + +Included in:: +<<zvkn>>, <<zvknc>>, <<zvkng>>, <<zvknh, zvknh[ab]>> + +<<< + +[[insns-vsha2ms, Vector SHA-2 Message Schedule]] +==== vsha2ms.vv + +Synopsis:: +Vector SHA-2 message schedule. + +Mnemonic:: +vsha2ms.vv vd, vs2, vs1 + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101101'}, +]} +.... +Reserved Encodings:: +* `zvknha`: `SEW` is any value other than 32 +* `zvknhb`: `SEW` is any value other than 32 or 64 +* The `vd` register group overlaps with either `vs1` or `vs2` +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 4*SEW | 4 | SEW | Message words {W[3], W[2], W[1], W[0]} +| Vs2 | input | 4*SEW | 4 | SEW | Message words {W[11], W[10], W[9], W[4]} +| Vs1 | input | 4*SEW | 4 | SEW | Message words {W[15], W[14], -, W[12]} +| Vd | output | 4*SEW | 4 | SEW | Message words {W[19], W[18], W[17], W[16]} +|=== + +Description:: +- `SEW`=32: Four rounds of SHA-256 message schedule expansion are performed (`zvknha` and `zvknhb`) +- `SEW`=64: Four rounds of SHA-512 message schedule expansion are performed (`zvkhnb`) + +Eleven of the last 16 `SEW`-sized message-schedule words from `vd` (oldest), `vs2`, +and `vs1` (most recent) are processed to produce the +next 4 message-schedule words. + +[TIP] +.Note to software developers +==== +The first 16 SEW-sized words of the message schedule come from the _message block_ +in big-endian byte order. Since this instruction treats all words as little endian, +software is required to endian swap these words. + +All of the subsequent message schedule words are produced by this instruction and +therefore do not require an endian swap. +==== + +[TIP] +.Note to software developers +==== +Software is required to pack the words into element groups +as shown above in the arguments table. The indices indicate the relate age with +lower indices indicating older words. +==== +// [NOTE] +// ==== +// W~13~ is not used by the instruction. +// ==== + +// Four `SEW` message schedule words are packed into each element group of the +// source and destination registers. From a vector register point of view, +// the message schedule words are packed into the +// element groups from the left to the right with the most significant word on the left +// and the least significant word on the right. + +// `{W~3~, W~2~, W~1~, W~0~} + +// {W~7~, W~6~, W~5~, W~4~} + +// {W~11~, W~10~, W~9~, W~8~} + +// {W~15~, W~14~, W~13~, W~12~}` + +// Since W~5~ through W~8~ are not needed in these calculations, we are able to compact these into +// three element groups +// +// `{W~3~, W~2~, W~1~, W~0~} + +// {W~11~, W~10~, W~9~, W~4~} + +// {W~15~, W~14~, W~13~, W~12~}` + +[TIP] +.Note to software developers +==== +The {W~11~, W~10~, W~9~, W~4~} element group can easily be formed by using a vector +vmerge instruction with the appropriate mask (for example with `vl=4` and `4b0001` +as the 4 mask bits) + +`vmerge.vvm {W~11~, W~10~, W~9~, W~4~}, {W~11~, W~10~, W~9~, W~8~}, {W~7~, W~6~, W~5~, W~4~}, V0` +==== + +// The number of words to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4` + +[NOTE] +==== +Preventing overlap between `vd` and `vs1` or `vs2` simplifies implementation with `VLEN < EGW`. +This restriction does not have any coding impact since proper implementation of the algorithm requires +that `vd`, `vs1` and `vs2` each contain different portions of the message schedule. +==== + +// This instruction is not masked. If any element groups are not to be processed, the _vl_ +// must be set accordingly. It is not possible to skip an intermediary element group. +// `VLMUL` must be at least 1. In typical usage it is expected to be 1. +// There are three source operands: `vd`, `vs1` and `vs2`. The result +// is written to `vd`. + +// NB:: for implementations with `VLEN < EGW`, the minimal `VLMUL` is `EGW / VLEN`. + +// In this code the input elements are numbered from 0 (16 words ago) to 15 (most recent message-schedule word). +// The outputs are numbered from 16 to 19. + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,sail] +-- +function clause execute (VSHA2ms(vs2, vs1, vd)) = { + // SEW32 = SHA-256 + // SEW64 = SHA-512 + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + {W[3] @ W[2] @ W[1] @ W[0]} : bits(EGW) = get_velem(vd, EGW, i); + {W[11] @ W[10] @ W[9] @ W[4]} : bits(EGW) = get_velem(vs2, EGW, i); + {W[15] @ W[14] @ W[13] @ W[12]} : bits(EGW) = get_velem(vs1, EGW, i); + + W[16] = sig1(W[14]) + W[9] + sig0(W[1]) + W[0]; + W[17] = sig1(W[15]) + W[10] + sig0(W[2]) + W[1]; + W[18] = sig1(W[16]) + W[11] + sig0(W[3]) + W[2]; + W[19] = sig1(W[17]) + W[12] + sig0(W[4]) + W[3]; + + set_velem(vd, EGW, i, {W[19] @ W[18] @ W[17] @ W[16]}); + } + RETIRE_SUCCESS + } +} + +function sig0(x) = { + match SEW { + 32 => (ROTR(x,7) XOR ROTR(x,18) XOR SHR(x,3)), + 64 => (ROTR(x,1) XOR ROTR(x,8) XOR SHR(x,7))); + } +} + +function sig1(x) = { + match SEW { + 32 => (ROTR(x,17) XOR ROTR(x,19) XOR SHR(x,10), + 64 => ROTR(x,19) XOR ROTR(x,61) XOR SHR(x,6)); + } +} + +function ROTR(x,n) = (x >> n) | (x << SEW - n) +function SHR (x,n) = x >> n + +-- + +Included in:: + <<zvkn>>, <<zvknc>>, <<zvkng>>, <<zvknh, zvknh[ab]>> + +<<< + +[[insns-vsm3c, SM3 Compression]] +==== vsm3c.vi + +Synopsis:: +Vector SM3 Compression + +Mnemonic:: +vsm3c.vi vd, vs2, uimm + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'uimm'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101011'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* The `vd` register group overlaps with the `vs2` register group + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 256 | 8 | 32 | Current state {H,G.F,E,D,C,B,A} +| uimm | input | - | - | - | round number (rnds) +| Vs2 | input | 256 | 8 | 32 | Message words {-,-,w[5],w[4],-,-,w[1],w[0]} +| Vd | output | 256 | 8 | 32 | Next state {H,G.F,E,D,C,B,A} +|=== + +Description:: +Two rounds of SM3 compression are performed. + +The current state of eight 32-bit words is read in as an element group from `vd`. Eight 32-bit +message words are read in as an element group from `vs2`, although only four of them are used. +All of the 32-bit input words are byte-swapped from big endian to little endian. +These inputs are processed somewhat differently based on the round group (as specified in rnds), +and the next state is generated as an element group of eight 32-bit words. +The next state of eight 32-bit words are generated, +swapped from little endian to big endian, and are returned in +an eight-element group. + +The round number is provided by the 5-bit `rnds` unsigned immediate. Legal values are 0 - 31 +and indicate which group of two rounds are being performed. For example, if rnds=1, +then rounds 2 and 3 are being performed. + +[NOTE] +==== +The round number is used in the rotation of the constant as well to inform the +behavior which differs between rounds 0-15 and rounds 16-63. +==== + +[NOTE] +==== +The endian byte swapping of the input and output words enables us to align with the SM3 +specification without requiring that software perform these swaps. +==== + +[NOTE] +==== +Preventing overlap between `vd` and `vs2` simplifies implementation with `VLEN < EGW`. +This restriction does not have any coding impact since proper implementation of the algorithm requires +that `vd` and `vs2` each are different registers. +==== + +// The elements are listed here in the order they appear in the register, with the most significant +// element on the left, and the least significant on the right. + +// vs2 = {w[7], w[6], w[5], w[4], w[3], w[2], w[1], w[0]} + +// The values consumed by the instruction are + +// vs2 = {- , - , w[5], w[4], -, -, w[1], w[0]} + +// Where the "-" characters are not consumed and are therefore don't cares. + +// This instruction consumes the "W" message schedule inputs and internally generates the "W'" values as needed + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=8`. + +// Likewise, `vstart` must be a multiple of `EGS=8`. + +Operation:: +[source,sail] +-- +function clause execute (VSM3C(rnds, vs2, vd)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + + // load state + let {Hi @ Gi @ Fi @ Ei @ Di @ Ci @ Bi @ Ai} : bits(256) : bits(256) = (get_velem(vd, 256, i)); + //load message schedule + let {u_w7 @ u_w6 @ w5i @ w4i @ u_w3 @ u_w2 @ w1i @ w0i} : bits(256) = (get_velem(vs2, 256, i)); + // u_w inputs are unused + +// perform endian swap +let H : bits(32) = rev8(Hi); +let G : bits(32) = rev8(Gi); +let F : bits(32) = rev8(Fi); +let E : bits(32) = rev8(Ei); +let D : bits(32) = rev8(Di); +let C : bits(32) = rev8(Ci); +let B : bits(32) = rev8(Bi); +let A : bits(32) = rev8(Ai); + +let w5 = : bits(32) rev8(w5i); +let w4 = : bits(32) rev8(w4i); +let w1 = : bits(32) rev8(w1i); +let w0 = : bits(32) rev8(w0i); + +let x0 :bits(32) = w0 ^ w4; // W'[0] +let x1 :bits(32) = w1 ^ w5; // W'[1] + +let j = 2 * rnds; +let ss1 : bits(32) = ROL32(ROL32(A, 12) + E + ROL32(T_j(j), j % 32), 7); +let ss2 : bits(32) = ss1 ^ ROL32(A, 12); +let tt1 : bits(32) = FF_j(A, B, C, j) + D + ss2 + x0; +let tt2 : bits(32) = GG_j(E, F, G, j) + H + ss1 + w0; +D = C; +let : bits(32) C1 = ROL32(B, 9); +B = A; +let A1 : bits(32) = tt1; +H = G; +let G1 : bits(32) = ROL32(F, 19); +F = E; +let E1 : bits(32) = P_0(tt2); + +j = 2 * rnds + 1; +ss1 = ROL32(ROL32(A1, 12) + E1 + ROL32(T_j(j), j % 32), 7); +ss2 = ss1 ^ ROL32(A1, 12); +tt1 = FF_j(A1, B, C1, j) + D + ss2 + x1; +tt2 = GG_j(E1, F, G1, j) + H + ss1 + w1; +D = C1; +let C2 : bits(32) = ROL32(B, 9); +B = A1; +let A2 : bits(32) = tt1; +H = G1; +let G2 = : bits(32) ROL32(F, 19); +F = E1; +let E2 = : bits(32) P_0(tt2); + +// Update the destination register - swap back to big endian +let result : bits(256) = {rev8(G1) @ rev8(G2) @ rev8(E1) @ rev8(E2) @ rev8(C1) @ rev8(C2) @ rev8(A1) @ rev8(A2)}; +set_velem(vd, 256, i, result); + } + +RETIRE_SUCCESS + } +} + +function FF1(X, Y, Z) = ((X) ^ (Y) ^ (Z)) +function FF2(X, Y, Z) = (((X) & (Y)) | ((X) & (Z)) | ((Y) & (Z))) + +function FF_j(X, Y, Z, J) = (((J) <= 15) ? FF1(X, Y, Z) : FF2(X, Y, Z)) + +function GG1(X, Y, Z) = ((X) ^ (Y) ^ (Z)) +function GG2(X, Y, Z) = (((X) & (Y)) | ((~(X)) & (Z))) +. +function GG_j(X, Y, Z, J) = (((J) <= 15) ? GG1(X, Y, Z) : GG2(X, Y, Z)) + +function T_j(J) = (((J) <= 15) ? (0x79CC4519) : (0x7A879D8A)) + +function P_0(X) = ((X) ^ ROL32((X), 9) ^ ROL32((X), 17)) + +-- + +Included in:: +<<zvks>>, <<zvksc>>, <<zvksg>>, <<zvksh>> + +<<< + +[[insns-vsm3me, SM3 Message Expansion]] +==== vsm3me.vv + +Synopsis:: +Vector SM3 Message Expansion + +Mnemonic:: +vsm3me.vv vd, vs2, vs1 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '100000'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* The `vd` register group overlaps with the `vs2` register group. + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vs1 | input | 256 | 8 | 32 | Message words W[7:0] +| Vs2 | input | 256 | 8 | 32 | Message words W[15:8] +| Vd | output | 256 | 8 | 32 | Message words W[23:16] +|=== + +Description:: +Eight rounds of SM3 message expansion are performed. + + +The sixteen most recent 32-bit message words are read in as two +eight-element groups from `vs1` and `vs2`. Each of these words is +swapped from big endian to little endian. +The next eight 32-bit message words are generated, +swapped from little endian to big endian, and are returned in +an eight-element group. + +[NOTE] +==== +The endian byte swapping of the input and output words enables us to align with the SM3 +specification without requiring that software perform these swaps. +==== + +// NOTE +// ==== +// For the best performance, it is recommended that implementations have VLEN≥256. +// When VLEN<EGW, an appropriate LMUL needs to be used by software so that elements from the +// specified register groups can be combined to form the full element group. +// ==== + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=8`. + +// Likewise, `vstart` must be a multiple of `EGS=8`. + +[NOTE] +==== +Preventing overlap between `vd` and `vs2` simplifies implementations with `VLEN < EGW`. +This restriction should not have any coding impact since the algorithm requires these +values to be preserved for generating the next 8 words. +==== + +Operation:: +[source,sail] +-- +function clause execute (VSM3ME(vs2, vs1)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + foreach (i from eg_start to eg_len-1) { + let w[7:0] : bits(256) = get_velem(vs1, 256, i); + let w[15:8] : bits(256) = get_velem(vs2, 256, i); + + // Byte Swap inputs from big-endian to little-endian + let w15 = rev8(w[15]); + let w14 = rev8(w[14]); + let w13 = rev8(w[13]); + let w12 = rev8(w[12]); + let w11 = rev8(w[11]); + let w10 = rev8(w[10]); + let w9 = rev8(w[9]); + let w8 = rev8(w[8]); + let w7 = rev8(w[7]); + let w6 = rev8(w[6]); + let w5 = rev8(w[5]); + let w4 = rev8(w[4]); + let w3 = rev8(w[3]); + let w2 = rev8(w[2]); + let w1 = rev8(w[1]); + let w0 = rev8(w[0]); + + // Note that some of the newly computed words are used in later invocations. + let w[16] = ZVKSH_W(w0 @ w7 @ w13 @ w3 @ w10); + let w[17] = ZVKSH_W(w1 @ w8 @ w14 @ w4 @ w11); + let w[18] = ZVKSH_W(w2 @ w9 @ w15 @ w5 @ w12); + let w[19] = ZVKSH_W(w3 @ w10 @ w16 @ w6 @ w13); + let w[20] = ZVKSH_W(w4 @ w11 @ w17 @ w7 @ w14); + let w[21] = ZVKSH_W(w5 @ w12 @ w18 @ w8 @ w15); + let w[22] = ZVKSH_W(w6 @ w13 @ w19 @ w9 @ w16); + let w[23] = ZVKSH_W(w7 @ w14 @ w20 @ w10 @ w17); + + // Byte swap outputs from little-endian back to big-endian + let w16 : Bits(32) = rev8(W[16]); + let w17 : Bits(32) = rev8(W[17]); + let w18 : Bits(32) = rev8(W[18]); + let w19 : Bits(32) = rev8(W[19]); + let w20 : Bits(32) = rev8(W[20]); + let w21 : Bits(32) = rev8(W[21]); + let w22 : Bits(32) = rev8(W[22]); + let w23 : Bits(32) = rev8(W[23]); + + + // Update the destination register. + set_velem(vd, 256, i, {w23 @ w22 @ w21 @ w20 @ w19 @ w18 @ w17 @ w16}); + } + RETIRE_SUCCESS + } +} + + function P_1(X) ((X) ^ ROL32((X), 15) ^ ROL32((X), 23)) + + function ZVKSH_W(M16, M9, M3, M13, M6) = \ + (P1( (M16) ^ (M9) ^ ROL32((M3), 15) ) ^ ROL32((M13), 7) ^ (M6)) +-- + +Included in:: +<<zvks>>, <<zvksc>>, <<zvksg>>, <<zvksh>> + +<<< + +[[insns-vsm4k, Vector SM4 Key Expansion]] +==== vsm4k.vi + +Synopsis:: +Vector SM4 KeyExpansion + +Mnemonic:: +vsm4k.vi vd, vs2, uimm + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: 'uimm'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '100001'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| uimm | input | - | - | - | Round group (rnd) +| Vs2 | input | 128 | 4 | 32 | Current 4 round keys rK[0:3] +| Vd | output | 128 | 4 | 32 | Next 4 round keys rK'[0:3] +|=== + +Description:: +Four rounds of the SM4 Key Expansion are performed. + +Four round keys are read in as a 4-element group from `vs2`. Each of the next four round keys are generated +by iteratively XORing the last three round keys with a constant that is indexed by the Round Group Number, +performing a byte-wise substitution, and then performing XORs between rotated versions of this value +and the corresponding current round key. + +The Round group number (`rnd`) comes from `uimm[2:0]`; the bits in `uimm[4:3]` are ignored. +Round group numbers range from 0 to 7 and indicate which +group of four round keys are being generated. Round Keys range from 0-31. +For example, if `rnd`=1, then round keys 4, 5, 6, and 7 are being generated. + +// vs2 = {rK[i-4], rK[i-3],rK[i-2], rK[i-1]} // last 4 round keys +// rnd = 0 to 7; // group of 4 rounds +// vd (out) = {rK[i], rK[i+1],rK[i+2], rK[i+3]} // next 4 rounds keys + +// Each of the 32 rounds consumes the last 4 32-bit keys along with a round constant and +// produces the next 32-bit key. + + +[NOTE] +==== +Software needs to generate the initial round keys. This is done by XORing the 128-bit encryption key with +the system parameters: FK[0:3] +==== + +.System Parameters +[%autowidth] +[%header,cols="^2,^2"] +|=== +|FK +|constant + +| 0 | A3B1BAC6 +| 1 | 56AA3350 +| 2 | 677D9197 +| 3 | B27022DC +|=== + + +//// +.System Parameters +[%autowidth] +[%header,cols="^2,^2"] +|=== +|FK +|constant + +| 0 | A3B1BAC6 +| 1 | 56AA3350 +| 2 | 677D9197 +| 3 | B27022DC +|=== +//// + +// MK = {MK[0], MK[1], MK[2], MK[3]} // Encryption Key +// rK[-4,-1] = K[0:3] = MK[0:3] ^ FK[0:3] + + +// The round keys are rK[0] to rK[31] +// B = (rK[i-3] XOR rK[i-2] XOR rK[i-1] XOR CK[round]); + +// S = subBytes(B); + +// rK[i]= rK[i-4] XOR S XOR ROTL13(S) XOR ROTR23(S); + +// +// The round constants and the S-box are described below and can be found at https://datatracker.ietf.org/doc/id/// draft-crypto-sm4-00 + +[NOTE] +==== +Implementation Hint + +The round constants (CK) can be generated on the fly fairly cheaply. +If the bytes of the constants are assigned an incrementing index from 0 to 127, the value of each byte is equal to its index multiplied by 7 modulo 256. +Since the results are all limited to 8 bits, the modulo operation occurs for free: + + B[n] = n + 2n + 4n; + = 8n + ~n + 1; +==== + +// This instruction only returns the generated keys to the same element group as the source. +// If it is desired to have the same key in all vector groups, either the input vector groups +// need to contain the same values, or the output from a particular group needs to be "broadcast" +// to the other groups using an instruction such as vrgather. + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +//// +.System Parameters +[%autowidth] +[%header,cols="^2,^2"] +|=== +|FK +|constant + +| 0 | A3B1BAC6 +| 1 | 56AA3350 +| 2 | 677D9197 +| 3 | B27022DC +|=== +//// + +Operation:: +[source,sail] +-- + +function clause execute (vsm4k(uimm, vs2)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + let B : bits(32) = 0; + let S : bits(32) = 0; + let rk4 : bits(32) = 0; + let rk5 : bits(32) = 0; + let rk6 : bits(32) = 0; + let rk7 : bits(32) = 0; + let rnd : bits(3) = uimm[2:0]; // Lower 3 bits + + foreach (i from eg_start to eg_len-1) { + let (rk3 @ rk2 @ rk1 @ rk0) : bits(128) = get_velem(vs2, 128, i); + + B = rk1 ^ rk2 ^ rk3 ^ ck(4 * rnd); + S = sm4_subword(B); + rk4 = ROUND_KEY(rk0, S); + + B = rk2 ^ rk3 ^ rk4 ^ ck(4 * rnd + 1); + S = sm4_subword(B); + rk5 = ROUND_KEY(rk1, S); + + B = rk3 ^ rk4 ^ rk5 ^ ck(4 * rnd + 2); + S = sm4_subword(B); + rk6 = ROUND_KEY(rk2, S); + + B = rk4 ^ rk5 ^ rk6 ^ ck(4 * rnd + 3); + S = sm4_subword(B); + rk7 = ROUND_KEY(rk3, S); + + // Update the destination register. + set_velem(vd, EGW=128, i, (rk7 @ rk6 @ rk5 @ rk4)); + } + RETIRE_SUCCESS + } +} + +val round_key : bits(32) -> bits(32) +function ROUND_KEY(X, S) = ((X) ^ ((S) ^ ROL32((S), 13) ^ ROL32((S), 23))) + +// SM4 Constant Key (CK) +let ck : list(bits(32)) = [| + 0x00070E15, 0x1C232A31, 0x383F464D, 0x545B6269, + 0x70777E85, 0x8C939AA1, 0xA8AFB6BD, 0xC4CBD2D9, + 0xE0E7EEF5, 0xFC030A11, 0x181F262D, 0x343B4249, + 0x50575E65, 0x6C737A81, 0x888F969D, 0xA4ABB2B9, + 0xC0C7CED5, 0xDCE3EAF1, 0xF8FF060D, 0x141B2229, + 0x30373E45, 0x4C535A61, 0x686F767D, 0x848B9299, + 0xA0A7AEB5, 0xBCC3CAD1, 0xD8DFE6ED, 0xF4FB0209, + 0x10171E25, 0x2C333A41, 0x484F565D, 0x646B7279 + |] +}; + + +-- + +Included in:: +<<zvks>>, <<zvksc>>, <<zvksed>>, <<zvksg>> + +<<< + +[[insns-vsm4r, SM4 Block Cipher Rounds]] +==== vsm4r.[vv,vs] + +Synopsis:: +Vector SM4 Rounds + +Mnemonic:: +vsm4r.vv vd, vs2 + +vsm4r.vs vd, vs2 + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '10000'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101000'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-P'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPMVV'}, +{bits: 5, name: '10000'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: '1'}, +{bits: 6, name: '101001'}, +]} +.... +Reserved Encodings:: +* `SEW` is any value other than 32 +* Only for the `.vs` form: the `vd` register group overlaps the `vs2` register + +Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2,2,2"] +|=== +|Register +|Direction +|EGW +|EGS +|EEW +|Definition + +| Vd | input | 128 | 4 | 32 | Current state X[0:3] +| Vs2 | input | 128 | 4 | 32 | Round keys rk[0:3] +| Vd | output | 128 | 4 | 32 | Next state X'[0:3] +|=== + +Description:: +Four rounds of SM4 Encryption/Decryption are performed. + +The four words of current state are read as a 4-element group from 'vd' +and the round keys are read from either the corresponding 4-element group +in `vs2` (vector-vector form) or the scalar element group in `vs2` +(vector-scalar form). +The next four words of state are generated +by iteratively XORing the last three words of the state with +the corresponding round key, performing +a byte-wise substitution, and then performing XORs between rotated +versions of this value and the corresponding current state. + +[NOTE] +==== +In SM4, encryption and decryption are identical except that decryption consumes the round keys in the reverse order. +==== + +[NOTE] +==== +For the first four rounds of encryption, the _current state_ is the plain text. +For the first four rounds of decryption, the _current state_ is the cipher text. +For all subsequent rounds, the _current state_ is the _next state_ from the +previous four rounds. +==== + +// The number of element groups to be processed is `vl`/`EGS`. +// `vl` must be set to the number of `SEW=32` elements to be processed and +// therefore must be a multiple of `EGS=4`. + +// Likewise, `vstart` must be a multiple of `EGS=4`. + +Operation:: +[source,pseudocode] +-- +function clause execute (VSM4R(vd, vs2)) = { + if(LMUL*VLEN < EGW) then { + handle_illegal(); // illegal instruction exception + RETIRE_FAIL + } else { + + eg_len = (vl/EGS) + eg_start = (vstart/EGS) + + let B : bits(32) = 0; + let S : bits(32) = 0; + let rk0 : bits(32) = 0; + let rk1 : bits(32) = 0; + let rk2 : bits(32) = 0; + let rk3 : bits(32) = 0; + let x0 : bits(32) = 0; + let x1 : bits(32) = 0; + let x2 : bits(32) = 0; + let x3 : bits(32) = 0; + let x4 : bits(32) = 0; + let x5 : bits(32) = 0; + let x6 : bits(32) = 0; + let x7 : bits(32) = 0; + + let keyelem : bits(32) = 0; + + foreach (i from eg_start to eg_len-1) { + keyelem = if suffix == "vv" then i else 0; + {rk3 @ rk2 @ rk1 @ rk0} : bits(128) = get_velem(vs2, EGW=128, keyelem); + {x3 @ x2 @ x1 @ x0} : bits(128) = get_velem(vd, EGW=128, i); + + B = x1 ^ x2 ^ x3 ^ rk0; + S = sm4_subword(B); + x4 = sm4_round(x0, S); + + B = x2 ^ x3 ^ x4 ^ rk1; + S = sm4_subword(B); + x5= sm4_round(x1, S); + + B = x3 ^ x4 ^ x5 ^ rk2; + S = sm4_subword(B); + x6 = sm4_round(x2, S); + + B = x4 ^ x5 ^ x6 ^ rk3; + S = sm4_subword(B); + x7 = sm4_round(x3, S); + + set_velem(vd, EGW=128, i, (x7 @ x6 @ x5 @ x4)); + + } + RETIRE_SUCCESS + } +} + +val sm4_round : bits(32) -> bits(32) +function sm4_round(X, S) = \ + ((X) ^ ((S) ^ ROL32((S), 2) ^ ROL32((S), 10) ^ ROL32((S), 18) ^ ROL32((S), 24))) + +-- + +Included in:: +<<zvks>>, <<zvksc>>, <<zvksed>>, <<zvksg>> + +<<< + +[[insns-vwsll, Vector Widening Shift Left Logical]] +==== vwsll.[vv,vx,vi] + +Synopsis:: +Vector widening shift left logical by vector/scalar/immediate. + +Mnemonic:: +vwsll.vv vd, vs2, vs1, vm + +vwsll.vx vd, vs2, rs1, vm + +vwsll.vi vd, vs2, uimm, vm + +Encoding (Vector-Vector):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVV'}, +{bits: 5, name: 'vs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '110101'}, +]} +.... + +Encoding (Vector-Scalar):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVX'}, +{bits: 5, name: 'rs1'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '110101'}, +]} +.... + +Encoding (Vector-Immediate):: +[wavedrom, , svg] +.... +{reg:[ +{bits: 7, name: 'OP-V'}, +{bits: 5, name: 'vd'}, +{bits: 3, name: 'OPIVI'}, +{bits: 5, name: 'uimm[4:0]'}, +{bits: 5, name: 'vs2'}, +{bits: 1, name: 'vm'}, +{bits: 6, name: '110101'}, +]} +.... + +Vector-Vector Arguments:: + +[%autowidth] +[%header,cols="4,2,2"] +|=== +|Register +|Direction +|Definition + +| Vs1 | input | Shift amount +| Vs2 | input | Data +| Vd | output | Shifted data +|=== + +Vector-Scalar/Immediate Arguments:: + +[%autowidth] +[%header,cols="4,2,2,2"] +|=== +|Register +|Direction +|EEW +|Definition + +| Rs1/imm | input | SEW | Shift amount +| Vs2 | input | SEW | Data +| Vd | output | 2*SEW | Shifted data +|=== + + +Description:: +A widening logical shift left is performed on each element of `vs2`. + +The elements in `vs2` are zero-extended to 2*`SEW` bits, then shifted left +by the shift amount specified by either +the corresponding elements of `vs1` (vector-vector), integer register `rs1` +(vector-scalar), or an immediate value (vector-immediate). +Only the low log2(2*`SEW`) bits of the shift-amount value are used, all other +bits are ignored. + +Operation:: +[source,sail] +-- +function clause execute (VWSLL_VV(vs2, vs1, vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=2*SEW, i, + get_velem(vs2, i) << (get_velem(vs1, i) & ((2*SEW)-1)) + ) + } + RETIRE_SUCCESS +} + +function clause execute (VWSLL_VX(vs2, rs1, vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=2*SEW, i, + get_velem(vs2, i) << (X(rs1) & ((2*SEW)-1)) + ) + } + RETIRE_SUCCESS +} + +function clause execute (VWSLL_VI(vs2, uimm[4:0], vd)) = { + foreach (i from vstart to vl - 1) { + set_velem(vd, EEW=2*SEW, i, + get_velem(vs2, i) << (uimm[4:0] & ((2*SEW)-1)) + ) + } + RETIRE_SUCCESS +} +-- + +Included in:: +<<zvbb>> + +<<< + + +[[crypto_vector_instructions]] +=== Crypto Vector Cryptographic Instructions + +OP-P (0x77) +Crypto Vector instructions except Zvbb and Zvbc + +// [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +[cols="4,1,1,1,1,4,1,1,1,4,1,1,1"] +|=== +5+^|Integer 4+^|Integer 4+^| FP + +| funct3 | | | | | funct3 | | | | funct3 | | | +| OPIVV |V| | | | OPMVV |V| | | OPFVV |V| | +| OPIVX | |X| | | OPMVX | |X| | OPFVF | |F| +| OPIVI | | |I| | | | | | | | | +|=== + +// [cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +[cols="6,1,1,1,1,6,1,1,6,6,1,1,1"] + +|=== +5+^| funct6 4+^| funct6 4+^| funct6 + +|100000||||| 100000 |V| | vsm3me | 100000 | | | +| 100001 | | | | | 100001 |V| | vsm4k.vi | 100001 | | | +| 100010 | | | | | 100010 |V| | vaeskf1.vi | 100010 | | | +| 100011 | | | | | 100011 | | | | 100011 | | | +| 100100 | | | | | 100100 | | | | 100100 | | | +| 100101 | | | | | 100101 | | | | 100101 | | | +| 100110 | | | | | 100110 | | | | 100110 | | | +| 100111 | | | | | 100111 | | | | 100111 | | | +| | | | | | | | | | | | | +| 101000 | | | | | 101000 |V| | *VAES.vv* | 101000 | | | +| 101001 | | | | | 101001 |V| | *VAES.vs* | 101001 | | | +| 101010 | | | | | 101010 |V| | vaeskf2.vi | 101010 | | | +| 101011 | | | | | 101011 |V| | vsm3c.vi | 101011 | | | +| 101100 | | | | | 101100 |V| | vghsh | 101100 | | | +| 101101 | | | | | 101101 |V| | vsha2ms | 101101 | | | +| 101110 | | | | | 101110 |V| | vsha2ch | 101110 | | | +| 101111 | | | | | 101111 |V| | vsha2cl | 101111 | | | +|=== + +<<< + +.VAES.vv and VAES.vs encoding space +[cols="2,14"] +|=== +|vs1| + +| 00000 | vaesdm +| 00001 | vaesdf +| 00010 | vaesem +| 00011 | vaesef +| 00111 | vaesz +| 10000 | vsm4r +| 10001 | vgmul +|=== + +[[crypto_vector_instructions_Zvbb_Zvbc]] +=== Vector Bitmanip and Carryless Multiply Instructions + +OP-V (0x57) +*Zvbb*, *Zvkb*, and *Zvbc* Vector instructions *in bold* +//[%auto-width] +[%autowidth,cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| Integer 4+| Integer 4+| FP + +| funct3 | | | | | funct3 | | | | funct3 | | | +| OPIVV |V| | | | OPMVV |V| | | OPFVV |V| | +| OPIVX | |X| | | OPMVX | |X| | OPFVF | |F| +| OPIVI | | |I| | | | | | | | | +|=== + +//[%auto-width] +[%autowidth,cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 000000 |V|X|I| vadd | 000000 |V| | vredsum | 000000 |V|F| vfadd +| 000001 |V|X| | *vandn* | 000001 |V| | vredand | 000001 |V| | vfredusum +| 000010 |V|X| | vsub | 000010 |V| | vredor | 000010 |V|F| vfsub +| 000011 | |X|I| vrsub | 000011 |V| | vredxor | 000011 |V| | vfredosum +| 000100 |V|X| | vminu | 000100 |V| | vredminu | 000100 |V|F| vfmin +| 000101 |V|X| | vmin | 000101 |V| | vredmin | 000101 |V| | vfredmin +| 000110 |V|X| | vmaxu | 000110 |V| | vredmaxu | 000110 |V|F| vfmax +| 000111 |V|X| | vmax | 000111 |V| | vredmax | 000111 |V| | vfredmax +| 001000 | | | | | 001000 |V|X| vaaddu | 001000 |V|F| vfsgnj +| 001001 |V|X|I| vand | 001001 |V|X| vaadd | 001001 |V|F| vfsgnjn +| 001010 |V|X|I| vor | 001010 |V|X| vasubu | 001010 |V|F| vfsgnjx +| 001011 |V|X|I| vxor | 001011 |V|X| vasub | 001011 | | | +| 001100 |V|X|I| vrgather | 001100 |V|X| *vclmul* | 001100 | | | +| 001101 | | | | | 001101 |V|X| *vclmulh* | 001101 | | | +| 001110 | |X|I| vslideup | 001110 | |X| vslide1up | 001110 | |F| vfslide1up +| 001110 |V| | | vrgatherei16| | | | | | | | +| 001111 | |X|I| vslidedown | 001111 | |X| vslide1down | 001111 | |F| vfslide1down +|=== + +[%autowidth,cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 010000 |V|X|I| vadc | 010000 |V| | VWXUNARY0 | 010000 |V| | VWFUNARY0 +| | | | | | 010000 | |X| VRXUNARY0 | 010000 | |F| VRFUNARY0 +| 010001 |V|X|I| vmadc | 010001 | | | | 010001 | | | +| 010010 |V|X| | vsbc | 010010 |V| | VXUNARY0 | 010010 |V| | VFUNARY0 +| 010011 |V|X| | vmsbc | 010011 | | | | 010011 |V| | VFUNARY1 +| 010100 |V|X| | *vror* | 010100 |V| | VMUNARY0 | 010100 | | | +| 010101 |V|X| | *vrol* | 010101 | | | | 010101 | | | +| 01010x | | |I| *vror* | | | | | | | | +| 010110 | | | | | 010110 | | | | 010110 | | | +| 010111 |V|X|I| vmerge/vmv | 010111 |V| | vcompress | 010111 | |F| vfmerge/vfmv +| 011000 |V|X|I| vmseq | 011000 |V| | vmandn | 011000 |V|F| vmfeq +| 011001 |V|X|I| vmsne | 011001 |V| | vmand | 011001 |V|F| vmfle +| 011010 |V|X| | vmsltu | 011010 |V| | vmor | 011010 | | | +| 011011 |V|X| | vmslt | 011011 |V| | vmxor | 011011 |V|F| vmflt +| 011100 |V|X|I| vmsleu | 011100 |V| | vmorn | 011100 |V|F| vmfne +| 011101 |V|X|I| vmsle | 011101 |V| | vmnand | 011101 | |F| vmfgt +| 011110 | |X|I| vmsgtu | 011110 |V| | vmnor | 011110 | | | +| 011111 | |X|I| vmsgt | 011111 |V| | vmxnor | 011111 | |F| vmfge +|=== + +[%autowidth,cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 100000 |V|X|I| vsaddu | 100000 |V|X| vdivu | 100000 |V|F| vfdiv +| 100001 |V|X|I| vsadd | 100001 |V|X| vdiv | 100001 | |F| vfrdiv +| 100010 |V|X| | vssubu | 100010 |V|X| vremu | 100010 | | | +| 100011 |V|X| | vssub | 100011 |V|X| vrem | 100011 | | | +| 100100 | | | | | 100100 |V|X| vmulhu | 100100 |V|F| vfmul +| 100101 |V|X|I| vsll | 100101 |V|X| vmul | 100101 | | | +| 100110 | | | | | 100110 |V|X| vmulhsu | 100110 | | | +| 100111 |V|X| | vsmul | 100111 |V|X| vmulh | 100111 | |F| vfrsub +| | | |I| vmv<nr>r | | | | | | | | +| 101000 |V|X|I| vsrl | 101000 | | | | 101000 |V|F| vfmadd +| 101001 |V|X|I| vsra | 101001 |V|X| vmadd | 101001 |V|F| vfnmadd +| 101010 |V|X|I| vssrl | 101010 | | | | 101010 |V|F| vfmsub +| 101011 |V|X|I| vssra | 101011 |V|X| vnmsub | 101011 |V|F| vfnmsub +| 101100 |V|X|I| vnsrl | 101100 | | | | 101100 |V|F| vfmacc +| 101101 |V|X|I| vnsra | 101101 |V|X| vmacc | 101101 |V|F| vfnmacc +| 101110 |V|X|I| vnclipu | 101110 | | | | 101110 |V|F| vfmsac +| 101111 |V|X|I| vnclip | 101111 |V|X| vnmsac | 101111 |V|F| vfnmsac +|=== + +[%autowidth,cols="4,1,1,1,8,4,1,1,8,4,1,1,8"] +|=== +5+| funct6 4+| funct6 4+| funct6 + +| 110000 |V| | | vwredsumu | 110000 |V|X| vwaddu | 110000 |V|F| vfwadd +| 110001 |V| | | vwredsum | 110001 |V|X| vwadd | 110001 |V| | vfwredusum +| 110010 | | | | | 110010 |V|X| vwsubu | 110010 |V|F| vfwsub +| 110011 | | | | | 110011 |V|X| vwsub | 110011 |V| | vfwredosum +| 110100 | | | | | 110100 |V|X| vwaddu.w | 110100 |V|F| vfwadd.w +| 110101 |V|X|I| *vwsll* | 110101 |V|X| vwadd.w | 110101 | | | +| 110110 | | | | | 110110 |V|X| vwsubu.w | 110110 |V|F| vfwsub.w +| 110111 | | | | | 110111 |V|X| vwsub.w | 110111 | | | +| 111000 | | | | | 111000 |V|X| vwmulu | 111000 |V|F| vfwmul +| 111001 | | | | | 111001 | | | | 111001 | | | +| 111010 | | | | | 111010 |V|X| vwmulsu | 111010 | | | +| 111011 | | | | | 111011 |V|X| vwmul | 111011 | | | +| 111100 | | | | | 111100 |V|X| vwmaccu | 111100 |V|F| vfwmacc +| 111101 | | | | | 111101 |V|X| vwmacc | 111101 |V|F| vfwnmacc +| 111110 | | | | | 111110 | |X| vwmaccus | 111110 |V|F| vfwmsac +| 111111 | | | | | 111111 |V|X| vwmaccsu | 111111 |V|F| vfwnmsac +|=== + +<<< + +//[%auto-width] +.VXUNARY0 encoding space +[%autowidth,cols="2,14"] +|=== +| vs1 | + +| 00010 | vzext.vf8 +| 00011 | vsext.vf8 +| 00100 | vzext.vf4 +| 00101 | vsext.vf4 +| 00110 | vzext.vf2 +| 00111 | vsext.vf2 +| 01000 | *vbrev8* +| 01001 | *vrev8* +| 01010 | *vbrev* +| 01100 | *vclz* +| 01101 | *vctz* +| 01110 | *vcpop* + +|=== + +[[crypto_vector_appx_sail]] +=== Supporting Sail Code + +This section contains the supporting Sail code referenced by the +instruction descriptions throughout the specification. +The +link:https://github.com/rems-project/sail/blob/sail2/manual.pdf[Sail Manual] +is recommended reading in order to best understand the supporting code. + +[source,sail] +---- +/* Auxiliary function for performing GF multiplicaiton */ +val xt2 : bits(8) -> bits(8) +function xt2(x) = { + (x << 1) ^ (if bit_to_bool(x[7]) then 0x1b else 0x00) +} + +val xt3 : bits(8) -> bits(8) +function xt3(x) = x ^ xt2(x) + +/* Multiply 8-bit field element by 4-bit value for AES MixCols step */ +val gfmul : (bits(8), bits(4)) -> bits(8) +function gfmul( x, y) = { + (if bit_to_bool(y[0]) then x else 0x00) ^ + (if bit_to_bool(y[1]) then xt2( x) else 0x00) ^ + (if bit_to_bool(y[2]) then xt2(xt2( x)) else 0x00) ^ + (if bit_to_bool(y[3]) then xt2(xt2(xt2(x))) else 0x00) +} + +/* 8-bit to 32-bit partial AES Mix Colum - forwards */ +val aes_mixcolumn_byte_fwd : bits(8) -> bits(32) +function aes_mixcolumn_byte_fwd(so) = { + gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2) +} + +/* 8-bit to 32-bit partial AES Mix Colum - inverse*/ +val aes_mixcolumn_byte_inv : bits(8) -> bits(32) +function aes_mixcolumn_byte_inv(so) = { + gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe) +} + +/* 32-bit to 32-bit AES forward MixColumn */ +val aes_mixcolumn_fwd : bits(32) -> bits(32) +function aes_mixcolumn_fwd(x) = { + let s0 : bits (8) = x[ 7.. 0]; + let s1 : bits (8) = x[15.. 8]; + let s2 : bits (8) = x[23..16]; + let s3 : bits (8) = x[31..24]; + let b0 : bits (8) = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3); + let b1 : bits (8) = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3); + let b2 : bits (8) = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3); + let b3 : bits (8) = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3); + b3 @ b2 @ b1 @ b0 /* Return value */ +} + +/* 32-bit to 32-bit AES inverse MixColumn */ +val aes_mixcolumn_inv : bits(32) -> bits(32) +function aes_mixcolumn_inv(x) = { + let s0 : bits (8) = x[ 7.. 0]; + let s1 : bits (8) = x[15.. 8]; + let s2 : bits (8) = x[23..16]; + let s3 : bits (8) = x[31..24]; + let b0 : bits (8) = gfmul(s0, 0xE) ^ gfmul(s1, 0xB) ^ gfmul(s2, 0xD) ^ gfmul(s3, 0x9); + let b1 : bits (8) = gfmul(s0, 0x9) ^ gfmul(s1, 0xE) ^ gfmul(s2, 0xB) ^ gfmul(s3, 0xD); + let b2 : bits (8) = gfmul(s0, 0xD) ^ gfmul(s1, 0x9) ^ gfmul(s2, 0xE) ^ gfmul(s3, 0xB); + let b3 : bits (8) = gfmul(s0, 0xB) ^ gfmul(s1, 0xD) ^ gfmul(s2, 0x9) ^ gfmul(s3, 0xE); + b3 @ b2 @ b1 @ b0 /* Return value */ +} + +val aes_decode_rcon : bits(4) -> bits(32) +function aes_decode_rcon(r) = { + match r { + 0x0 => 0x00000001, + 0x1 => 0x00000002, + 0x2 => 0x00000004, + 0x3 => 0x00000008, + 0x4 => 0x00000010, + 0x5 => 0x00000020, + 0x6 => 0x00000040, + 0x7 => 0x00000080, + 0x8 => 0x0000001b, + 0x9 => 0x00000036, + 0xA => 0x00000000, + 0xB => 0x00000000, + 0xC => 0x00000000, + 0xD => 0x00000000, + 0xE => 0x00000000, + 0xF => 0x00000000 + } +} + +/* SM4 SBox - only one sbox for forwards and inverse */ +let sm4_sbox_table : list(bits(8)) = [| +0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, +0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, +0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, +0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, 0xE4, 0xB3, 0x1C, 0xA9, +0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, 0x47, +0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, +0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, +0x4B, 0x70, 0x56, 0x9D, 0x35, 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, +0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, +0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, +0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, +0xA1, 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, +0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, +0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, +0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, 0x8D, 0x1B, 0xAF, +0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, +0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, +0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, +0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, +0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48 +|] + +let aes_sbox_fwd_table : list(bits(8)) = [| +0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, +0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, +0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, +0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, +0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, +0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, +0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, +0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, +0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, +0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, +0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, +0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, +0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, +0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, +0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, +0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, +0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, +0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, +0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, +0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 +|] + +let aes_sbox_inv_table : list(bits(8)) = [| +0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, +0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, +0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, +0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, +0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, +0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, +0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, +0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, +0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, +0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, +0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, +0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, +0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, +0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, +0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, +0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, +0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, +0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, +0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, +0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d +|] + +/* Lookup function - takes an index and a list, and retrieves the + * x'th element of that list. + */ +val sbox_lookup : (bits(8), list(bits(8))) -> bits(8) +function sbox_lookup(x, table) = { + match (x, table) { + (0x00, t0::tn) => t0, + ( y, t0::tn) => sbox_lookup(x - 0x01, tn) + } +} + +/* Easy function to perform a forward AES SBox operation on 1 byte. */ +val aes_sbox_fwd : bits(8) -> bits(8) +function aes_sbox_fwd(x) = sbox_lookup(x, aes_sbox_fwd_table) + +/* Easy function to perform an inverse AES SBox operation on 1 byte. */ +val aes_sbox_inv : bits(8) -> bits(8) +function aes_sbox_inv(x) = sbox_lookup(x, aes_sbox_inv_table) + +/* AES SubWord function used in the key expansion + * - Applies the forward sbox to each byte in the input word. + */ +val aes_subword_fwd : bits(32) -> bits(32) +function aes_subword_fwd(x) = { + aes_sbox_fwd(x[31..24]) @ + aes_sbox_fwd(x[23..16]) @ + aes_sbox_fwd(x[15.. 8]) @ + aes_sbox_fwd(x[ 7.. 0]) +} + +/* AES Inverse SubWord function. + * - Applies the inverse sbox to each byte in the input word. + */ +val aes_subword_inv : bits(32) -> bits(32) +function aes_subword_inv(x) = { + aes_sbox_inv(x[31..24]) @ + aes_sbox_inv(x[23..16]) @ + aes_sbox_inv(x[15.. 8]) @ + aes_sbox_inv(x[ 7.. 0]) +} + +/* Easy function to perform an SM4 SBox operation on 1 byte. */ +val sm4_sbox : bits(8) -> bits(8) +function sm4_sbox(x) = sbox_lookup(x, sm4_sbox_table) + +val aes_get_column : (bits(128), nat) -> bits(32) +function aes_get_column(state,c) = (state >> (to_bits(7, 32 * c)))[31..0] + +/* 64-bit to 64-bit function which applies the AES forward sbox to each byte + * in a 64-bit word. + */ +val aes_apply_fwd_sbox_to_each_byte : bits(64) -> bits(64) +function aes_apply_fwd_sbox_to_each_byte(x) = { + aes_sbox_fwd(x[63..56]) @ + aes_sbox_fwd(x[55..48]) @ + aes_sbox_fwd(x[47..40]) @ + aes_sbox_fwd(x[39..32]) @ + aes_sbox_fwd(x[31..24]) @ + aes_sbox_fwd(x[23..16]) @ + aes_sbox_fwd(x[15.. 8]) @ + aes_sbox_fwd(x[ 7.. 0]) +} + +/* 64-bit to 64-bit function which applies the AES inverse sbox to each byte + * in a 64-bit word. + */ +val aes_apply_inv_sbox_to_each_byte : bits(64) -> bits(64) +function aes_apply_inv_sbox_to_each_byte(x) = { + aes_sbox_inv(x[63..56]) @ + aes_sbox_inv(x[55..48]) @ + aes_sbox_inv(x[47..40]) @ + aes_sbox_inv(x[39..32]) @ + aes_sbox_inv(x[31..24]) @ + aes_sbox_inv(x[23..16]) @ + aes_sbox_inv(x[15.. 8]) @ + aes_sbox_inv(x[ 7.. 0]) +} + +/* + * AES full-round transformation functions. + */ + +val getbyte : (bits(64), int) -> bits(8) +function getbyte(x, i) = (x >> to_bits(6, i * 8))[7..0] + +val aes_rv64_shiftrows_fwd : (bits(64), bits(64)) -> bits(64) +function aes_rv64_shiftrows_fwd(rs2, rs1) = { + getbyte(rs1, 3) @ + getbyte(rs2, 6) @ + getbyte(rs2, 1) @ + getbyte(rs1, 4) @ + getbyte(rs2, 7) @ + getbyte(rs2, 2) @ + getbyte(rs1, 5) @ + getbyte(rs1, 0) +} + +val aes_rv64_shiftrows_inv : (bits(64), bits(64)) -> bits(64) +function aes_rv64_shiftrows_inv(rs2, rs1) = { + getbyte(rs2, 3) @ + getbyte(rs2, 6) @ + getbyte(rs1, 1) @ + getbyte(rs1, 4) @ + getbyte(rs1, 7) @ + getbyte(rs2, 2) @ + getbyte(rs2, 5) @ + getbyte(rs1, 0) +} + +/* 128-bit to 128-bit implementation of the forward AES ShiftRows transform. + * Byte 0 of state is input column 0, bits 7..0. + * Byte 5 of state is input column 1, bits 15..8. + */ +val aes_shift_rows_fwd : bits(128) -> bits(128) +function aes_shift_rows_fwd(x) = { + let ic3 : bits(32) = aes_get_column(x, 3); + let ic2 : bits(32) = aes_get_column(x, 2); + let ic1 : bits(32) = aes_get_column(x, 1); + let ic0 : bits(32) = aes_get_column(x, 0); + let oc0 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic1[15.. 8] @ ic0[ 7.. 0]; + let oc1 : bits(32) = ic0[31..24] @ ic3[23..16] @ ic2[15.. 8] @ ic1[ 7.. 0]; + let oc2 : bits(32) = ic1[31..24] @ ic0[23..16] @ ic3[15.. 8] @ ic2[ 7.. 0]; + let oc3 : bits(32) = ic2[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic3[ 7.. 0]; + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* 128-bit to 128-bit implementation of the inverse AES ShiftRows transform. + * Byte 0 of state is input column 0, bits 7..0. + * Byte 5 of state is input column 1, bits 15..8. + */ +val aes_shift_rows_inv : bits(128) -> bits(128) +function aes_shift_rows_inv(x) = { + let ic3 : bits(32) = aes_get_column(x, 3); /* In column 3 */ + let ic2 : bits(32) = aes_get_column(x, 2); + let ic1 : bits(32) = aes_get_column(x, 1); + let ic0 : bits(32) = aes_get_column(x, 0); + let oc0 : bits(32) = ic1[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0]; + let oc1 : bits(32) = ic2[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic1[ 7.. 0]; + let oc2 : bits(32) = ic3[31..24] @ ic0[23..16] @ ic1[15.. 8] @ ic2[ 7.. 0]; + let oc3 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic2[15.. 8] @ ic3[ 7.. 0]; + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the forward sub-bytes step of AES to a 128-bit vector + * representation of its state. + */ +val aes_subbytes_fwd : bits(128) -> bits(128) +function aes_subbytes_fwd(x) = { + let oc0 : bits(32) = aes_subword_fwd(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_subword_fwd(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_subword_fwd(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_subword_fwd(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the inverse sub-bytes step of AES to a 128-bit vector + * representation of its state. + */ +val aes_subbytes_inv : bits(128) -> bits(128) +function aes_subbytes_inv(x) = { + let oc0 : bits(32) = aes_subword_inv(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_subword_inv(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_subword_inv(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_subword_inv(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the forward MixColumns step of AES to a 128-bit vector + * representation of its state. + */ +val aes_mixcolumns_fwd : bits(128) -> bits(128) +function aes_mixcolumns_fwd(x) = { + let oc0 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Applies the inverse MixColumns step of AES to a 128-bit vector + * representation of its state. + */ +val aes_mixcolumns_inv : bits(128) -> bits(128) +function aes_mixcolumns_inv(x) = { + let oc0 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 0)); + let oc1 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 1)); + let oc2 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 2)); + let oc3 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 3)); + (oc3 @ oc2 @ oc1 @ oc0) /* Return value */ +} + +/* Performs the word rotation for AES key schedule +*/ + +val aes_rotword : bits(32) -> bits(32) +function aes_rotword(x) = { + let a0 : bits (8) = x[ 7.. 0]; + let a1 : bits (8) = x[15.. 8]; + let a2 : bits (8) = x[23..16]; + let a3 : bits (8) = x[31..24]; + (a0 @ a3 @ a2 @ a1) /* Return Value */ +} + +val brev : bits(SEW) -> bits(SEW) +function brev(x) = { + let output : bits(SEW) = 0; + foreach (i from 0 to SEW-8 by 8) + output[i+7..i] = reverse_bits_in_byte(input[i+7..i]); + output /* Return Value */ +} + +val reverse_bits_in_byte : bits(8) -> bits(8) +function reverse_bits_in_byte(x) = { + let output : bits(8) = 0; + foreach (i from 0 to 7) + output[i] = x[7-i]); + output /* Return Value */ +} + +val rev8 : bits(SEW) -> bits(SEW) +function rev8(x) = { // endian swap + let output : bits(SEW) = 0; + let j = SEW - 1; + foreach (k from 0 to (SEW - 8) by 8) { + output[k..(k + 7)] = x[(j - 7)..j]; + j = j - 8; + output /* Return Value */ + } + RETIRE_SUCCESS + + +val rol32 : bits(32) -> bits(32) +function ROL32(x,n) = (X << N) | (X >> (32 - N)) + +val sm4_subword : bits(32) -> bits(32) +function sm4_subword(x) = { + sm4_sbox(x[31..24]) @ + sm4_sbox(x[23..16]) @ + sm4_sbox(x[15.. 8]) @ + sm4_sbox(x[ 7.. 0]) +} +---- diff --git a/src/vector-examples.adoc b/src/vector-examples.adoc new file mode 100644 index 0000000..9e54acd --- /dev/null +++ b/src/vector-examples.adoc @@ -0,0 +1,125 @@ +[appendix] +== Vector Assembly Code Examples + +The following are provided as non-normative text to help explain the vector ISA. + +=== Vector-vector add example + +---- +include::example/vvaddint32.s[lines=4..-1] +---- + +=== Example with mixed-width mask and compute. + +---- +# Code using one width for predicate and different width for masked +# compute. +# int8_t a[]; int32_t b[], c[]; +# for (i=0; i<n; i++) { b[i] = (a[i] < 5) ? c[i] : 1; } +# +# Mixed-width code that keeps SEW/LMUL=8 + loop: + vsetvli a4, a0, e8, m1, ta, ma # Byte vector for predicate calc + vle8.v v1, (a1) # Load a[i] + add a1, a1, a4 # Bump pointer. + vmslt.vi v0, v1, 5 # a[i] < 5? + + vsetvli x0, a0, e32, m4, ta, mu # Vector of 32-bit values. + sub a0, a0, a4 # Decrement count + vmv.v.i v4, 1 # Splat immediate to destination + vle32.v v4, (a3), v0.t # Load requested elements of C, others undisturbed + sll t1, a4, 2 + add a3, a3, t1 # Bump pointer. + vse32.v v4, (a2) # Store b[i]. + add a2, a2, t1 # Bump pointer. + bnez a0, loop # Any more? +---- + +=== Memcpy example + +---- +include::example/memcpy.s[lines=4..-1] +---- + +=== Conditional example + +---- +# (int16) z[i] = ((int8) x[i] < 5) ? (int16) a[i] : (int16) b[i]; +# + +loop: + vsetvli t0, a0, e8, m1, ta, ma # Use 8b elements. + vle8.v v0, (a1) # Get x[i] + sub a0, a0, t0 # Decrement element count + add a1, a1, t0 # x[i] Bump pointer + vmslt.vi v0, v0, 5 # Set mask in v0 + vsetvli x0, x0, e16, m2, ta, mu # Use 16b elements. + slli t0, t0, 1 # Multiply by 2 bytes + vle16.v v2, (a2), v0.t # z[i] = a[i] case + vmnot.m v0, v0 # Invert v0 + add a2, a2, t0 # a[i] bump pointer + vle16.v v2, (a3), v0.t # z[i] = b[i] case + add a3, a3, t0 # b[i] bump pointer + vse16.v v2, (a4) # Store z + add a4, a4, t0 # z[i] bump pointer + bnez a0, loop +---- +=== SAXPY example + +---- +include::example/saxpy.s[lines=4..-1] +---- + +=== SGEMM example + +---- +include::example/sgemm.S[lines=4..-1] +---- + +=== Division approximation example + +---- +# v1 = v1 / v2 to almost 23 bits of precision. + +vfrec7.v v3, v2 # Estimate 1/v2 + li t0, 0x40000000 +vmv.v.x v4, t0 # Splat 2.0 +vfnmsac.vv v4, v2, v3 # 2.0 - v2 * est(1/v2) +vfmul.vv v3, v3, v4 # Better estimate of 1/v2 +vmv.v.x v4, t0 # Splat 2.0 +vfnmsac.vv v4, v2, v3 # 2.0 - v2 * est(1/v2) +vfmul.vv v3, v3, v4 # Better estimate of 1/v2 +vfmul.vv v1, v1, v3 # Estimate of v1/v2 +---- + +=== Square root approximation example + +---- +# v1 = sqrt(v1) to almost 23 bits of precision. + + fmv.w.x ft0, x0 # Mask off zero inputs +vmfne.vf v0, v1, ft0 # to avoid div by zero +vfrsqrt7.v v2, v1, v0.t # Estimate 1/sqrt(x) +vmfne.vf v0, v2, ft0, v0.t # Additionally mask off +inf inputs + li t0, 0x40400000 +vmv.v.x v4, t0 # Splat 3.0 +vfmul.vv v3, v1, v2, v0.t # x * est +vfnmsub.vv v3, v2, v4, v0.t # - x * est * est + 3 +vfmul.vv v3, v3, v2, v0.t # est * (-x * est * est + 3) + li t0, 0x3f000000 + fmv.w.x ft0, t0 # 0.5 +vfmul.vf v2, v3, ft0, v0.t # Estimate to 14 bits +vfmul.vv v3, v1, v2, v0.t # x * est +vfnmsub.vv v3, v2, v4, v0.t # - x * est * est + 3 +vfmul.vv v3, v3, v2, v0.t # est * (-x * est * est + 3) +vfmul.vf v2, v3, ft0, v0.t # Estimate to 23 bits +vfmul.vv v1, v2, v1, v0.t # x * 1/sqrt(x) +---- + +=== C standard library strcmp example + +---- +include::example/strcmp.s[lines=4..-1] +---- + +include::fraclmul.adoc[] diff --git a/src/zacas.adoc b/src/zacas.adoc new file mode 100644 index 0000000..ebb7942 --- /dev/null +++ b/src/zacas.adoc @@ -0,0 +1,260 @@ +== Atomic Compare-and-Swap (CAS) instructions (Zacas), Version 1.0.0 + +=== Introduction + +Compare-and-Swap (CAS) provides an easy and typically faster way to perform +thread synchronization operations when supported as a hardware instruction. CAS +is typically used by lock-free and wait-free algorithms. This extension proposes +CAS instructions to operate on 32-bit, 64-bit, and 128-bit (RV64 only) data +values. The CAS instruction supports the C++11 atomic compare and exchange +operation. + +While compare-and-swap for XLEN wide data may be accomplished using LR/SC, the +CAS atomic instructions scale better to highly parallel systems than LR/SC. +Many lock-free algorithms, such as a lock-free queue, require manipulation of +pointer variables. A simple CAS operation may not be sufficient to guard against +what is commonly referred to as the ABA problem in such algorithms that +manipulate pointer variables. To avoid the ABA problem, the algorithms associate +a reference counter with the pointer variable and perform updates using a +quadword compare and swap (of both the pointer and the counter). The double and +quadword CAS instructions support implementation of algorithms for ABA problem +avoidance. + +The Zacas extension depends upon the A extension cite:[unpriv]. + +[[chapter2]] +=== Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) + +[wavedrom, , ] +.... +{reg: [ + {bits: 7, name: 'opcode', attr:'AMO'}, + {bits: 5, name: 'rd', attr:'dest'}, + {bits: 3, name: 'funct3', attr:['010', '011', '100']}, + {bits: 5, name: 'rs1', attr:'addr'}, + {bits: 5, name: 'rs2', attr:'src'}, + {bits: 1, name: 'rl'}, + {bits: 1, name: 'aq'}, + {bits: 5, name: '00101', attr:['AMOCAS.W', 'AMOCAS.D', 'AMOCAS.Q']}, +], config:{lanes: 1, hspace:1024}} +.... + +For RV32, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, +compares the loaded value to the 32-bit value held in `rd`, and if the comparison +is bitwise equal, then stores the 32-bit value held in `rs2` to the original +address in `rs1`. The value loaded from memory is placed into register `rd`. The +operation performed by `AMOCAS.W` for RV32 is as follows: + +[listing] +---- + temp = mem[X(rs1)] + if ( temp == X(rd) ) + mem[X(rs1)] = X(rs2) + X(rd) = temp +---- + +`AMOCAS.D` is similar to `AMOCAS.W` but operates on 64-bit data values. + +For RV32, `AMOCAS.D` atomically loads 64-bits of a data value from address in +`rs1`, compares the loaded value to a 64-bit value held in a register pair +consisting of `rd` and `rd+1`, and if the comparison is bitwise equal, then +stores the 64-bit value held in the register pair `rs2` and `rs2+1` to the +original address in `rs1`. The value loaded from memory is placed into the +register pair `rd` and `rd+1`. The instruction requires the first register in +the pair to be even numbered; encodings with odd numbered registers specified +in `rs2` and `rd` are reserved. When the first register of a source register +pair is `x0`, then both halves of the pair read as zero. When the first +register of a destination register pair is `x0`, then the entire register +result is discarded and neither destination register is written. +The operation performed by `AMOCAS.D` for RV32 is as follows: +[listing] + temp0 = mem[X(rs1)+0] + temp1 = mem[X(rs1)+4] + comp0 = (rd == x0) ? 0 : X(rd) + comp1 = (rd == x0) ? 0 : X(rd+1) + swap0 = (rs2 == x0) ? 0 : X(rs2) + swap1 = (rs2 == x0) ? 0 : X(rs2+1) + if ( temp0 == comp0 ) && ( temp1 == comp1 ) + mem[X(rs1)+0] = swap0 + mem[X(rs1)+4] = swap1 + endif + if ( rd != x0 ) + X(rd) = temp0 + X(rd+1) = temp1 + endif + +For RV64, `AMOCAS.W` atomically loads a 32-bit data value from address in +`rs1`, compares the loaded value to the lower 32 bits of the value held in `rd`, +and if the comparison is bitwise equal, then stores the lower 32 bits of the +value held in `rs2` to the original address in `rs1`. The 32-bit value loaded +from memory is sign-extended and is placed into register `rd`. The operation +performed by `AMOCAS.W` for RV64 is as follows: + +[listing] + temp[31:0] = mem[X(rs1)] + if ( temp[31:0] == X(rd)[31:0] ) + mem[X(rs1)] = X(rs2)[31:0] + X(rd) = SignExtend(temp[31:0]) + +For RV64, `AMOCAS.D` atomically loads 64-bits of a data value from address in +`rs1`, compares the loaded value to a 64-bit value held in `rd`, and if the +comparison is bitwise equal, then stores the 64-bit value held in `rs2` to the +original address in `rs1`. The value loaded from memory is placed into register +`rd`. The operation performed by `AMOCAS.D` for RV64 is as follows: +[listing] + temp = mem[X(rs1)] + if ( temp == X(rd) ) + mem[X(rs1)] = X(rs2) + X(rd) = temp + +`AMOCAS.Q` (RV64 only) atomically loads 128-bits of a data value from address in +`rs1`, compares the loaded value to a 128-bit value held in a register pair +consisting of `rd` and `rd+1`, and if the comparison is bitwise equal, then +stores the 128-bit value held in the register pair `rs2` and `rs2+1` to the +original address in `rs1`. The value loaded from memory is placed into the +register pair `rd` and `rd+1`. The instruction requires the first register in +the pair to be even numbered; encodings with odd numbered registers specified in +`rs2` and `rd` are reserved. When the first register of a source register pair +is `x0`, then both halves of the pair read as zero. When the first register of a +destination register pair is `x0`, then the entire register result is discarded +and neither destination register is written. The operation performed by +`AMOCAS.Q` is as follows: +[listing] + temp0 = mem[X(rs1)+0] + temp1 = mem[X(rs1)+8] + comp0 = (rd == x0) ? 0 : X(rd) + comp1 = (rd == x0) ? 0 : X(rd+1) + swap0 = (rs2 == x0) ? 0 : X(rs2) + swap1 = (rs2 == x0) ? 0 : X(rs2+1) + if ( temp0 == comp0 ) && ( temp1 == comp1 ) + mem[X(rs1)+0] = swap0 + mem[X(rs1)+8] = swap1 + endif + if ( rd != x0 ) + X(rd) = temp0 + X(rd+1) = temp1 + endif + +[NOTE] +==== +For a future RV128 extension, `AMOCAS.Q` would encode a single XLEN=128 register +in `rs2` and `rd`. +==== + +[NOTE] +==== +Some algorithms may load the previous data value of a memory location into the +register used as the compare data value source by a Zacas instruction. When +using a Zacas instruction that uses a register pair to source the compare value, +the two registers may be loaded using two individual loads. The two individual +loads may read an inconsistent pair of values but that is not an issue since the +`AMOCAS` operation itself uses an atomic load-pair from memory to obtain the +data value for its comparison. + +The following example code sequence illustrates the use of `AMOCAS.D` in a RV32 +implementation to atomically increment a 64-bit counter. +[listing] +# a0 - address of the counter. +increment: + lw a2, (a0) # Load current counter value using + lw a3, 4(a0) # two individual loads. +retry: + mv a6, a2 # Save the low 32 bits of the current value. + mv a7, a3 # Save the high 32 bits of the current value. + addi a4, a2, 1 # Increment the low 32 bits. + sltu a1, a4, a2 # Determine if there is a carry out. + add a5, a3, a1 # Add the carry if any to high 32 bits. + amocas.d.aqrl a2, a4, (a0) + bne a2, a6, retry # If amocas.d failed then retry + bne a3, a7, retry # using current values loaded by amocas.d. + ret +==== + +Just as for AMOs in the A extension, `AMOCAS.W/D/Q` requires that the address +held in `rs1` be naturally aligned to the size of the operand (i.e., 16-byte +aligned for _quadwords_, eight-byte aligned for _doublewords_, and four-byte +aligned for _words_). And the same exception options apply if the address +is not naturally aligned. + +Just as for AMOs in the A extension, the `AMOCAS.W/D/Q` optionally provide +release consistency semantics, using the `aq` and `rl` bits, to help implement +multiprocessor synchronization. The memory operation performed by an +`AMOCAS.W/D/Q`, when successful, has acquire semantics if `aq` bit is 1 and has +release semantics if `rl` bit is 1. The memory operation performed by an +`AMOCAS.W/D/Q`, when not successful, has acquire semantics if `aq` bit is 1 but +does not have release semantics, regardless of `rl`. + +A FENCE instruction may be used to order the memory read access and, if +produced, the memory write access by an `AMOCAS.W/D/Q` instruction. + +[NOTE] +==== +An unsuccessful `AMOCAS.W/D/Q` may either not perform a memory write or may +write back the old value loaded from memory. The memory write, if produced, does +not have release semantics, regardless of `rl`. +==== + +An `AMOCAS.W/D/Q` instruction always requires write permissions. + +<<< + +[NOTE] +==== +The following example code sequence illustrates the use of `AMOCAS.Q` to +implement the _enqueue_ operation for a non-blocking concurrent queue using the +algorithm outlined in cite:[queue]. The algorithm atomically operates on a +pointer and its associated modification counter using the `AMOCAS.Q` instruction +to avoid the ABA problem. + +[listing] +# Enqueue operation of a non-blocking concurrent queue. +# Data structures used by the queue: +# structure pointer_t {ptr: node_t *, count: uint64_t} +# structure node_t {next: pointer_t, value: data type} +# structure queue_t {Head: pointer_t, Tail: pointer_t} +# Inputs to the procedure: +# a0 - address of Tail variable +# a4 - address of a new node to insert at tail +enqueue: + ld a6, (a0) # a6 = Tail.ptr + ld a7, 8(a0) # a7 = Tail.count + ld a2, (a6) # a2 = Tail.ptr->next.ptr + ld a3, 8(a6) # a3 = Tail.ptr->next.count + ld t1, (a0) + ld t2, 8(a0) + bne a6, t1, enqueue # Retry if Tail & next are not consistent + bne a7, t2, enqueue # Retry if Tail & next are not consistent + bne a2, x0, move_tail # Was tail pointing to the last node? + mv t1, a2 # Save Tail.ptr->next.ptr + mv t2, a3 # Save Tail.ptr->next.count + addi a5, a3, 1 # Link the node at the end of the list + amocas.q.aqrl a2, a4, (a6) + bne a2, t1, enqueue # Retry if CAS failed + bne a3, t2, enqueue # Retry if CAS failed + addi a5, a7, 1 # Update Tail to the inserted node + amocas.q.aqrl a6, a4, (a0) + ret # Enqueue done +move_tail: # Tail was not pointing to the last node + addi a3, a7, 1 # Try to swing Tail to the next node + amocas.q.aqrl a6, a2, (a0) + j enqueue # Retry + +==== + +=== Additional AMO PMAs + +There are four levels of PMA support defined for AMOs in the A extension. Zacas +defines three additional levels of support: `AMOCASW`, `AMOCASD`, and `AMOCASQ`. + +`AMOCASW` indicates that in addition to instructions indicated by `AMOArithmetic` +level support, the `AMOCAS.W` instruction is supported. `AMOCASD` indicates that +in addition to instructions indicated by `AMOCASW` level support, the `AMOCAS.D` +instruction is supported. `AMOCASQ` indicates that in addition to instructions +indicated by `AMOCASD` level support, the `AMOCAS.Q` instruction is supported. + +[NOTE] +==== +`AMOCASW/D/Q` require `AMOArithmetic` level support as the `AMOCAS.W/D/Q` +instructions require ability to perform an arithmetic comparison and a swap +operation. +==== |
