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authorVed Shanbhogue <ved@rivosinc.com>2024-03-25 13:30:55 -0500
committerbeeman <beeman@rivosinc.com>2024-03-25 14:12:39 -0700
commit9f9130e45e1f103047e068d859dd818047eaefcc (patch)
tree88aecf903690274949541a42ff5474413ad4e5fd
parentc601e5032822bee4e3041bbc5882430c1245ef27 (diff)
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Add B standard extension
-rw-r--r--src/b-st-ext.adoc5
-rw-r--r--src/machine.adoc6
-rw-r--r--src/naming.adoc2
3 files changed, 11 insertions, 2 deletions
diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc
index 52beb61..81ec997 100644
--- a/src/b-st-ext.adoc
+++ b/src/b-st-ext.adoc
@@ -1,6 +1,9 @@
[[bits]]
== "B" Standard Extension for Bit Manipulation, Version 1.0.0
+The B standard extension comprises instructions provided by the Zba, Zbb, and
+Zbs extensions.
+
[[preface]]
=== Bit-manipulation a, b, c and s extensions grouped for public review and ratification
@@ -3898,4 +3901,4 @@ strcmp:
ret
.size strcmp, .-strcmp
--- \ No newline at end of file
+--
diff --git a/src/machine.adoc b/src/machine.adoc
index 42012ac..21e4083 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -156,7 +156,7 @@ X +
Y +
Z
|Atomic extension +
-_Reserved_ +
+B extension +
Compressed extension +
Double-precision floating-point extension +
RV32E/64E base ISA +
@@ -192,6 +192,10 @@ supervisor modes respectively.
The "X" bit will be set if there are any non-standard extensions.
+When "B" bit is 1, the implementation supports the instructions provided by the
+Zba, Zbb, and Zbs extensions. When "B" bit is 0, it indicates that the
+implementation may not support one or more of the Zba, Zbb, or Zbs extensions.
+
[NOTE]
====
The `misa` CSR exposes a rudimentary catalog of CPU features to
diff --git a/src/naming.adoc b/src/naming.adoc
index f597733..63c45d3 100644
--- a/src/naming.adoc
+++ b/src/naming.adoc
@@ -182,6 +182,8 @@ e.g., RV32IMACV is legal, whereas RV32IMAVC is not.
|16-bit Compressed Instructions |C |
+|B Extension |B |
+
|Packed-SIMD Extensions |P |
|Vector Extension |V |D