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| author | Andrew Waterman <andrew@sifive.com> | 2024-03-20 16:46:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-20 16:46:18 -0700 |
| commit | 14a3f0983754b9df83ee52ba274e7d93d17012bc (patch) | |
| tree | 2cb5a6b6b5029c9a6576781acd101f7739efb435 | |
| parent | 78e0c5d896c05a174bebb3f41644dedb25a8e137 (diff) | |
| parent | 54ed5b9a3bb1f9c02e89d1f6d93c9f68b3f2961c (diff) | |
| download | riscv-isa-manual-14a3f0983754b9df83ee52ba274e7d93d17012bc.zip riscv-isa-manual-14a3f0983754b9df83ee52ba274e7d93d17012bc.tar.gz riscv-isa-manual-14a3f0983754b9df83ee52ba274e7d93d17012bc.tar.bz2 | |
Merge pull request #1278 from riscv/priv-tocriscv-isa-release-14a3f09-2024-03-20
Reorder priv spec chapters and fix other ToC issues
| -rw-r--r-- | src/riscv-privileged.adoc | 8 | ||||
| -rw-r--r-- | src/sscofpmf.adoc (renamed from src/sscofpmt.adoc) | 0 | ||||
| -rw-r--r-- | src/sstc.adoc | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/riscv-privileged.adoc b/src/riscv-privileged.adoc index 1677ec4..3d46280 100644 --- a/src/riscv-privileged.adoc +++ b/src/riscv-privileged.adoc @@ -82,14 +82,14 @@ include::priv-intro.adoc[] include::priv-csrs.adoc[] include::machine.adoc[] include::smstateen.adoc[] +include::indirect-csr.adoc[] include::smepmp.adoc[] +include::smcntrpmf.adoc[] include::rnmi.adoc[] include::supervisor.adoc[] -include::sscofpmt.adoc[] -include::smcntrpmf.adoc[] -include::hypervisor.adoc[] include::sstc.adoc[] -include::indirect-csr.adoc[] +include::sscofpmf.adoc[] +include::hypervisor.adoc[] include::priv-insns.adoc[] include::priv-history.adoc[] include::bibliography.adoc[] diff --git a/src/sscofpmt.adoc b/src/sscofpmf.adoc index 101c15f..101c15f 100644 --- a/src/sscofpmt.adoc +++ b/src/sscofpmf.adoc diff --git a/src/sstc.adoc b/src/sstc.adoc index 8e7a8e7..b0e3738 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -1,5 +1,5 @@ [[Sstc]] -== "Stimecmp/Vstimecmp" Extension, Version 1.0.0 +== Sstc Standard Extension for Supervisor-mode Timer Interrupts, Version 1.0.0 The current Privileged arch specification only defines a hardware mechanism for generating machine-mode timer interrupts (based on the mtime and mtimecmp @@ -187,4 +187,4 @@ if this extension is not implemented. When STCE in menvcfg is one but STCE in henvcfg is zero, an attempt to access stimecmp (really vstimecmp) when V = 1 raises a virtual instruction exception, and VSTIP in hip reverts to its defined behavior as if this extension is not -implemented.
\ No newline at end of file +implemented. |