Removed obsolete commentary.

1 files changed, 0 insertions, 11 deletions

diff --git a/src/a.tex b/src/a.tex
index 7b846ec..b2bd899 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -51,17 +51,6 @@ observed to happen before any earlier memory operations or after any
 later memory operations in the same RISC-V hart and to the same
 address domain.
 
-\begin{commentary}
-Theoretically, the definition of the {\em aq} and {\em rl} bits allows
-for implementations without global store atomicity.  When both {\em
-  aq} and {\em rl} bits are set, however, we require full sequential
-consistency for the atomic operation which implies global store
-atomicity in addition to both acquire and release semantics.  In
-practice, hardware systems are usually implemented with global store
-atomicity, embodied in local processor ordering rules together with
-single-writer cache coherence protocols.
-\end{commentary}
-
 \section{Load-Reserved/Store-Conditional Instructions}
 \label{sec:lrsc}