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author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 18:26:59 -0700 |
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committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 18:26:59 -0700 |
commit | dfdf1ff8439bffc3142dd8bd67939f7dff4361e4 (patch) | |
tree | 6b310b3ea9b900a1f74828c67e8c3beeea06364a | |
parent | aba09b1c9225ddf4f388a42fb87b898e6624d4c9 (diff) | |
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Removed obsolete commentary.
-rw-r--r-- | src/a.tex | 11 |
1 files changed, 0 insertions, 11 deletions
@@ -51,17 +51,6 @@ observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain. -\begin{commentary} -Theoretically, the definition of the {\em aq} and {\em rl} bits allows -for implementations without global store atomicity. When both {\em - aq} and {\em rl} bits are set, however, we require full sequential -consistency for the atomic operation which implies global store -atomicity in addition to both acquire and release semantics. In -practice, hardware systems are usually implemented with global store -atomicity, embodied in local processor ordering rules together with -single-writer cache coherence protocols. -\end{commentary} - \section{Load-Reserved/Store-Conditional Instructions} \label{sec:lrsc} |