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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-24 16:24:48 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-24 16:25:40 -0700 |
| commit | ca838c12b0bf61824e62eba60050a4dbc2604698 (patch) | |
| tree | 21cf415bc281459a3de1fe608f3fd783baec078e | |
| parent | 4c6ee856fcd8576d582a14b55fdab4e72483a804 (diff) | |
| download | riscv-isa-manual-ca838c12b0bf61824e62eba60050a4dbc2604698.zip riscv-isa-manual-ca838c12b0bf61824e62eba60050a4dbc2604698.tar.gz riscv-isa-manual-ca838c12b0bf61824e62eba60050a4dbc2604698.tar.bz2 | |
SFENCE behavior is independent of privilege mode
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/machine.tex b/src/machine.tex index ba1e1aa..438f75a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2981,9 +2981,7 @@ that affects either the physical memory that holds the page tables or the physical memory to which the page tables point, M-mode software must synchronize the PMP settings with the virtual memory system. This is accomplished by executing an SFENCE.VMA instruction with {\em rs1}={\tt x0} -and {\em rs2}={\tt x0}, after the PMP CSRs are written. Note, SFENCE.VMA is -only guaranteed to synchronize the PMP settings with the virtual memory system -when it is executed in M-mode. +and {\em rs2}={\tt x0}, after the PMP CSRs are written. If page-based virtual memory is not implemented, or when it is disabled, memory accesses check the PMP settings synchronously, so no fence is needed. |